JPH04186591A - Dynamic semiconductor memory - Google Patents

Abstract

PURPOSE:To easily rewrite vertical information of a screen by holding a column address content in a register during activation of a column address register control signal. CONSTITUTION:When a vertical address register control signal is activated before a vertical address strobe signal is activated, a signal is input to an address register controller 110, and initial input address to the register 112 is latched. Then, the address of a lateral address counter 111 is counted, and output to a lateral decoder 104. When the vertical address data are fixed, the vertical address is automatically supplied when the lateral address is thereafter sequentially varied, high speed continuous accessing in a bit line direction is performed, and vertical data rewriting of a screen is facilitated in an image processing. The latched vertical address data is reset in its content only at the time of inactivation of the vertical address register control signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a dynamic semiconductor memory device, and in particular to a column address register that latches a column address and a column address register control signal that controls this register. This relates to the column register control unit that inputs the data.

[Conventional technology]

In conventional dynamic semiconductor memory devices, when performing high-speed continuous access in page mode or high-speed page mode, as shown in Figure 4, row addresses are stored in memory in synchronization with the falling edge of the row address strobe signal. After that, the column addresses are continuously input to the memory in synchronization with the falling edge of the column address stroke signal. In this mode, the internal operation of the memory is to internally latch the row address at the falling edge of the row address stroke signal and decode the address data using the row decoder. Next, a column address is captured by a change in address data, and at the same time the column decoder starts decoding the column address, and the column address is latched at the falling edge of the column address strobe signal.

FIG. 5 shows a block diagram of a conventional dynamic semiconductor memory device. In this figure, 501... row address strobe signal control section and 502... column address control section.
The address strobe signal control section receives the row address strobe signal and the column address strobe signal, and supplies the row address and column address latches, 504 . . . row decoder, 506 .
...Control address decoding in the column decoder. According to the decoded address data, 508...
・Word lines and bit lines in the memory array are activated.

[Problem to be solved by the invention]

In this conventional dynamic semiconductor memory device, in a high-speed access mode such as the above-mentioned page mode or high-speed page mode, as a basic operation, all memory cells on the word line selected by the first row address input are Columns to be activated and then input continuously
Being selected by an address Since each memory cell on a word line is subject to read and write operations in sequence, continuous access is performed only on the word line selected by a single row address, as shown in Figure 6. The problem was that I couldn't do it.

[Means for Solving the Problems] In the dynamic semiconductor memory device of the present invention, column
a column address register to latch the address;
A column address register control section that controls this register, a column address register control signal input terminal,
When the column address register control signal and column address register control signal are active, the row address register control signal automatically increments the row address and presses address data into the row decoder by toggling the row address stroke signal. It has a counter.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of the inside of a dynamic semiconductor memory device according to an embodiment of the present invention. These internal operations will be explained using FIGS. 1 and 2. When the row address strobe signal is activated, the row address that has passed through the address buffer 103 in FIG. 1 becomes the row address 111...
After passing through the address counter, it is decoded by a row decoder 104, and the selected word line is activated.

Next, the column address is captured due to a change in address data, and at the same time the column decoder starts decoding the column address, and the column address is latched at the falling edge of the column address strobe signal. When the column address register control signal is activated as shown in FIG. 2 before this column address strobe signal is activated, a signal is input to the column address register control section 110... - Latch the first column address input to the address register. Next, by toggling the row address strobe signal, the row address in the row address counter is counted up and output to the row decoder. By fixing the column address data in this way, when the row address changes sequentially from subsequent memory access cycles, the column address is automatically supplied inside the memory and the bits as shown in Figure 3 are Continuous access in the linear direction is possible. In this continuous access, the operation of the column decoder is reset by deactivating the four address strobe signals. When the next row address is supplied, the latched column address is reset to the column decoder again. is supplied to The column address data latched in the column address register is not reset on the rising edge of the row address strobe signal on each cycle while the column address register control signal is active;
111...The contents of the register are reset only when the column address register control signal is inactivated (at the rising edge of the signal in FIG. 2).

〔Effect of the invention〕

As explained above, the present invention has a built-in column register, and while the column address register control signal is active, it is possible to latch the column address and automatically increment the row address. So,
This enables high-speed continuous access in the bit line direction as shown in FIG. 3, and has the effect that data in the vertical direction of the screen can be easily rewritten in image processing and the like.

For example, the read/write cycle time of conventional products is 1
In the case of 50 ns, the present invention can reduce the read/write cycle time by about 10 ns to 15 ns, and the performance improves by about 10%.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing diagram of the embodiment, and FIG. 3 is a simplified diagram representing the access method of the embodiment. Also, FIG. 4 is a timing chart of a conventional page mode, FIG. 5 is a block diagram of a conventional dynamic semiconductor memory device, and FIG. 6 is a simplified diagram of a conventional page mode access method. It is. In Figures 3 and 6, 301, 601...
Memory array, 302, 602... Row decoder, 303, 603... Column decoder. In FIG. 1, 101...Row address strobe signal control section, 102...Column address strobe signal control section, 103...Address buffer,
104...Row decoder, 105...
・I10 data bus, 106...Column decoder, 107...Sense amplifier, 108...
. . . Memory array, 109 . . . 10 buffers, 110 . . . Column address register control section, 111 . . . Four address counters, 112. ...Al in column address register. Further, in FIG. 5, 501... Row address strobe 7' signal control section, 502... Column address strobe signal control section, 503... Address・Buffer, 504...Row decoder, 505...
...I10 data bus, 506 ... column decoder, 507 ... sense amplifier, 5
08... Memory array, 509... Engineering 10 buffer. Agent Patent Attorney Uchi Hara Syllable 1 / θj /, '7 7# Figure 2 IFJ 3 Figure

Claims (1)

[Claims] A dynamic semiconductor memory device comprising a built-in column address register and retaining the contents of the column address while a column address register control signal is activated.