JPH0474057A - Signal processor - Google Patents

Abstract

PURPOSE:To output video signals separately one by one page at a low speed vari-speed reproduction by adopting the constitution such that 1st and 2nd memories are used to control error correction, special reproduction processing and signal rearrangement and time axis adjustment. CONSTITUTION:Only signals of n-th page and (n+l)th page are selected by a gate 22a and written in a 1st memory 23a and signals of the n-th page are selected by a gate 22b and written in a 1st memory 23b. After the signal of the n-th page is finished, the gate 22a selects only the signal of (n+l)th page and writes it in the 1st memory 23a, the 1st memory 23b reads the signal of the n-th page and an outputted signal is subject to high efficient code decoding at a high efficient decoder 24 and written in an area corresponding to the 2nd memory 25b. After the write is finished, the gate 22b selects only signals of (n+l)th page and (n+2)th page and written in the 1st memory 23a, the 2nd memory 25a finishes reading the signal of (n-1)th page and the n-th page signal is outputted from the 2nd memory 25b to an output terminal 26 as an original digital video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing device used for recording, reproducing, or transmitting highly efficiently encoded digital video signals.

Conventional technology When high-efficiency encoding of digital video processing is performed, methods that utilize correlation in the time axis direction, methods that perform motion detection, or correlation within one page (one page represents one field or multiple fields) are used. Generally, methods require sorting in order to be used, and each method requires at least two
Requires more memory than pages.

On the other hand, when recording, reproducing, or transmitting a digital video signal encoded with high efficiency, if one error is detected, a signal in a certain range of the screen cannot be obtained, so surrounding pixels on the same page are used. Since it is not possible to perform retouching and the retouching must be performed using pixels from the previous and following pages, a memory is required in page units. Furthermore, when performing low-speed repeating, high-speed playback, etc., the input order of signals is different from normal playback and becomes irregular, so three pages of memory are required to reconstruct the video signals of each page.

Problems to be Solved by the Invention However, the above configuration requires an extremely large amount of memory. In view of this point, it is an object of the present invention to provide a signal processing device with a small memory capacity.

Means for Solving the Problems The present invention includes a first memory capable of storing a reproduced signal in a highly efficient encoded state on a screen-by-screen basis, and a high efficiency memory that performs highly efficient decoding of the signal output from the first memory. The present invention is characterized by comprising a decoding means, a second memory capable of storing the signal output from the high efficiency decoding means on a screen-by-screen basis, and a control means for controlling the first memory and the second memory. .

According to the present invention, a signal processing device with a small memory capacity is constructed by synchronizing the first memory and the second memory and using them for error correction, special reproduction processing, signal rearrangement, and time axis adjustment.

Embodiment A first embodiment of the present invention, which is a signal processing apparatus for signals reproduced and error-corrected in a device for recording and reproducing digital video signals by highly efficient encoding page by page, will be described below. FIG. 1 is a block diagram of a signal processing device according to a first embodiment of the present invention. In FIG. 1, 11 is an input terminal, 12 is a first memory with a capacity of one page, 13 is a selector, 14 is a high-efficiency decoder, 15a, 1
5b is a second memory each having a capacity of one page, and 16 is an output terminal. If the compression rate of the high-efficiency decoder 14 is N, the capacity of the first memory 12 is 1/1/2 of the capacity of each second memory.
It is N.

The operation of the signal processing device of this embodiment configured as described above will be described below. An error detection signal is added to the signal input to the input terminal 11, and by writing only the signal in which no error was detected to the first memory 12, the first memory 12 detects the error in the data one page before. A signal is obtained with the substitution of . It is assumed that the error detection signal is also written into the first memory 12 at the same time, and writing of the signals up to n pages is now completed. When the signal of the n+l page is input to the input terminal 11, the first memory 12 reads out the signal at the same position on the screen as that signal, and then writes the input signal based on the error detection signal. In the selector 13,
If the signal read from the first memory 12 is a signal in which no error has been detected, it is output as is. Also, the signal is an error detected and replaced with the signal from one page before, and
If it is better to replace the signal with the signal one page later than with the signal from the previous page, the signal from the input terminal 11 is output. Therefore, the signal from the first memory 12 is output. The signal output from the selector 13 is decoded into a high-efficiency code by the high-efficiency decoder 14, and then stored in the second memory 15a.
write to the corresponding position. The writing/reading of the second memory 15a and the second memory 15b is switched for each page, and the signal of the n-1 page is outputted from the output terminal 16 as the original digital video signal. Second memory 15a, 15
In step b, signal rearrangement and time axis adjustment are also performed.According to this embodiment, the memory of 2 pages and 1/N page constitutes a signal processing device that can adaptively correct errors from the previous and next pages. can do. Note that in this example, 1
This is an example, and error correction processing is possible with a similar configuration. For example, if there are 2 pages and 2/N pages of memory, errors can be adaptively corrected by comparing the previous and next pages. It is also possible to perform error correction processing in the second memory, and it is also possible to perform time axis adjustment in the first memory.

FIG. 2 is a block diagram of a signal processing device according to a second embodiment of the present invention, and FIG. 3 is a timing chart of the same signal processing device during 1/3 speed playback. In FIG. 2, 21 is an input terminal, 22a and 22b are gates, 23a and 23b are first memories each with a capacity of one page, 24 is a high efficiency decoder, and 25a and 25b are second memories each with a capacity of one page. Memory 26 is an output terminal. If the compression rate of the high-efficiency decoder 24 is N, then the capacity of each first memory is 1/N of the capacity of each second memory.

The operation of the signal processing device for low-speed playback according to the present embodiment configured as described above will be described below. Here 1
/3 times the speed, and each page of the reproduced digital video signal is output repeatedly three times. Input terminal 1
Unlike during normal playback, the signals input to 1 have no regular order and are not arranged in units of pages. Therefore, the gate 22a selects only the signals of the n page and the n+1 page and writes them into the first memory 23a, and the gates 1-22b
selects only the n-page signals and writes them into the first memory 23b. After the n page signals are completed, the gate 22a
Only the +1 page signal is selected and written to the first memory 23a, the first memory 23b reads the n page signal, and the output signal is decoded into a high efficiency code by the high efficiency decoder 24. Write to the corresponding location in the second memory 25b. After this writing is completed, the gate 22b selects only the signals of the n+1 page and the n+2 page and writes the signals to the first memory 2.
3a, the second memory 25a finishes reading the n-1 page of signals, and the second memory 25b reads n-1 signals.
The page signal begins to be output from the output terminal 26 as the original digital video signal. The second memories 25a and 25b also perform signal rearrangement and time axis adjustment. As shown in FIG. 3, writing/reading can be controlled every six pages. As described above, according to this embodiment, it is possible to configure a signal processing device that can separate and output a video signal page by page during low-speed variable speed playback using the 2-page and 2/N-page memories.

Note that this embodiment is just one example, and special playback processing can be performed with a similar configuration. Furthermore, a configuration combining the two embodiments described above is also possible.

As described in detail, according to the present invention, a signal processing device capable of error correction, special reproduction processing, signal rearrangement, and time axis adjustment can be realized with a configuration with a small memory capacity. It can be done, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal processing device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a signal processing device according to a second embodiment of the present invention, and FIG. 3 is a 1/3-speed playback This is a timing chart of the time. 11, 21... Input terminal, 12.23a, 2
3b...First memory with a capacity of 1 page, 13.
...Selector, 14.24...High efficiency decoder, 15a, 15b, 25a, 25b...Second memory, each with a capacity of one page, 16.26.・・・
...output terminal, 22a, 22b...gate. Name of agent: Patent attorney Shigetaka Awano Figure 1! ,7 Figure 2

Claims (5)

[Claims] (1) When a digital video signal is highly efficiently encoded and recorded or transmitted, a first memory capable of storing a reproduced signal or a received signal in a highly efficiently encoded state on a screen-by-screen basis; and the first memory; a second memory capable of storing the signal output from the high efficiency decoding means on a screen-by-screen basis;
A signal processing device comprising a control means for controlling error correction, special playback processing, signal rearrangement, and time axis adjustment using the first memory and the second memory. (2) Claim (1) characterized in that when one page of a digital video signal is composed of one field or a plurality of fields, the capacity of the first memory is within two pages.
) Signal processing device. (3) The signal processing device according to claim (1) or (2), wherein the second memory has a capacity of two pages or less. (4) The first memory is memory 2 with a capacity of 1 page.
3. The signal processing device according to claim 2, wherein the signal processing device is comprised of: (5) The signal processing device according to claim 3, wherein the second memory is composed of two memories each having a capacity of one page.