JPH0479683A - Signal processor - Google Patents

Abstract

PURPOSE:To reduce the memory capacity of a signal processor by controlling error correction, special reproducing process, signal rearrangement, and time base adjustment with plural memories. CONSTITUTION:An error detecting signal is added to signals inputted to an input terminal 11 and, by only writing signals from which no error is detected in the 1st memory 12, signals in which errors are replaced with the data of preceding pages are obtained in the memory 12. At the same time, signals are successively read out at the 2nd memory 13 in the order of output and the signals at the same position as that of the successively read out signals on a screen are written in the memory 13 while the signals are read out from the memory 12. Therefore, a signal processor which can make error correction, special reproducing process, signal rearrangement, and time base adjustment can be constituted with a smaller memory capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing device used for recording, reproducing, or transmitting digital video signals.

Conventional technology When recording, reproducing or transmitting digital video signals, 1
If errors are detected and corrections are made using the pixels of the pages before and after the screen, one page represents one field or a plurality of fields, and a page-based memory is required. Also, when performing slow playback, high-speed playback, etc., the input order of signals is different from normal playback and there is no regularity, so three pages of memory are used to reconstruct the video signal of each page, and each page is converted into one page. It is necessary to switch between reading and writing on a page-by-page basis, such that one page is only for reading, one page is only for writing the page to be read next, and one page is only for writing the page to be read next.

Problems to be Solved by the Invention However, the above configuration requires an extremely large amount of memory. In view of this point, it is an object of the present invention to provide a signal processing device with a small memory capacity.

Means for Solving the Problems A first aspect of the present invention includes a first memory capable of storing a reproduced signal or a received signal on a screen-by-screen basis, and a second memory capable of storing a signal output from the first memory on a screen-by-screen basis. The present invention is characterized in that it has two memories, and a control means for controlling error correction, special playback processing, signal rearrangement, and time axis adjustment using the first memory and the second memory.

A second aspect of the present invention provides a first memory and a second memory capable of storing input reproduced signals or received signals on a screen-by-screen basis, and obtains the input of the second memory from the output of the first memory and the input of the reproduced signal. a second selection means; a first selection means for obtaining the input of the first memory from the output of the second memory and the reproduction signal input;
It is characterized by having an output selection means for switching between the outputs of the memory and the second memory, and a control means for performing error correction, special reproduction processing, signal rearrangement, and time axis adjustment using the first memory and the second memory. do.

According to the first aspect of the present invention, a signal processing device with a small memory capacity is constructed by operating the first memory and the second memory with a clock twice as high as the clock synchronized with the signal rate.

According to the second aspect of the present invention, the signal processing device has a small memory capacity by operating either the first memory or the second memory with a clock twice as fast as the clock synchronized with the signal rate. Configure.

Embodiment Below, a signal processing apparatus for error-corrected signals reproduced in a device for recording and reproducing digital video signals, which is an embodiment of the first invention, will be described. FIG. 1 is a block diagram of a signal processing device in a first embodiment of the present invention. In FIG. 1, 11 is an input terminal, 12 is a first memory with a capacity of one page, 13 is a second memory with a capacity of one page, 14 is a selector, and 15 is an output terminal.

The operation of the signal processing device of this embodiment configured as described above will be described below. An error detection signal is added to the signal input to the input terminal 11, and by writing only the signal in which no error was detected to the first memory 12, the first memory 12 detects the error in the previous page. A signal replaced with data is obtained. The error detection signal is also written into the first memory 12 at the same time. It is now assumed that signals up to n pages have been written. When the rl-1-1 page signal is input to the input terminal 11, the first memory area 2
will be written in. At the same time, in the second memo 1/3, signals are read out in the order in which they are output, and the signals and the signals at the same position on the screen are read out from the first memory 12 and written into the second memo 3. Furthermore, the signal of page n-1 read from the second memo January 3 is a signal replaced with the signal of page n-2, which is one page before, and the signal of page n, which is one page after the signal of one page before. If it is a signal that should be replaced with a signal from the first memory 12, the selector 14 selects the n-page signal from the first memory 12 and outputs it from the output terminal 15. As described above, according to this embodiment, a signal processing device that can adaptively correct errors from the previous and next pages can be constructed using two pages of memory. Note that this embodiment is just an example, and with a similar configuration, in addition to error correction processing, special reproduction processing, rearrangement, time axis adjustment, etc. are also possible.

FIG. 2 is a block diagram of a signal processing device according to an embodiment of the second invention. In Fig. 2, 21 is an input terminal, 22
a is a first selector, 22b is a second selector, 23a is a first memory with a capacity of one page, and 23b is a second memory with a capacity of one page.
24 is an output selector, and 25 is an output terminal.

The operation of the signal processing device of this embodiment configured as described above will be described below. It is assumed that the signal input to the input terminal 11 is an n-page signal, and the input n-page signal is written into the first memory 23a, and the n-1 page signal is read from the second memory 23b. 1st
If an error is detected among the signals written to the memory 23a, the n-1 signal read from the second memory 23b is
The page signal is selected by the first selector 22a and written into the first memory 23a. In the second memory 23b, the signal of page n-1 is replaced by the signal of page n-2, which is one page before, and it is better to replace the signal of page n after one page than the signal of page one page before. If the signal is good, the n page signal is sent to the second memory 2 through the second selector 22b.
Write to 3b. The output selector 24 selects the output of the second memory 23b, and outputs it from the output terminal 25. After writing the n+l page signal, the first selector 22a, the second selector 22b, the first memory 23a, and the second memory 23b each write the signals for the next page. The operation is reversed so that the output selector 24 also selects the output of the first memory 23a. As described above, according to this embodiment, it is possible to configure a signal processing device that can adaptively correct errors from the previous and next pages using two pages of memory. Note that this embodiment is just an example, and with a similar configuration, in addition to correction processing, special reproduction processing, rearrangement, time axis adjustment, etc. are also possible.

As described in detail, according to the present invention, a signal processing device capable of error correction, special reproduction processing, signal rearrangement, and time axis adjustment can be realized with a configuration with a small memory capacity. It can be done, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal processing device according to a first embodiment of the present invention, and FIG. 2 is a block diagram of a signal processing device according to a second embodiment of the present invention. IL 21... Input terminal, 12.23a...
...First memory with a capacity of 1 page, 13.23b...
...Second memory with a capacity of 1 page, 14...
・Selector, 15.25...Output terminal, 22a・
...First selector, 22b...Second selector, 24...Output selector.

Claims (6)

[Claims] (1) When recording or transmitting digital video signals, the first
a memory, a second memory capable of storing signals output from the first memory on a screen-by-screen basis, error correction, special reproduction processing, signal rearrangement, and time axis using the first memory and the second memory; A signal processing device comprising a control means for controlling adjustment. (2) When one page of a digital video signal is composed of one field or multiple fields, the capacity of the first memory is one page or less, and the capacity of the second memory is one page or less. The signal processing device according to claim (1). (3) When recording or transmitting a digital video signal, a first memory and a second memory capable of storing an input playback signal or a reception signal on a screen-by-screen basis, and an output of the first memory and the playback signal input are provided. a second selection means that switches between the output of the second memory and the input of the reproduction signal and sets the input of the reproduction signal as an input of the first memory; It is characterized by comprising an output selection means for switching the output of the second memory, and a control means for controlling error correction, special playback processing, signal rearrangement, and time axis adjustment using the first memory and the second memory. signal processing device. (4) When one page of a digital video signal is composed of one field or multiple fields, the capacity of the first memory is one page or less, and the capacity of the second memory is one page or less. The signal processing device according to claim (3). (5) Out of the first memory and the second memory, the one whose output is selected by the output selection means reads out the entire screen and writes data to modify the current screen in the memory with a subsequent screen, or stores the data in the other memory. Read the next screen for correction using the previous screen, and if output is not selected by the output selection means between the first memory and the second memory, write the entire screen and correct the screen in the memory using the previous screen. 4. The signal processing device according to claim 3, wherein the signal processing device performs writing to perform data processing. (6) Out of the first memory and the second memory, the one whose output is selected by the output selection means must operate at twice the clock rate that is synchronized with the rate of the reproduction signal, and 5. The signal processing device according to claim 3, wherein the one whose output is not selected by the output selection means operates with a clock synchronized with the rate of the reproduced signal.