JPH0473610B2 - - Google Patents

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Publication number
JPH0473610B2
JPH0473610B2 JP60229382A JP22938285A JPH0473610B2 JP H0473610 B2 JPH0473610 B2 JP H0473610B2 JP 60229382 A JP60229382 A JP 60229382A JP 22938285 A JP22938285 A JP 22938285A JP H0473610 B2 JPH0473610 B2 JP H0473610B2
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layer
plane
gaas
growth
substrate
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JPS6288318A (en
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Priority to JP60229382A priority Critical patent/JPS6288318A/en
Priority to GB8706194A priority patent/GB2202371B/en
Priority to DE19873709134 priority patent/DE3709134A1/en
Publication of JPS6288318A publication Critical patent/JPS6288318A/en
Publication of JPH0473610B2 publication Critical patent/JPH0473610B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02392—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02398—Antimonides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Semiconductor Lasers (AREA)

Abstract

A semiconductor epitaxial layer is formed by misorienting the planar azimuth of single-crystal substrate by 0.1 to 1 degree from plane (111)B and forming the layer by molecular beam epitaxy. The method is described as applied to the fabrication of a GRIN-SCH semiconductor laser of improved quality.

Description

【発明の詳細な説明】 ＜技術分野＞ 本発明は、MBE（分子線エピタキシー）法によ
り単結晶基板上に高品質なエピタキシヤル層を形
成する半導体装置の製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a method for manufacturing a semiconductor device in which a high quality epitaxial layer is formed on a single crystal substrate by the MBE (molecular beam epitaxy) method.

＜従来技術＞ 近年、MBE成長技術の進歩は著しく、10Å以
下の単分子層オーダーまでの極めて薄いエピタキ
シヤル層の制御が可能となつている。このような
MBE成長技術の進歩は半導体装置においても、
従来の液相エピタキシヤル成長（LPE）法など
では製作が困難であつた極めて薄い層を有する素
子構造に基づく新しい効果を利用した半導体装置
の製作を可能とした。その代表的なものとして、
GaAs／AlGas量子井戸（Quantum Well；略し
てQW）レーザがある。このQWレーザは従来の
二重ヘテロ接合（DH）レーザでは、数百Å以上
あつた活性層厚を100Å程度あるいはそれ以下と
することによつて、活性層中に量子化準位が形成
されることを利用しており、従来のDHレーザに
比べて閾値電流が下がる、温度特性が良い、ある
いは過渡特性に優れている等の数々の利点を有し
ている。これに関する参考文献としては次のよう
なものがある。<Prior Art> In recent years, MBE growth technology has made remarkable progress, and it has become possible to control extremely thin epitaxial layers down to the order of a monomolecular layer of 10 Å or less. like this
Advances in MBE growth technology have also led to improvements in semiconductor devices.
This makes it possible to manufacture semiconductor devices that take advantage of new effects based on device structures with extremely thin layers that are difficult to manufacture using conventional liquid phase epitaxial growth (LPE) methods. As a representative example,
There is a GaAs/AlGas quantum well (QW) laser. In this QW laser, a quantization level is formed in the active layer by reducing the thickness of the active layer from several hundred Å or more in conventional double heterojunction (DH) lasers to approximately 100 Å or less. It has many advantages over conventional DH lasers, such as lower threshold current, better temperature characteristics, and superior transient characteristics. References regarding this include the following:

ダブリユー．テイ．ツアング、フイジツクス
レターズ、ボリユーム39、ナンバー10、ペー
ジ786（1981）（W.T.Tsang、Physics Letters、
vol.39、No.10、pp.786（1981））。 Double you. Tei. Tsang, Physics Letters, Volume 39, Number 10, Page 786 (1981) (WTTsang, Physics Letters,
vol.39, No.10, pp.786 (1981)).

エヌ．ケイ．ドウツタア、ジヤーナル オヴ
アプライド フイジツクス、ボリユーム53、
ナンバー11、ページ7211（1982）（N.K.Dutta、
Journal of Applied Physics、vol.53、No.11、
pp.7211（1982））。 N. Kay. Doutsutaa, Journal of Applied Physics, Volume 53,
Number 11, page 7211 (1982) (NKDutta,
Journal of Applied Physics, vol.53, No.11,
pp.7211 (1982)).

エイチ．イワムラ、テイ．サク、テイ．イシ
バシ、ケイ．オオツカ、ワイ．ホリコシ、エレ
クトロニクス レターズ、ボリユーム19、ナン
バー５、ページ180（1983）（H.Iwamura、T.
Saku、T.Ishibashi、K.Otsuka、Y.
Horikoshi、Electronics Letters、vol、19、
No.5、pp.180（1983））。 H. Iwamura, Tei. Saku, Tei. Ishibashi, Kay. Otsuka, wai. Horikoshi, Electronics Letters, Volume 19, Number 5, Page 180 (1983) (H.Iwamura, T.
Saku, T. Ishibashi, K. Otsuka, Y.
Horikoshi, Electronics Letters, vol. 19,
No.5, pp.180 (1983)).

また、MBE法により作製されたもう１つの代
表的な半導体装置として、GaAsとAlGaAs界面
に形成された２次元電子ガスの高移動度特性を利
用した電界効果トランジスタ（FET）がある
（テイ．ミムラ（T.Mimura）他 ジヤパン ジ
ヤーナル アプライド フイジツクス ボリユー
ム19（Japn.J.Appl.Phys.vol.19）（1980）p.L225）。
これらの半導体装置をMBE法で製作する場合、
成長層の結晶が素子特性に大きな影響を及ぼすこ
とが知られている。特に、GaAs／AlGaAs系の
素子では、Alを含むAlGaAsの結晶性が成長条件
に大きく依存するため、AlGaAsの結晶性の向上
が重要である。（ダブリユ・テイ・ツアング（W.
T.Tsang）他 アプライド フイジツクス レ
ター バリユーム36（1980）ページ118（Appl.
Phys.Lett.vol.36（1980）p.118）。 Another typical semiconductor device fabricated by the MBE method is the field-effect transistor (FET), which utilizes the high mobility characteristics of the two-dimensional electron gas formed at the interface between GaAs and AlGaAs (T. Mimura (T. Mimura) et al. Japan Applied Physics Volume 19 (Japn.J.Appl.Phys.vol.19) (1980) p.L225).
When manufacturing these semiconductor devices using the MBE method,
It is known that the crystals in the grown layer have a large effect on device characteristics. In particular, in GaAs/AlGaAs-based devices, improving the crystallinity of AlGaAs is important because the crystallinity of AlGaAs containing Al greatly depends on the growth conditions. (Davriyu Tei Tsang (W.
T.Tsang et al. Applied Physics Letter Varium 36 (1980) Page 118 (Appl.
Phys. Lett. vol. 36 (1980) p. 118).

＜発明の目的＞ 本発明は、以上のような事情に鑑み、MBE法
を用いてエピタキシヤル成長したエピタキシヤル
層の結晶性を従来より向上させることにより、閾
値電流が小さく、温度特性、過渡特性等に優れた
半導体装置が得られる半導体装置の製造方法を提
供することを目的とする。<Purpose of the Invention> In view of the above circumstances, the present invention improves the crystallinity of an epitaxial layer grown epitaxially using the MBE method compared to the conventional method, thereby improving the threshold current, temperature characteristics, and transient characteristics. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can obtain a semiconductor device having excellent properties such as the following.

＜発明の構成＞ 本発明の半導体装置の製造方法は、分子線エピ
タキシー法により、単結晶基板上にエピタキシヤ
ル層を形成して半導体装置を製造する半導体装置
の製造方法において、 前記単結晶基板として、GaAs、GaSb、InAs、
InP、GaP、InSbのいずれかから成り、かつ、面
方位が（111）Ｂ面より0.1〜１度の範囲で傾いて
いる単結晶基板を用い、 該単結晶基板の（111）Ｂ面より0.1〜１度の範
囲で傾いている面上に前記エピタキシヤル層とし
て−Ｖ族化合物半導体を形成することを特徴と
している。<Structure of the Invention> A method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a semiconductor device is manufactured by forming an epitaxial layer on a single crystal substrate by a molecular beam epitaxy method, comprising: as the single crystal substrate; , GaAs, GaSb, InAs,
Using a single-crystal substrate made of InP, GaP, or InSb whose plane orientation is tilted within a range of 0.1 to 1 degree from the (111) B-plane, 0.1 degrees from the (111) B-plane of the single-crystal substrate The present invention is characterized in that a -V group compound semiconductor is formed as the epitaxial layer on a surface tilted within a range of 1 degree.

本発明者らは、MBE法により成長したエピタ
キシヤル層の結晶性を改善する目的で、面方位の
異なるGaAs基板上にAlxGa1-xAs（ｘ＝0.2〜0.8）
を成長して、エピタキシヤル層の結晶性を評価し
た。この結果、従来から用いられている（001）
面上では基板温度720℃以上で表面が完全鏡面の
良質なエピタキシヤル成長層が得られるが、
（011）及び（111）Ｂ面上では非鏡面の成長層し
か得られないことが判明した。更に、（111）Ｂ面
の基板について、第１図に示すように、成長前の
硫酸・過酸化水素水・水の混合液によるエツチン
グの際に基板周辺部にだれを生じせしめ、（111）
Ｂ面より角度が連続して傾いたオフ面を形成し、
同様の成長を行つた。この際、通常の（001）面
基板上にも同時に成長を行い、両者の比較を行つ
た。第２図にも示すように、GaAs基板３１上に
2μｍ厚のAl0.7Ga0.3As層３２を成長し、その上に
80Å厚のGaAs量子井戸層３３を形成し、更に
1000ÅのAl0.7Ga0.3As層３４成長して量子井戸層
３３の発光特性よりAl0.7Ga0.3As層３２の結晶性
を評価した。 In order to improve the crystallinity of the epitaxial layer grown by the MBE method, the present inventors developed AlxGa 1- xAs (x = 0.2 to 0.8) on GaAs substrates with different plane orientations.
was grown and the crystallinity of the epitaxial layer was evaluated. As a result, the conventionally used (001)
On the surface, a high-quality epitaxial growth layer with a perfectly mirror-like surface can be obtained at a substrate temperature of 720°C or higher;
It has been found that only non-specular growth layers can be obtained on the (011) and (111) B planes. Furthermore, as shown in Figure 1, with respect to the (111) B-side substrate, sagging was produced around the substrate during etching with a mixture of sulfuric acid, hydrogen peroxide, and water before growth.
Forms an off surface that is tilted continuously from the B surface,
It has undergone similar growth. At this time, growth was also performed on a normal (001) plane substrate at the same time, and the two were compared. As shown in FIG. 2, on the GaAs substrate 31
A 2 μm thick Al 0.7 Ga 0.3 As layer 32 is grown, and a
A GaAs quantum well layer 33 with a thickness of 80 Å is formed, and
A 1000 Å thick Al 0.7 Ga 0.3 As layer 34 was grown, and the crystallinity of the Al 0.7 Ga 0.3 As layer 32 was evaluated from the emission characteristics of the quantum well layer 33.

GaAs基板３１の面方位の（111）Ｂ面からの
傾き角度が0.1〜１度の範囲では完全に鏡面の成
長表面ホモロジーが得られたが、この範囲をはず
れると大小いずれ側にずれても非鏡面しか得られ
なかつた。514.5nｍのArレーザ光で励起して量
子井戸層３３からの室温におけるフオトルミネツ
センスの効率を測定したところ、第３図に示すよ
うに、傾き角度が0.1〜１度の範囲ではそれ以外
の部分に比べて１桁以上高い発光効率が得られ、
この部分の成長層が高い品質を有することが確認
された。同時に（001）面基板上に成長を行い、
鏡面の成長が得られたが、量子井戸層３３からの
発光強度は、（111）面上の非鏡面の成長層と同一
オーダーであり、（111）Ｂ面からの傾いた面上の
鏡面成長部分の方が格段に優れていることがわか
つた。（111）Ｂ面上の非鏡面成長部の発光効率が
比較的高く、（001）面上と同程度あるものは、非
鏡面の原因が局部的な表面欠陥の形成によるもの
であつて、表面欠陥以外の部分は完全鏡面である
ため、この部分での発光が強いことに起因してい
る。 When the plane orientation of the GaAs substrate 31 is in the range of 0.1 to 1 degree from the (111) B plane, a completely mirror-like growth surface homology was obtained, but outside this range, no matter how large or small the deviation is. All I could get was a mirror surface. When we measured the efficiency of photoluminescence from the quantum well layer 33 at room temperature by exciting it with a 514.5 nm Ar laser beam, we found that when the tilt angle is in the range of 0.1 to 1 degree, The luminous efficiency is more than an order of magnitude higher than that of the other parts.
It was confirmed that the growth layer in this part had high quality. At the same time, growth is performed on a (001) plane substrate,
Although specular growth was obtained, the emission intensity from the quantum well layer 33 was of the same order as that of the non-specular growth layer on the (111) plane. I found the parts to be much better. The luminous efficiency of the non-specular growth area on the (111) B plane is relatively high and is comparable to that on the (001) plane, because the non-specular growth is due to the formation of local surface defects. This is due to the fact that the part other than the defect is a completely mirrored surface, so the light emission is strong in this part.

以上のように、（111）Ｂ面から0.1〜１度傾い
た面上に高品質の成長が可能であることを見出し
たが、それを形成した基板の周辺部にはその方向
に依存せず、高品質のエピタキシヤル成長が可能
であつた。このことから傾むかせる方向にはよら
ないことがわかつた。 As described above, we found that high-quality growth is possible on a plane tilted by 0.1 to 1 degree from the (111) B plane, but the periphery of the substrate on which it was formed does not depend on that direction. , high quality epitaxial growth was possible. This shows that it does not depend on the direction in which it is tilted.

本発明は、上記の発見に基づき、面方位が
（111）Ｂ面から0.1〜１度傾いた基板上にMBE成
長したエピタキシヤル層を用いて、高性能のデバ
イスを得るものである。なお、上記例では、単結
晶基板として、GaAsを用いたが、GaSb、InAs、
InP、GaP、InSbのいずれを用いても、同様な効
果が得られた。 The present invention is based on the above discovery, and uses an epitaxial layer grown by MBE on a substrate whose plane orientation is tilted by 0.1 to 1 degree from the (111)B plane to obtain a high-performance device. In the above example, GaAs was used as the single crystal substrate, but GaSb, InAs,
Similar effects were obtained using InP, GaP, and InSb.

＜実施例＞ 以下、本発明を図示の実施例により詳細に説明
する。<Examples> Hereinafter, the present invention will be explained in detail with reference to illustrated examples.

本発明の一実施例であるGRIN−SCH（Gr−
aded Index Separate Confinement
Heterostruc−ture）型半導体レーザの断面構成
図を第４図に示す。（111）Ｂ面から（110）面に
向かつて0.5度傾むかせたｎ−GaAs基板（Si：
1018cm-3ドープ）１上に、ｎ−GaAsバツフア層
２（0.5μｍ）、ｎ−Al0.7Ga0.3Asクラツド層３（1μ
ｍ）、アンドープAlxGa1-xAs光ガイド層４
（0.2μｍ）、アンドープGaAs量子井戸層５（70
Å）、アンドープAlxGa1 -xAs光ガイド層６
（0.2μｍ）、ｐ−Al0.7Ga0.3Asクラツド層７（1μ
ｍ）、ｐ−GaAsキヤツプ層８（0.5μｍ）、ｎ−
Al0.5Ga0.5As電流閉じ込め層９を基板温度720℃
において連続的にMBE成長した。光ガイド層４
及び６はクラツド層３及び７から量子井戸層５の
端に向かつてAl混晶比が0.7→0.2と２乗分布をと
るよに変化させている。成長後、フツ化水素
（HF）により電流閉じ込め層９を5μｍ幅のスト
ライプ状に選択的に除去し、電流ストライプ２０
を形成し、ｎ側にAuGe−Ni層１１、ｐ側に
AuZn層１０を蒸着・アロイしてオーミツク電極
を形成した。このレーザは250μｍキヤビテイ長
の場合、室温での閾値電流40ｍＡで発振した。比
較のため同時に従来の（100）ｎ−GaAs基板上
に同一の素子構造を製作したところ、閾値電流は
60ｍＡであり、本発明により半導体レーザの閾値
電流が大幅に低減できた。 GRIN-SCH (Gr-
aded Index Separate Confinement
FIG. 4 shows a cross-sectional configuration diagram of a heterostructure type semiconductor laser. An n-GaAs substrate (Si:
10 18 cm -3 doped) 1, n-GaAs buffer layer 2 (0.5 μm), n-Al 0.7 Ga 0.3 As cladding layer 3 (1 μm)
m), undoped AlxGa 1- xAs light guide layer 4
(0.2 μm), undoped GaAs quantum well layer 5 (70
Å), undoped AlxGa 1 - xAs light guide layer 6
(0.2μm), p-Al 0.7 Ga 0.3 As cladding layer 7 (1μm)
m), p-GaAs cap layer 8 (0.5 μm), n-
Al 0.5 Ga 0.5 As current confinement layer 9 at substrate temperature 720℃
Continuously increased MBE. Light guide layer 4
and 6, the Al mixed crystal ratio is changed from 0.7 to 0.2 from the cladding layers 3 and 7 toward the edge of the quantum well layer 5 to take a square distribution. After the growth, the current confinement layer 9 is selectively removed in stripes with a width of 5 μm using hydrogen fluoride (HF) to form current stripes 20.
, an AuGe-Ni layer 11 is formed on the n-side, and an AuGe-Ni layer 11 is formed on the p-side.
An ohmic electrode was formed by depositing and alloying an AuZn layer 10. This laser oscillated with a threshold current of 40 mA at room temperature when the cavity length was 250 μm. For comparison, we fabricated the same device structure on a conventional (100) n-GaAs substrate at the same time, and found that the threshold current was
The threshold current of the semiconductor laser was significantly reduced by the present invention.

以上、本発明の実施例としてAlGaAs系半導体
レーザを例にとつて説明したが、本発明の基礎と
なる現象は−Ｖ族化合物半導体をMBE成長す
る際の本質的な成長機構に基づいているので、
MBE成長により作成した他の−Ｖ族半導体デ
バイス全般に適用可能である。例えば、GaAs基
板上に作製したGaAs／AlGaAs、２次元電子ガ
ス電界効果トランジスタやInP基板上のInAlAs／
InGaAsレーザ等がある。また、単結晶基板とし
て、GaSb、InAs、GaP、InSbを用いても、同様
の効果が得られる。 Although the present invention has been described above using an AlGaAs semiconductor laser as an example, the phenomenon underlying the present invention is based on the essential growth mechanism when growing -V group compound semiconductors by MBE. ,
It is applicable to all other -V group semiconductor devices produced by MBE growth. For example, GaAs/AlGaAs fabricated on a GaAs substrate, two-dimensional electron gas field effect transistor, and InAlAs/AlGaAs fabricated on an InP substrate.
There are InGaAs lasers, etc. Further, similar effects can be obtained even if GaSb, InAs, GaP, or InSb is used as the single crystal substrate.

＜発明の効果＞ 以上より明らかなように、本発明によれば、エ
ピタキシヤル層を高品質化でき、閾値電流が小さ
い等の優れた特性を有する半導体装置が得られ
る。<Effects of the Invention> As is clear from the above, according to the present invention, it is possible to improve the quality of the epitaxial layer and to obtain a semiconductor device having excellent characteristics such as a small threshold current.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はエピタキシヤル層の基板の面方位依存
性を調べるために用いたGaAs基板の断面模式図
である。第２図はエピタキシヤル層の品質を評価
するために成長した構造の断面模式図である。第
３図は量子井戸層からのフオトルミネツセンス発
光効率の（111）Ｂ面からの傾き角度の依存性を
示す説明図である。第４図は本発明の一実施例に
より製作した半導体レーザの断面模式図である。 １……ｎ−GaAs基板、２……ｎ−GaAsバツ
フア層、３……ｎ−Al0.7Ga0.3Asクラツド層、４
……AlxGa1-xAs光ガイド層、５……GaAs量子
井戸層、６……AlxGa1-xAs光ガイド層、７……
ｐ−Al0.7Ga0.3Asクラツド層、８……ｐ−GaAs
キヤツプ層、９……ｎ−Al0.5Ga0.5As電流閉じ込
め層、１０，１１……オーミツク電極、２０……
電流ストライプ、３１……GaAs基板、３２……
Al0.7Ga0.3As層、３３……量子井戸層。 FIG. 1 is a schematic cross-sectional view of a GaAs substrate used to investigate the dependence of the epitaxial layer on the plane orientation of the substrate. FIG. 2 is a schematic cross-sectional view of a structure grown to evaluate the quality of the epitaxial layer. FIG. 3 is an explanatory diagram showing the dependence of the photoluminescence efficiency from the quantum well layer on the tilt angle from the (111)B plane. FIG. 4 is a schematic cross-sectional view of a semiconductor laser manufactured according to an embodiment of the present invention. 1... n-GaAs substrate, 2... n-GaAs buffer layer, 3... n-Al 0.7 Ga 0.3 As cladding layer, 4
...AlxGa 1- xAs light guide layer, 5... GaAs quantum well layer, 6... AlxGa 1- xAs light guide layer, 7...
p-Al 0.7 Ga 0.3 As cladding layer, 8...p-GaAs
Cap layer, 9... n-Al 0.5 Ga 0.5 As current confinement layer, 10, 11... Ohmic electrode, 20...
Current stripe, 31...GaAs substrate, 32...
Al 0.7 Ga 0.3 As layer, 33...quantum well layer.

Claims (1)

【特許請求の範囲】 １ 分子線エピタキシー法により、単結晶基板上
にエピタキシヤル層を形成して半導体装置を製造
する半導体装置の製造方法において、 前記単結晶基板として、GaAs、GaSb、InAs、
InP、GaP、InSbのいずれかから成り、かつ、面
方位が（111）Ｂ面より0.1〜１度の範囲で傾いて
いる単結晶基板を用い、 該単結晶基板の（111）Ｂ面より0.1〜１度の範
囲で傾いている面上に前記エピタキシヤル層とし
て−Ｖ族化合物半導体を形成することを特徴と
する半導体装置の製造方法。[Claims] 1. A method for manufacturing a semiconductor device in which a semiconductor device is manufactured by forming an epitaxial layer on a single crystal substrate by a molecular beam epitaxy method, wherein the single crystal substrate includes GaAs, GaSb, InAs,
Using a single-crystal substrate made of InP, GaP, or InSb whose plane orientation is tilted within a range of 0.1 to 1 degree from the (111) B-plane, 0.1 degrees from the (111) B-plane of the single-crystal substrate A method for manufacturing a semiconductor device, characterized in that a -V group compound semiconductor is formed as the epitaxial layer on a surface that is tilted within a range of -1 degree.
JP60229382A 1985-10-14 1985-10-14 Semiconductor device Granted JPS6288318A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP60229382A JPS6288318A (en) 1985-10-14 1985-10-14 Semiconductor device
GB8706194A GB2202371B (en) 1985-10-14 1987-03-16 Semiconductor device
DE19873709134 DE3709134A1 (en) 1985-10-14 1987-03-20 SEMICONDUCTOR COMPONENT

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60229382A JPS6288318A (en) 1985-10-14 1985-10-14 Semiconductor device
GB8706194A GB2202371B (en) 1985-10-14 1987-03-16 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6288318A JPS6288318A (en) 1987-04-22
JPH0473610B2 true JPH0473610B2 (en) 1992-11-24

Family

ID=39345493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60229382A Granted JPS6288318A (en) 1985-10-14 1985-10-14 Semiconductor device

Country Status (3)

Country Link
JP (1) JPS6288318A (en)
DE (1) DE3709134A1 (en)
GB (1) GB2202371B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2708156B2 (en) * 1987-07-27 1998-02-04 シャープ株式会社 Method for manufacturing semiconductor device
JP2750856B2 (en) * 1987-11-12 1998-05-13 シャープ株式会社 Semiconductor device
JP2674043B2 (en) * 1987-12-11 1997-11-05 ソニー株式会社 Epitaxial growth method
JPH039515A (en) * 1989-06-07 1991-01-17 Sharp Corp Semiconductor device
JP3129112B2 (en) * 1994-09-08 2001-01-29 住友電気工業株式会社 Compound semiconductor epitaxial growth method and InP substrate therefor
CN100453690C (en) * 2006-07-21 2009-01-21 哈尔滨工业大学 Molecular beam epitaxy process of growing GaAs-base InSb film
DE102011087628A1 (en) * 2011-12-02 2013-06-06 Bosch Mahle Turbo Systems Gmbh & Co. Kg loader

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3325314A (en) * 1961-10-27 1967-06-13 Siemens Ag Semi-conductor product and method for making same
US3379584A (en) * 1964-09-04 1968-04-23 Texas Instruments Inc Semiconductor wafer with at least one epitaxial layer and methods of making same
US3476592A (en) * 1966-01-14 1969-11-04 Ibm Method for producing improved epitaxial films
GB8518353D0 (en) * 1985-07-20 1985-08-29 Plessey Co Plc Heterostructure device
EP0214610B1 (en) * 1985-09-03 1990-12-05 Daido Tokushuko Kabushiki Kaisha Epitaxial gallium arsenide semiconductor wafer and method of producing the same

Also Published As

Publication number Publication date
GB2202371B (en) 1991-03-20
DE3709134A1 (en) 1988-09-29
GB2202371A (en) 1988-09-21
JPS6288318A (en) 1987-04-22
GB8706194D0 (en) 1987-04-23

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