JPH0472749A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH0472749A JPH0472749A JP2186283A JP18628390A JPH0472749A JP H0472749 A JPH0472749 A JP H0472749A JP 2186283 A JP2186283 A JP 2186283A JP 18628390 A JP18628390 A JP 18628390A JP H0472749 A JPH0472749 A JP H0472749A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- insulating film
- organic insulating
- alloy
- wiring circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 12
- 229920001721 polyimide Polymers 0.000 claims abstract description 9
- 239000004642 Polyimide Substances 0.000 claims abstract description 6
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 5
- 239000000956 alloy Substances 0.000 claims abstract description 5
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 4
- 229910017709 Ni Co Inorganic materials 0.000 claims abstract description 3
- 229910003267 Ni-Co Inorganic materials 0.000 claims abstract description 3
- 229910003262 Ni‐Co Inorganic materials 0.000 claims abstract description 3
- 239000004696 Poly ether ether ketone Substances 0.000 claims abstract description 3
- 239000004962 Polyamide-imide Substances 0.000 claims abstract description 3
- 239000004697 Polyetherimide Substances 0.000 claims abstract description 3
- 239000004734 Polyphenylene sulfide Substances 0.000 claims abstract description 3
- 239000002253 acid Substances 0.000 claims abstract description 3
- 239000011256 inorganic filler Substances 0.000 claims abstract description 3
- 229910003475 inorganic filler Inorganic materials 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000000203 mixture Substances 0.000 claims abstract description 3
- 229920002492 poly(sulfone) Polymers 0.000 claims abstract description 3
- 229920002312 polyamide-imide Polymers 0.000 claims abstract description 3
- 229920002530 polyetherether ketone Polymers 0.000 claims abstract description 3
- 229920001601 polyetherimide Polymers 0.000 claims abstract description 3
- 229920000069 polyphenylene sulfide Polymers 0.000 claims abstract description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims abstract 2
- 229910052802 copper Inorganic materials 0.000 claims abstract 2
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 239000000470 constituent Substances 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 abstract description 6
- 239000012808 vapor phase Substances 0.000 abstract description 4
- 230000017525 heat dissipation Effects 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 229920006332 epoxy adhesive Polymers 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
二の発明は、樹脂封止型マルチチップパッケージ（以下
は単にマルチチンプパッケージと言う）用のリードフレ
ームに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The second invention relates to a lead frame for a resin-sealed multichip package (hereinafter simply referred to as a multichip package).
従来のマルチチップパッケージ内のグイパッド部の構造
は、大別して５種類ある。その断面構造を第２図乃至第
６図に示す。There are five types of structures for the pad portions in conventional multi-chip packages. Its cross-sectional structure is shown in FIGS. 2 to 6.
第２図は、リードフレーム１のダイパッド２上に接着剤
３′を用いてプリント配線基板４を貼り、その基板４上
に素子５を搭載して基板上の配線回路６と素子５及び配
線回路６とリードフレームのリード部をボンディングワ
イヤ７で接続してある。FIG. 2 shows a printed wiring board 4 pasted on the die pad 2 of the lead frame 1 using an adhesive 3', an element 5 mounted on the board 4, a wiring circuit 6 on the board, an element 5, and a wiring circuit. 6 and the lead portion of the lead frame are connected by bonding wires 7.
第３図は、第２図のプリント配線基板４に代えてダイパ
ッド上に厚膜セラミック基板８を接着したもの、第４図
はダイパッドを用いずに両面実装厚膜セラミック基板８
′を採用したもの（図中９はスルーホール）、第５図は
リードフレームの一部を配線回路６として使用するもの
、第６図はダイパッド２上にセラミック１１１１０を形
成してその上に配線回路６を形成し、素子５を搭載する
ものである。3 shows a thick film ceramic substrate 8 bonded onto a die pad instead of the printed wiring board 4 shown in FIG. 2, and FIG. 4 shows a double-sided mounted thick film ceramic substrate 8 without using a die pad.
5 uses a part of the lead frame as the wiring circuit 6, and FIG. 6 shows a ceramic 11110 formed on the die pad 2 and wiring on top of it. A circuit 6 is formed and an element 5 is mounted thereon.
マルチチップパッケージ用リードフレーム（特にそのグ
イバンド部）は、下記の特性を満たすことが要求される
。A lead frame for a multi-chip package (especially its guide band portion) is required to satisfy the following characteristics.
１）形状・・・・・・最終封止側である樹脂との間に生
しる応力を極力緩和するために肉厚が
薄い。1) Shape: Thin wall thickness to minimize stress generated between the final sealing side and the resin.
２）耐熱性・・・・・・素子搭載、ワイヤーボンディン
グ等のプロセスに耐える耐熱性を持つ。2) Heat resistance: Heat resistance that can withstand processes such as element mounting and wire bonding.
３）熱放散性・・・・・・素子に生じた熱を効率良く逃
がすために良好な熱放散性を持つ。3) Heat dissipation property: Good heat dissipation property to efficiently dissipate heat generated in the element.
４）高密度配線・・・・・・小型化の面で高密度配線が
可能。4) High-density wiring: High-density wiring is possible in terms of miniaturization.
５）広範囲グランド・・・・・・ノイズに対する安定性
確保のために広範囲にグランドがとれ
る。5) Wide-range grounding: Grounding can be provided over a wide range to ensure stability against noise.
６）適性コスト。6) Aptitude cost.
この要求に対し、従来技術では要求の全てを満たし得て
いない。With respect to this requirement, the conventional technology has not been able to satisfy all of the requirements.
即ち、第２図の構造は、ダイパッド部に接着剤を使用し
ているため、耐熱性に劣る。また、接着剤層が絶縁層の
層厚を増加させるので熱放散性も悪い、加えて接着剤の
不純物による悪影響があるなど信頼性に問題がある。That is, the structure shown in FIG. 2 uses an adhesive in the die pad portion, and therefore has poor heat resistance. In addition, since the adhesive layer increases the thickness of the insulating layer, heat dissipation is poor, and impurities in the adhesive have an adverse effect, resulting in reliability problems.
第３図の構造も、第２図と同様の欠点が見られる。また
、この構造は、素子搭載部が非常に厚くなる。The structure of FIG. 3 also has the same drawbacks as that of FIG. 2. Further, in this structure, the element mounting portion becomes very thick.
その他の構造は接着剤層が存在しないが、第４図の構造
は、素子搭載部が非常に厚く、熱放散性も悪い。Although the other structures do not have an adhesive layer, the structure shown in FIG. 4 has a very thick element mounting portion and poor heat dissipation.
また、第５図の構造はリードフレームの一部を配線に利
用しているので配線の幅、間隔を縮小できず、高密度実
装、配線設計に制約がある。Further, since the structure shown in FIG. 5 uses a part of the lead frame for wiring, the width and spacing of the wiring cannot be reduced, which imposes restrictions on high-density packaging and wiring design.
さらに、第６図の構造は、薄膜セラミンク層を気相プロ
セスで形成するのでコスト高となる。Furthermore, the structure shown in FIG. 6 requires high cost because the thin ceramic layer is formed by a vapor phase process.
この発明は、従来のリードフレームに見られる前述の問
題点を無くして高信鯨、低コストのマルチチップパッケ
ージ用リードフレームを実現することをａｔ１５１とし
ている。The purpose of this invention is to eliminate the above-mentioned problems found in conventional lead frames and realize a high-cost, low-cost lead frame for multi-chip packages.
上記の課題を解決するため、この発明においては、第１
図に示すように、グイバンド２上に有機絶縁膜３を接着
剤を用いずに直接形成し、その上に物理的気相成膜法Ｃ
Ｐ Ｖ Ｄ法）による配線回路６を形成する。In order to solve the above problems, in this invention, the first
As shown in the figure, an organic insulating film 3 is directly formed on the Guiband 2 without using an adhesive, and then a physical vapor deposition method C
A wiring circuit 6 is formed by a P VD method.
このリードフレームのフレーム材質は、Ｃｕ合金、Ｆｅ
−Ｎｉ合金、又はＦｅ−Ｎｉ−Ｃｏ合金が好ましい。The frame material of this lead frame is Cu alloy, Fe
-Ni alloy or Fe-Ni-Co alloy is preferred.
また、有機絶縁膜はポリイミド、ポリアミドイミド、ポ
リエーテルイミド、ポリエーテルエーテルケトン、ポリ
フェニレンサルファイド、ポリスルホン、ポリパラバン
酸もしくはこれ等に無機物フィラーを混合したものなど
がよい。The organic insulating film is preferably made of polyimide, polyamideimide, polyetherimide, polyetheretherketone, polyphenylene sulfide, polysulfone, polyparabanic acid, or a mixture thereof with an inorganic filler.
１さらに、配線回路の構成金属はＡｎ、Ｃｕのいずれか
が良い。1 Furthermore, the constituent metal of the wiring circuit is preferably either An or Cu.
ｌ）有機絶縁膜は１〜１００μの厚さであり、接着剤層
も存在しないので、ダイパッド部の全体厚みを薄くし得
る。l) Since the organic insulating film has a thickness of 1 to 100 μm and there is no adhesive layer, the overall thickness of the die pad portion can be reduced.
２） 接着剤層が無いので、フレーム全体の耐熱性が有
機絶縁膜３の耐熱性で決まる。従って、この有機絶縁膜
を耐熱性に優れる前述のポリイミド樹脂等で形成すれば
、エポキシ系接着剤を用いている他のリードフレームに
比して耐熱性が向上する。2) Since there is no adhesive layer, the heat resistance of the entire frame is determined by the heat resistance of the organic insulating film 3. Therefore, if this organic insulating film is formed of the above-mentioned polyimide resin having excellent heat resistance, the heat resistance will be improved compared to other lead frames using epoxy adhesives.
これは表１の熱変形温度を見るとよく判る。This can be clearly seen by looking at the heat distortion temperatures in Table 1.
表１
３）第７図に示すような回転対称のモデルを用いて有機
絶縁膜をポリイミド樹脂のみで形成した場合（ｔ−５（
ｌａｗ）と、ポリイミド樹脂フィルム＋エポキシ系接着
剤で形成した場合（ｔ ＝ １５０ａｍ）の有機絶縁膜
の熱抵抗を表２に示す。Table 1 3) When an organic insulating film is formed only from polyimide resin using a rotationally symmetrical model as shown in Figure 7 (t-5 (
Table 2 shows the thermal resistance of the organic insulating film when it was formed using a polyimide resin film and an epoxy adhesive (t = 150 am).
表２
この表から、有機絶縁膜の厚さによって熱放散性が左右
されることが判るが、本発明では接着剤が無く、有機絶
縁膜を薄くし得るため、熱放散性が向上する。Table 2 From this table, it can be seen that the heat dissipation property is influenced by the thickness of the organic insulating film, but in the present invention, since there is no adhesive and the organic insulating film can be made thin, the heat dissipation property is improved.
４） マスクを用いてＰＶＤ法で配線回路を形成するの
で、低コストでの高密度配線が可能。4) Since wiring circuits are formed using a mask using the PVD method, high-density wiring is possible at low cost.
５） ダイパッド部をグランドとして利用できるので、
グランドを広範囲にとることが可能。5) The die pad can be used as a ground, so
It is possible to cover a wide range of grounds.
６） 有機絶縁膜は気相プロセスによる必要がないので
、コストアンプを招かない。6) The organic insulating film does not require a vapor phase process, so it does not increase costs.
Ｃｕ合金リードフレームのダイパッド上に、ポリイミド
前駆体をスクリーン印刷法で塗布し、Ｎ！雰囲気下で焼
きつけてＬｏｗ厚のポリイミド絶縁膜を形成した。A polyimide precursor is applied onto the die pad of the Cu alloy lead frame using a screen printing method, and N! A low-thickness polyimide insulating film was formed by baking in an atmosphere.
次に、溶融／ｌを寥着源として電子銃による電子線加熱
でイオンブレーティングを行い、薄膜ポリイミド絶縁膜
上にＡＮ配線回路を形成した。そして、このようにして
得られた第１図の構造の本発明のリードフレームと、ダ
イパッド上にポリイミドプリント配線基板を接着剤で貼
った第２図の構造の従来品の耐熱性を比較した。その結
果を表３に示す。Next, an AN wiring circuit was formed on the thin polyimide insulating film by performing ion blating by electron beam heating using an electron gun using the melted /l as a trapping source. The heat resistance of the thus obtained lead frame of the present invention having the structure shown in FIG. 1 was compared with that of a conventional product having the structure shown in FIG. The results are shown in Table 3.
表３
〔効果〕
以上説明したように、この発明のリードフレームは、形
状（厚さ）、耐熱性、熱放散性、高密度配線、広範囲グ
ランド、コストのいずれについても優れており、従って
、これ等の特性をもれ無く満すことが望まれるマルチチ
ップパッケージに利用すると、当該パッケージの品質及
び信頼性の向上に寄与できる。Table 3 [Effects] As explained above, the lead frame of the present invention is excellent in shape (thickness), heat resistance, heat dissipation, high-density wiring, wide grounding, and cost. When used in a multi-chip package that is desired to fully satisfy the following characteristics, it can contribute to improving the quality and reliability of the package.
第１図はこの発明のリードフレームの要部を使用状態に
して示す断面図、第２図乃至第６図は従来のリードフレ
ームの使用状態におけるダイパ・ノド部の断面図、第７
図は熱抵抗の計重に用いたモデルの断面図である。
１・・・・・・リードフレーム、２・・・・・・ダイパ
ッド、３・・・・・・有機絶縁膜、 ５・・・・・・
素子、６・・・・・・配線回路、
７・・・・・・ボンディングワイヤ。
特許出願人 住友電気工業株式会社
同 代理人
鎌
田
文
ほか２名
第１図
第２図
第３図
第４図
第５図
第６図
第７図
軸対称モデルFIG. 1 is a sectional view showing the main parts of the lead frame of the present invention in a used state, FIGS. 2 to 6 are sectional views of the dieper throat section of a conventional lead frame in a used state, and FIG.
The figure is a cross-sectional view of the model used to measure thermal resistance. 1...Lead frame, 2...Die pad, 3...Organic insulating film, 5...
Element, 6... Wiring circuit, 7... Bonding wire. Patent applicant: Sumitomo Electric Industries, Ltd. Agent Aya Kamata and two others Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Axisymmetric model
Claims (4)
に物理的気相成膜法による配線回路を形成してあるリー
ドフレーム。(1) A lead frame in which an organic insulating film is directly formed on a die pad, and a wiring circuit is formed thereon using a physical vapor deposition method.
Ｆｅ−Ｎｉ−Ｃｏ合金である請求項（１）記載のリード
フレーム。(2) The lead frame according to claim (1), wherein the frame material is a Cu alloy, a Fe-Ni alloy, or a Fe-Ni-Co alloy.
リエーテルイミド、ポリエーテルエーテルケトン、ポリ
フェニレンサルファイド、ポリスルホン、ポリパラバン
酸もしくはこれ等に無機物フィラーを混合したものであ
る請求項（１）又は（２）に記載のリードフレーム。(3) According to claim (1) or (2), the organic insulating film is made of polyimide, polyamideimide, polyetherimide, polyetheretherketone, polyphenylene sulfide, polysulfone, polyparabanic acid, or a mixture thereof with an inorganic filler. Lead frame listed.
（１）、（２）又は（３）に記載のリードフレーム。(4) The lead frame according to claim (1), (2) or (3), wherein the constituent metal of the wiring circuit is Al or Cu.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2186283A JPH0472749A (en) | 1990-07-13 | 1990-07-13 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2186283A JPH0472749A (en) | 1990-07-13 | 1990-07-13 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0472749A true JPH0472749A (en) | 1992-03-06 |
Family
ID=16185597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2186283A Pending JPH0472749A (en) | 1990-07-13 | 1990-07-13 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0472749A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5483740A (en) * | 1994-05-26 | 1996-01-16 | Ak Technology, Inc. | Method of making homogeneous thermoplastic semi-conductor chip carrier package |
| KR100229222B1 (en) * | 1996-06-19 | 1999-11-01 | 유무성 | Loc package |
| US6876910B2 (en) | 1998-09-30 | 2005-04-05 | Mitsubishi Denki Kabushiki Kaisha | Electric power steering system |
-
1990
- 1990-07-13 JP JP2186283A patent/JPH0472749A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5483740A (en) * | 1994-05-26 | 1996-01-16 | Ak Technology, Inc. | Method of making homogeneous thermoplastic semi-conductor chip carrier package |
| KR100229222B1 (en) * | 1996-06-19 | 1999-11-01 | 유무성 | Loc package |
| US6876910B2 (en) | 1998-09-30 | 2005-04-05 | Mitsubishi Denki Kabushiki Kaisha | Electric power steering system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH04260358A (en) | Electronic device and manufacture thereof | |
| JPH0878574A (en) | Semiconductor device and manufacturing method thereof | |
| WO2012073572A1 (en) | Semiconductor device, and process for manufacture of semiconductor device | |
| JPH05304247A (en) | Resin sealed semiconductor device | |
| JPH03268351A (en) | Semiconductor device | |
| JPH0831988A (en) | Sealing structure of tape carrier package | |
| JPH0472749A (en) | Lead frame | |
| JPS6050354B2 (en) | Resin-encapsulated semiconductor device | |
| JPH0817870A (en) | Semiconductor device | |
| JP2009231371A (en) | Semiconductor chip and semiconductor apparatus | |
| JP2937713B2 (en) | Semiconductor device | |
| US5541451A (en) | Packaged semiconductor device with external leads having anchor holes provided at polyamide/glass sealed regions | |
| JP2883458B2 (en) | Manufacturing method of wiring board for hybrid integrated circuit | |
| JPS60178655A (en) | Lead frame | |
| JP3335657B2 (en) | Semiconductor package | |
| JPH0945804A (en) | Semiconductor package | |
| JPH0563130A (en) | Lead frame and manufacture thereof, and semiconductor package | |
| JPH06163811A (en) | Semiconductor device and manufacture thereof | |
| JPH0343719Y2 (en) | ||
| JPH0710495Y2 (en) | Semiconductor device | |
| JPH04359548A (en) | Microwave ic package | |
| JP2617052B2 (en) | Manufacturing method of ceramic package | |
| JPS6317263Y2 (en) | ||
| JPH02303052A (en) | Semiconductor package | |
| JPH0429360A (en) | Resin-sealed semiconductor device |