JPH02303052A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH02303052A
JPH02303052A JP12306689A JP12306689A JPH02303052A JP H02303052 A JPH02303052 A JP H02303052A JP 12306689 A JP12306689 A JP 12306689A JP 12306689 A JP12306689 A JP 12306689A JP H02303052 A JPH02303052 A JP H02303052A
Authority
JP
Japan
Prior art keywords
melting point
point glass
metal substrate
lead
cap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12306689A
Other languages
Japanese (ja)
Inventor
Masakazu Umeda
梅田 正和
Masaharu Yamamoto
雅春 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Proterial Ltd
Original Assignee
Sumitomo Special Metals Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Special Metals Co Ltd filed Critical Sumitomo Special Metals Co Ltd
Priority to JP12306689A priority Critical patent/JPH02303052A/en
Publication of JPH02303052A publication Critical patent/JPH02303052A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To increase mechanical strength and heat dissipation, and obtain a small-sized package having electromagnetic shielding effect which is easily manufactured, by sealing a metal cap for a semiconductor chip arranged on a metal substrate via high melting point glass, and necessary leads by using low melting point glass. CONSTITUTION:A metal cap 17 seals a semiconductor chip 11 mounted and arranged on high melting point glass 13 on a metal substrate 12 of low thermal expansion alloy. Said cap 17 is seal-bonded together with the following by using low melting point glass 18; inner leads 15 of Al or Cu thin film connected with bonding wires 16, and outer leads 14 connected with the inner leads 15. By this constitution wherein the seal is performed by using the metal cap and low melting point glass without using a plastic cap, mechanical strength and heat dissipation are increased, and electromagnetic shielding effect is realized. Further a small-sized and low cost semiconductor package is easily manufactured.

Description

【発明の詳細な説明】 産業上の利用分野 この発明は、半導体チップを配置する基板に低熱膨張合
金板を用いた半導体パッケージに係り、内外リード部材
を載置する基板にガラス絶縁層を設け、例えば低熱膨張
合金からなるキャップをガラス封着することにより、機
械的強度にすぐれ取扱いやすく、電磁気的なシールド効
果を有し、がつ熱放散性にすぐれた半導体パッケージに
関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a semiconductor package using a low thermal expansion alloy plate as a substrate on which a semiconductor chip is placed, and in which a glass insulating layer is provided on the substrate on which inner and outer lead members are placed. For example, the present invention relates to a semiconductor package that has excellent mechanical strength, is easy to handle, has an electromagnetic shielding effect, and has excellent heat dissipation properties by sealing a cap made of a low thermal expansion alloy with glass.

背景技術 従来から半導体パッケージとして、半導体チップ(以下
チップという)をプラスチックで封止した第6図に示す
如き、所謂プラスチックパッケージが多用されている。
BACKGROUND ART Conventionally, a so-called plastic package, as shown in FIG. 6, in which a semiconductor chip (hereinafter referred to as a chip) is sealed with plastic, has been widely used as a semiconductor package.

すなわち、プラスチックパッケージ(1)は、チップ(
2)がリードフレーム(3)の中央部に形成されるアイ
ランド(4)に載置され、ろう材や接着材、はんだ等に
て固着されるとともに、ステッチ(5)(内部リード部
)とボンディングワイヤ(6)を介して電気的に接続さ
れ、さらに周囲を樹脂(7)にて封止される構成である
That is, the plastic package (1) contains the chip (
2) is placed on the island (4) formed in the center of the lead frame (3), fixed with brazing material, adhesive, solder, etc., and bonded to the stitch (5) (inner lead part). It has a configuration in which it is electrically connected via a wire (6), and the periphery is further sealed with a resin (7).

プラスチックパッケージは量産性にすぐれ安価であるが
、プラスチック自体が本来吸湿性を持っているため、封
止が完全とは言い難く周囲の影響を受は易くチップの信
頼性を低下させ、高集積化、多機能化が要求される高性
能チップのパッケージには使用できないとされている。
Plastic packages are easy to mass-produce and are inexpensive, but since the plastic itself is inherently hygroscopic, the sealing is not perfect and is easily affected by the surrounding environment, reducing chip reliability and increasing integration. It is said that it cannot be used in high-performance chip packages that require multi-functionality.

半導体パッケージのチップは、大型コンピューター用の
LSIやULSIの如く、高集積度化、演算速度の高速
化の方向に進んでおり、作動中における消費電力の増加
に伴う発熱量が非常に大きくなっている。また、半導体
パッケージの多ビン化、小型化が強く要求されている。
Semiconductor package chips, such as LSI and ULSI for large computers, are moving toward higher integration and faster calculation speed, and the amount of heat generated due to the increase in power consumption during operation has become extremely large. There is. Additionally, there is a strong demand for semiconductor packages to have a larger number of bins and to be smaller.

樹脂封止の前記パッケージ(1)においては、第6図に
示す如く、リードフレームが半導体チップの外部への電
気的接続の経路となるだけでなく、チップ(2)で発生
する熱の放散経路として重要な役割を果している。
In the resin-sealed package (1), as shown in FIG. 6, the lead frame not only serves as a path for electrical connection to the outside of the semiconductor chip, but also as a dissipation path for heat generated in the chip (2). plays an important role as

従って、リードフレーム(3)には、チップから発生す
る熱をパッケージの外部に放散するために熱伝導率の良
い材料が望まれる。
Therefore, the lead frame (3) is desired to be made of a material with good thermal conductivity in order to dissipate the heat generated from the chip to the outside of the package.

一方、チップ(2)とアイランド(4)との接着界面の
剥離や、樹脂(7)にみられるクラック等は、チップ(
2)や封止樹脂(7)とリードフレーム(3)との熱膨
張係数の差を要因として発生しており、これを防止する
ためには、前記チップ(2)及び樹脂(7)とリードフ
レーム(3)との熱膨張係数の整合性が不可欠となる。
On the other hand, peeling of the adhesive interface between the chip (2) and the island (4) and cracks observed in the resin (7) are caused by the chip (
2) and the difference in thermal expansion coefficient between the sealing resin (7) and the lead frame (3).In order to prevent this, it is necessary to Matching the coefficient of thermal expansion with the frame (3) is essential.

このようにプラスチックパッケージは、熱放散性が悪く
、またリードフレーム材が限定され、特に、電気抵抗の
低減を図ることができない。
As described above, plastic packages have poor heat dissipation properties, are limited in lead frame materials, and are particularly unable to reduce electrical resistance.

また、プラスチックパッケージは電磁気的なシールド効
果がないことから外部からのノイズ影響を防ぐことがで
きない問題があった。
Furthermore, since plastic packages do not have an electromagnetic shielding effect, there is a problem in that they cannot prevent the influence of external noise.

発明の目的 この発明は、上記のプラスチックパッケージの問題点を
解決し、機械的強度並びに熱放散性にすぐれ、電磁気的
なシールド効果を有し、近年の多ビン化、小型化の要求
を満し量産性にすぐれた半導体パッケージの提供を目的
としている。
Purpose of the Invention The present invention solves the above-mentioned problems of plastic packaging, has excellent mechanical strength and heat dissipation, has an electromagnetic shielding effect, and satisfies the recent demands for multi-bin size and miniaturization. The aim is to provide semiconductor packages that are easy to mass produce.

発明の概要 この発明は、チップを配置する基板あるいはさらにチッ
プを被包するキャップに低熱膨張合金を用い、基板の絶
縁層として高融点ガラスを被着して、チップとワイヤボ
ンディングを行なう内部リードにA1またはCu薄膜を
用い薄膜形成技術にて配置形成し、外部リードとの接続
を容易にし、これら基板とキャップとを低融点ガラスに
て一体化した構成により前記の目的を達成したものであ
る。
Summary of the Invention This invention uses a low thermal expansion alloy for the substrate on which the chip is placed or the cap that encloses the chip, and coats high-melting point glass as an insulating layer on the substrate, and provides internal leads for wire bonding to the chip. The above object has been achieved by using A1 or Cu thin films and forming them using thin film forming technology to facilitate connection with external leads, and by integrating these substrates and caps with low melting point glass.

すなわち、この発明は、 少なくとも封着部、内外リード部材の配設予定部に高融
点ガラス絶縁層を被覆した低熱膨張合金からなる金属基
板と、基板絶縁層上面に成膜したAlまたはCu薄膜か
らなる内部リードと、内部リードと積層接続されるリー
ドフレームからなる外部リードと、金属基板面に固着し
た半導体チッ・プを被包し低融点ガラスを介して前記金
属基板を封着しかつ少なくとも前記リードフレームを挾
持するキャップとから構成されたことを特徴とする半導
体パッケージである。
That is, the present invention comprises a metal substrate made of a low thermal expansion alloy coated with a high melting point glass insulating layer at least at the sealing part and the part where the inner and outer lead members are to be disposed, and an Al or Cu thin film formed on the upper surface of the substrate insulating layer. an external lead consisting of a lead frame which is laminated and connected to the internal lead; and a semiconductor chip fixed to the surface of the metal substrate, which is encapsulated and sealed to the metal substrate via a low-melting glass; The present invention is a semiconductor package characterized by being comprised of a cap that holds a lead frame.

また、この発明は、 少なくとも封着部、内外リード部材の配設予定部に高融
点ガラス絶縁層を被覆した低熱膨張合金からなる金属基
板と、基板絶縁層上面に成膜したAlまたはCu薄膜か
らなる内部リードと、前記金属基板を貫通し高融点ガラ
スを介して立設するリードビンからなる外部リードと、
金属基板面に固着した半導体チップを被包し低融点ガラ
スを介して前記金属基板を封着するキャップとがら構成
されたことを特徴とする半導体パッケージである。
Further, the present invention includes a metal substrate made of a low thermal expansion alloy coated with a high melting point glass insulating layer at least at the sealing portion and the portion where the inner and outer lead members are to be disposed, and an Al or Cu thin film formed on the upper surface of the substrate insulating layer. an internal lead consisting of an internal lead, and an external lead consisting of a lead bin that penetrates the metal substrate and is erected through high melting point glass;
This semiconductor package is characterized in that it includes a cap that encloses a semiconductor chip fixed to a surface of a metal substrate and seals the metal substrate through a low-melting glass.

好ましい実施態様 この発明に用いる基板材料としては、Fe−Cr合金(
18Cr−Fe等)、Fe−Ni−Cr系合金(42N
i−6Cr−Fe等)、Fe−Ni系合金(42Ni−
Fe等)、Fe−Ni−Co系合金(29Ni−16C
o−Fe等)などの公知の低熱膨張合金が使用できる。
Preferred Embodiment The substrate material used in this invention is Fe-Cr alloy (
18Cr-Fe, etc.), Fe-Ni-Cr alloys (42N
i-6Cr-Fe, etc.), Fe-Ni alloy (42Ni-
Fe, etc.), Fe-Ni-Co alloy (29Ni-16C
Known low thermal expansion alloys such as o-Fe, etc.) can be used.

特に、後述する高融点ガラスやチップ等の熱膨張係数に
対応して最適な合金を選定することが望ましい。
In particular, it is desirable to select an optimal alloy in accordance with the coefficient of thermal expansion of high melting point glass, chips, etc., which will be described later.

また、基板材に、熱放散性を考慮して、熱伝導性の良い
Cu、 Cu合金等を中間層に配置した上記低熱膨張合
金のクラツド材、例えば、インバーlCu/インバー、
コバール/Cu/コバールを用いることもできる。
In addition, in consideration of heat dissipation properties, the substrate material may be a cladding material of the above-mentioned low thermal expansion alloy in which Cu, Cu alloy, etc. with good thermal conductivity is arranged in the intermediate layer, such as Invar lCu/Invar,
Kovar/Cu/Kovar can also be used.

上記低熱膨張合金の上面に被着する高融点ガラスとして
は、pb系ガラス等が採用でき、チップからの発熱等を
考慮すると、チップ、基板材との熱膨張係数差が小さく
、機械的強度が高いことが望ましく、また、リード部材
のAl、 Cuとの濡れ性がよいことが望ましい。
As the high melting point glass to be adhered to the upper surface of the above low thermal expansion alloy, PB glass etc. can be used. Considering heat generation from the chip, the difference in thermal expansion coefficient between the chip and the substrate material is small, and the mechanical strength is low. It is desirable that the bonding temperature is high, and that the wettability with Al and Cu of the lead member is good.

この発明において、高融点ガラスは、キャップとの封着
に用いる低融点ガラスとの相対的比較での高融点であり
、封着時に溶融しない高融点ガラスであればよく、前記
条件や低融点ガラスの特性、さらに製造作業性を考慮し
て接着に必要なガラスの溶融、軟化温度を適宜選定する
とよい。
In this invention, the high melting point glass has a high melting point relative to the low melting point glass used for sealing with the cap, and may be any high melting point glass that does not melt during sealing. It is preferable to appropriately select the melting and softening temperature of the glass necessary for adhesion, taking into consideration the characteristics of the glass and manufacturing workability.

さらに高融点ガラスは、後述する内部リードとなる金属
薄膜配線を形成する際に採用される手段に応じて、例え
ばエツチング等を採用する場合には、これらのエツチン
グ液等によって反応しないよう、耐食性のすぐれたもの
を選定することが望ましい。
Furthermore, depending on the method used to form the metal thin film wiring that will become the internal leads (described later), high-melting point glass may be coated with corrosion-resistant material to prevent it from reacting with the etching solution. It is desirable to select an excellent one.

低熱膨張合金への高融点ガラスの被覆は、該高融点ガラ
ス焼成時に外部リード部材を同時に固着する場合は、リ
ード部材厚みを考慮し所定の粒度(通常200メツシユ
〜300メツシユ)からなるガラス粉末をスクリーン印
刷や電着等により、所要厚みに塗布したのち焼成して一
体化する等の公知の技術が採用できる。
When coating a low thermal expansion alloy with a high melting point glass, if an external lead member is to be attached at the same time when the high melting point glass is fired, a glass powder of a predetermined particle size (usually 200 mesh to 300 mesh) must be used in consideration of the thickness of the lead member. Known techniques such as applying the film to a required thickness by screen printing, electrodeposition, etc., and then baking and integrating the film can be employed.

また、予め金属基板上に内部リードの金属薄膜配線を形
成したのち、該配線端部に外部リード部材を載置し加熱
、拡散して固着する手段を採用する場合は、上記スクリ
ーン印刷、電着等の他、該基板の上面に高融点ガラス板
を配置した後、高融点ガラスの軟化温度以上に加熱、加
圧して一体化する方法も採用できる。
In addition, if a method is adopted in which a metal thin film wiring of an internal lead is formed on a metal substrate in advance, and then an external lead member is placed on the end of the wiring and fixed by heating and diffusing, the above-mentioned screen printing, electrodeposition In addition to the above, it is also possible to adopt a method in which a high melting point glass plate is placed on the upper surface of the substrate and then heated and pressurized to a temperature higher than the softening temperature of the high melting point glass to integrate them.

金属基板の低熱膨張合金板の厚さくA)と高融点ガラス
の厚さくB)との比A/Bは、絶縁耐圧、相互の熱膨張
率、熱伝導率等を考慮して選定するが、通常1010.
5〜1015の範囲が望ましい。
The ratio A/B between the thickness A) of the low thermal expansion alloy plate of the metal substrate and the thickness B) of the high melting point glass is selected taking into consideration dielectric strength voltage, mutual coefficient of thermal expansion, thermal conductivity, etc. Usually 1010.
A range of 5 to 1015 is desirable.

高融点ガラスの絶縁層は、必ずしも金属基板の全面に設
ける必要はなく、金属基板の少なくとも封着部、内外リ
ード部側の配設部に設けるとよく、例えば、チップがら
の熱の枚数性を考慮して、金属基板へ直接チップを固着
することができる。
The insulating layer of high-melting point glass does not necessarily need to be provided on the entire surface of the metal substrate, but it is better to provide it at least on the sealing part and on the inner and outer lead parts of the metal substrate. With this in mind, it is possible to fix the chip directly to the metal substrate.

さらに、低熱膨張合金と高融点ガラスとの密着性を改善
するために、低熱膨張合金と高融点ガラスとの間に酸化
被膜を介在させることが望ましく、特に低熱膨張合金が
Crを含有する場合には、出願人の先の提案(特開昭6
3−47955号)の如く、低熱膨張合金の主面に熱処
理によV) Cr2O3を主体とする酸化被膜を形成し
、その後高融点ガラスを被覆する等の手段を採用するこ
とができる。
Furthermore, in order to improve the adhesion between the low thermal expansion alloy and the high melting point glass, it is desirable to interpose an oxide film between the low thermal expansion alloy and the high melting point glass, especially when the low thermal expansion alloy contains Cr. The applicant's earlier proposal (Japanese Unexamined Patent Publication No. 6
No. 3-47955), it is possible to employ a method such as forming an oxide film mainly composed of V) Cr2O3 on the main surface of a low thermal expansion alloy by heat treatment, and then covering it with high melting point glass.

一方、チップを被包するためのキャップの材料には、前
記の基板材料と同様に公知の低熱膨張合金が使用でき、
この際、キャップ材料は必ずしも基板材料と同一材料と
する必要はなく、また、透明ガラスなど他の側斜を用い
ることもできる。
On the other hand, as the material of the cap for enclosing the chip, a known low thermal expansion alloy can be used, similar to the above-mentioned substrate material.
At this time, the cap material does not necessarily have to be the same material as the substrate material, and other side slopes such as transparent glass can also be used.

キャップを封着するための低融点ガラスは、キャップと
基板との封着接合部のみに配置すれば良く、キャップへ
の被着手段は作業性等を考慮して、スクリーン印刷や電
着後焼成する等公知の手段が採用できる。
The low melting point glass for sealing the cap needs to be placed only at the sealing joint between the cap and the substrate, and the method of adhering it to the cap may be screen printing or electrodeposition followed by firing, taking into consideration workability. Known means such as doing this can be employed.

また、低熱膨張合金との密着性を向上させるため、低融
点ガラスとの間に酸化被膜を介在することも好ましい。
Further, in order to improve the adhesion with the low thermal expansion alloy, it is also preferable to interpose an oxide film between the low melting point glass and the low thermal expansion alloy.

上記低融点ガラスは、キャップ材料である低熱膨張合金
、透明ガラス等との熱膨張率、熱伝導率差等の他、キャ
ップと金属基板との接合が、チップボンディング後に行
なわれるため、これらの接合に悪影響を与えないよう極
力接着温度の低いものを設定することが望まれる。例え
ば、溶融温度が500℃以下のpb系ガラス等が採用で
きる。
The above-mentioned low melting point glass has a difference in thermal expansion coefficient and thermal conductivity with the cap material such as a low thermal expansion alloy or transparent glass, etc., and the bonding between the cap and the metal substrate is performed after chip bonding. It is desirable to set the bonding temperature as low as possible so as not to adversely affect the bonding temperature. For example, PB glass having a melting temperature of 500° C. or lower can be used.

この発明において、内部リードは、絶縁層を形成する高
融点ガラスの上面に、AlまたはCuからなる金属薄膜
配線を公知の薄膜形成技術を用いて容易に精度良く被着
することができ、厚さは5〜10pm程度が望ましい。
In this invention, the internal lead can be formed by easily and precisely depositing a metal thin film wiring made of Al or Cu on the upper surface of the high melting point glass forming the insulating layer using a known thin film forming technique. is preferably about 5 to 10 pm.

すなわち、内部リードの被着には、絶縁層の上面の所定
位置にマスク処理を施した後、AlまたはCuを蒸着し
、再度マスク材を除去する方法や、予め絶縁層の上面全
面にAtまたはCuを貼付したり、蒸着等にて被着した
後、エツチング処理にて不要な部分を除去する方法等が
採用できる。
In other words, for the deposition of internal leads, there is a method in which a predetermined position on the upper surface of the insulating layer is masked, Al or Cu is evaporated, and the mask material is removed again, or a method in which At or Cu is applied to the entire upper surface of the insulating layer in advance. A method may be adopted in which Cu is pasted or deposited by vapor deposition or the like, and then unnecessary portions are removed by etching.

内部リードのAl、 Cuは、例えばW、 Mn−Mo
合金等に比べ低価格であるだけでなく、蒸着やエツチン
グ等の薄膜形成技術が適用し尋ずく、またチップとのワ
イヤーボンディングも容易にできる利点がある。
Al and Cu of the internal leads are, for example, W, Mn-Mo
Not only is it less expensive than alloys, but it also has the advantage of being easily applicable to thin film formation techniques such as vapor deposition and etching, and can be easily wire-bonded to chips.

また、W、 Mn−Mo合金等に比べ電気抵抗が小さく
、使用時の発熱の低減や応答時の向上に寄り、すること
ができる。特に、Alの場合は高融点ガラスとの密着性
が高く、使用中における薄膜配線の剥がれ等による損傷
や誤動作を著しく低減することができる。
In addition, it has a lower electrical resistance than W, Mn-Mo alloys, etc., and can reduce heat generation during use and improve response time. In particular, in the case of Al, it has high adhesion to high melting point glass, and can significantly reduce damage and malfunction due to peeling of thin film wiring during use.

上記の内部リードの端部に接続され外部リードとなるリ
ードフレームやリードビンには、金属基板や金属キャッ
プに用いる材料と同様な公知の低熱膨張合金が採用でき
、従来のリードフレーム材の外面にCuめっきしたもの
など、Cu、 Cu合金と同等の電気抵抗等の特性を有
するものが好ましい。
The lead frames and lead bins that are connected to the ends of the internal leads and serve as external leads can be made of a known low thermal expansion alloy similar to the material used for metal substrates and metal caps, and the outer surface of conventional lead frame materials is made of Cu. It is preferable to use a plated material having characteristics such as electrical resistance equivalent to Cu or Cu alloy.

また、外部リードにCuまたはCu合金あるいはCuめ
っきした材料を用りすると、内部リードがAt薄膜の場
合、加熱拡散接合によって、容易に一体化できる利点を
有する。
Furthermore, if the outer lead is made of Cu, a Cu alloy, or a Cu-plated material, it has the advantage that if the inner lead is an At thin film, it can be easily integrated by heat diffusion bonding.

図面に基づく開示 第1図、第2図はこの発明の半導体パッケージの縦断説
明図である。第3図〜第5図はこの発明の半導体パッケ
ージの要部縦断説明図である。
DISCLOSURE BASED ON THE DRAWINGS FIGS. 1 and 2 are longitudinal sectional views of the semiconductor package of the present invention. FIGS. 3 to 5 are longitudinal sectional views of main parts of the semiconductor package of the present invention.

第1図に示す半導体パッケージ(10)は、上面中央部
にチップ(11)を載置する金属基板(12)が、低熱
膨張合金板の全面に絶縁層として高融点ガラス(13)
を被覆した構成からなる。
The semiconductor package (10) shown in FIG. 1 has a metal substrate (12) on which a chip (11) is mounted at the center of the upper surface, and a high melting point glass (13) as an insulating layer on the entire surface of a low thermal expansion alloy plate.
It consists of a covered structure.

高融点ガラス(13)層上に設けられている外部リード
(14)は所謂リードフレームがらなり、同様に絶縁層
上に所要パターンで薄膜形成されたA1またはCu薄膜
配線からなる内部リード(15)の一端部を積層して接
続しである。さらに内部リード(15)はボンディング
ワイヤ(16)でチップ(11)と接続しである。
The external leads (14) provided on the high melting point glass (13) layer consist of a so-called lead frame, and the internal leads (15) similarly consist of A1 or Cu thin film wiring formed in a desired pattern on an insulating layer. One end of each is laminated and connected. Furthermore, the internal leads (15) are connected to the chip (11) with bonding wires (16).

低熱膨張合金から形成された金属キャップ(17)は、
上記金属基板(12)上に配置されているチップ(11
)、内部リード(15)及びボンディングワイヤ(16
)をともに被包し、低融点ガラス(18)を介して前記
金属基板(12)と封着される。
The metal cap (17) is made of a low thermal expansion alloy.
The chip (11) placed on the metal substrate (12)
), internal leads (15) and bonding wires (16)
) and are sealed to the metal substrate (12) via a low melting point glass (18).

上記構成において、金属キャップ(17)と金属基板(
12)との封着部に外部リード(14)、内部リード(
15)ともに挾持されているため接合強度が大きく、ま
た、両者の接合部におけるクラックの発生を防止するこ
とが可能となり、極めて高い封止効果が得られる。
In the above configuration, the metal cap (17) and the metal substrate (
12), the external lead (14) and the internal lead (
15) Since they are sandwiched together, the bonding strength is high, and it is possible to prevent cracks from occurring at the bonded portion between the two, resulting in an extremely high sealing effect.

また、第2図に示す半導体パッケージ(20)は、上述
の第1図の半導体パッケージ(10)と同様構成からな
り、金属キャップ(27)と金属基板(22)との封着
部に外部リード(24)、内部リード(25)ともに挾
持する構成と効果は同様であり、さらに、チップ(21
)からの熱放散性を図るため、金属基板(22)の上面
中央部に四部を設けて高融点ガラス(23)を被着する
ことなく、チップ(21)を載置したものである。
The semiconductor package (20) shown in FIG. 2 has the same configuration as the semiconductor package (10) shown in FIG. (24) and the internal lead (25) have the same structure and effect, and furthermore, the chip (21)
) In order to improve heat dissipation from the metal substrate (22), four parts are provided at the center of the upper surface of the metal substrate (22), and the chip (21) is placed thereon without covering the high melting point glass (23).

第3図に示す半導体パッケージ(30)は、基本的には
第1図の構成と同様であり、内部リード(35)が金属
キャップ(37)と金属基板(32)との封着部に挾持
されず、外部リード(35)のみが四部に挾持される構
成である。
The semiconductor package (30) shown in FIG. 3 has basically the same structure as that shown in FIG. Instead, only the external lead (35) is held between the four parts.

第4図に示す半導体パッケージ(40)は、特に、内部
リード(45)としてA1を、外部リード(44)にC
uまたはCu合金あるいは表面にCuめっきした素材を
用いた場合に有効な構成であり、金属基板(42)の高
融点ガラス(43)の上面に内部リード(45)を薄膜
形成したのち、該端部に、外部リード(44)を積層載
置し、これを加熱・拡散にて一体化した構成である。
In particular, the semiconductor package (40) shown in FIG. 4 has A1 as the internal lead (45) and C as the external lead (44).
This configuration is effective when using u or Cu alloy or a material with Cu plating on the surface. After forming a thin film of the internal lead (45) on the upper surface of the high melting point glass (43) of the metal substrate (42), In this structure, external leads (44) are stacked and integrated by heating and diffusion.

第5図に示す半導体パッケージ(50)は、第1図〜第
4図の構成が外部リードにリードフレームを用いたのに
対して、リードビンを用いた場合の実施例である。
The semiconductor package (50) shown in FIG. 5 is an embodiment in which a lead bin is used for the external lead, whereas the structure shown in FIGS. 1 to 4 uses a lead frame for the external lead.

詳述すると、チップ(51)を配置する金属基板(52
)は、上述の各半導体パッケージと同様に低膨張合金板
の上面に絶縁層として高融点ガラス(53)を被覆して
あり、リードビンからなる外部リード(54)は、例え
ば、予め金属基板(52)に形成された貫通孔より、金
属基板(52)との絶縁を確保する高融点ガラス管(5
4a)に挿通したリードビンを挿入°し、外部リード(
54)上端部を高融点ガラス(52)層より突出露出さ
せ、同様に絶縁層上に所要パターンで薄膜形成されたA
lまたはCu薄膜配線からなる内部リード(55)を積
層して接続しである。さらに内部リード(55)はボン
ディングワイヤ(56)でチップ(51)と接続しであ
る。
In detail, a metal substrate (52) on which a chip (51) is placed
) has a high melting point glass (53) coated as an insulating layer on the upper surface of a low expansion alloy plate, similar to each semiconductor package described above, and the external lead (54) consisting of a lead bin is, for example, preliminarily connected to the metal substrate (52). ) through the through hole formed in the high melting point glass tube (5) to ensure insulation with the metal substrate (52).
Insert the lead bottle inserted into 4a) and insert the external lead (
54) A thin film was similarly formed on the insulating layer in the desired pattern, with the upper end exposed protruding from the high melting point glass (52) layer.
Internal leads (55) made of L or Cu thin film wiring are stacked and connected. Furthermore, the internal leads (55) are connected to the chip (51) with bonding wires (56).

低熱膨張合金から形成された金属キャップ(57)は、
上記金属基板(52)上に配置されているチップ(51
)、内部リード(55)及びボンディングワイヤ(56
)をともに被包し、低融点ガラス(58)を介して前記
金属基板(52)と封着される。
The metal cap (57) is formed from a low thermal expansion alloy.
Chip (51) placed on the metal substrate (52)
), internal leads (55) and bonding wires (56)
) and are sealed to the metal substrate (52) via a low melting point glass (58).

発明の効果 以上に示す如く、この発明の製造方法により得られる半
導体パッケージは基板、あるいはさらにキャップに低熱
膨張合金材を用いガラス封着するため ■機械的強度に富み、破損の危険性が極めて低くなり、
軽量化、小型化でき取扱い安くなる。
Effects of the Invention As shown above, the semiconductor package obtained by the manufacturing method of the present invention has high mechanical strength and extremely low risk of breakage because the substrate or cap is sealed with glass using a low thermal expansion alloy material. Become,
Lighter weight, smaller size, and cheaper to handle.

■従来のパッケージ等に比べて熱放散性が大幅に向上す
る。
■Significantly improves heat dissipation compared to conventional packages.

■電磁気的なシールドが可能となり、外部ノイズによる
影響が低減する。
■Enables electromagnetic shielding, reducing the effects of external noise.

■従来のリードフレームのみを用いた構成に比べ、ワイ
ヤボンディングを行なう先端部分が高精度に形成でき、
多ビン化、小型化に大きく寄与することができる。
■Compared to the conventional structure using only lead frames, the tip part where wire bonding is performed can be formed with high precision.
It can greatly contribute to increasing the number of bins and downsizing.

■A1、Cuを使用できることから、Auメッキ等を必
要とせず安価であるばかりでなく電気抵抗を低減するこ
とができ、使用時の発熱低減、高速応答等を可能とする
(2) Since A1 and Cu can be used, it is not only inexpensive since it does not require Au plating, etc., but also reduces electrical resistance, making it possible to reduce heat generation during use and achieve high-speed response.

実施例 肛■ 一実施例として第1図に示す半導体パッケージを作成し
た場合を説明する。
Example (1) As an example, a case will be described in which a semiconductor package shown in FIG. 1 is manufactured.

30mmX長さ30mmX0.2mmの42Ni−6C
r−Feからなる低熱膨張合金板(熱膨張係数=95〜
100xlO’/℃)の上面に、露点33℃の温潤H2
ガス中で1150℃に加熱して膜厚1.0μmのCr2
O3を主とする酸化被膜層を形成したのち、絶縁層とな
るpb系高融点ガラス(熱膨張係数:94xlO−7/
’C)をスクリーン印刷にて塗布し、さらに800℃に
て焼成してこれらを一体化し金属基板となした。焼成後
の高融点ガラスの厚さは0.05mmであった。
42Ni-6C of 30mm x length 30mm x 0.2mm
Low thermal expansion alloy plate made of r-Fe (thermal expansion coefficient = 95~
100xlO'/°C) on the upper surface of the
Cr2 with a film thickness of 1.0 μm was heated to 1150°C in gas.
After forming an oxide film layer mainly composed of O3, PB-based high melting point glass (thermal expansion coefficient: 94xlO-7/
'C) was applied by screen printing and further baked at 800° C. to integrate them to form a metal substrate. The thickness of the high melting point glass after firing was 0.05 mm.

上記焼成時に、外部リードとして厚さ0.15mmの4
2Ni−Feからなるリードフレーム(熱膨張係数:5
0xlO−7/’C)を上面を露出させて上記金属基板
に一体化した。
During the above firing, a 0.15 mm thick 4
Lead frame made of 2Ni-Fe (coefficient of thermal expansion: 5
0xlO-7/'C) was integrated into the metal substrate with the top surface exposed.

次いで、内部リードとして所要形状からなるAl薄膜配
線を、マスク材としてステンレス治具を用い蒸着にて形
成し、前記リードフレームの露出面と接続した。この時
のAl薄膜の厚さは10pmであった。
Next, an Al thin film wiring having a desired shape as an internal lead was formed by vapor deposition using a stainless steel jig as a mask material, and connected to the exposed surface of the lead frame. The thickness of the Al thin film at this time was 10 pm.

その後、チップを前記絶縁層の上面に接着剤にて固着し
、該チップとAl薄膜配線をAlボンディングワイヤに
て接続した。
Thereafter, the chip was fixed to the upper surface of the insulating layer with an adhesive, and the chip and the Al thin film wiring were connected using an Al bonding wire.

キャップには、前記金属基板と同材質の低熱膨張合金を
用い、予めCr2O3膜形成熱処理を施した後、所定位
置にpb系低融点ガラス(熱膨張係数:80xlO’/
 ’C)をスクリーン印刷にて被着しておき、前記金属
基板上に載置し450’Cにて焼成することによって金
属基板と一体化し、Al薄膜配線、リードフレームをと
もに封着部で挟持した。
The cap is made of a low thermal expansion alloy made of the same material as the metal substrate, and after being heat-treated to form a Cr2O3 film in advance, PB-based low melting point glass (thermal expansion coefficient: 80xlO'/
'C) is applied by screen printing, placed on the metal substrate and baked at 450'C to integrate with the metal substrate, and the Al thin film wiring and lead frame are both sandwiched by the sealing part. did.

この発明の半導体パッケージと第6図に示す如く、基板
、キャップともにプラスチックからなる従来の半導体パ
ッケージとを比較したところ、この発明の半導体パッケ
ージの熱放散性が35〜50%程度向上することが確認
された。
When comparing the semiconductor package of the present invention with a conventional semiconductor package whose substrate and cap are both made of plastic as shown in Fig. 6, it was confirmed that the heat dissipation performance of the semiconductor package of the present invention was improved by about 35 to 50%. It was done.

また、電磁気的なシールド効果により外部ノイズによる
影響が低減されることも確認した。
We also confirmed that the electromagnetic shielding effect reduces the effects of external noise.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図はこの発明の半導体パッケージの縦断説
明図である。 第3図〜第5図はこの発明の半導体パッケージの要部縦
断説明図である。 第6図は従来のプラスチックパッケージの縦断面説明図
である。 10.20,30,40,50・・−半導体パッケージ
、11.21,31,41,51・・・チップ、12.
22,32,42.52・・・金属基板、13.23,
33,43,53・・・高融点ガラス、14.24,3
4,44,54・・・外部リード、15.25,35,
45,55・・・内部リード、16.26,36,46
.56・・・ボンディングワイヤ、17.27,37,
47.57・・・金属キャップ、18.28,38,4
8,58・・・低融点ガラス。
FIGS. 1 and 2 are longitudinal sectional views of the semiconductor package of the present invention. FIGS. 3 to 5 are longitudinal sectional views of main parts of the semiconductor package of the present invention. FIG. 6 is an explanatory longitudinal cross-sectional view of a conventional plastic package. 10. 20, 30, 40, 50... - semiconductor package, 11. 21, 31, 41, 51... chip, 12.
22,32,42.52...metal substrate, 13.23,
33,43,53...High melting point glass, 14.24,3
4,44,54...external lead, 15.25,35,
45, 55...internal lead, 16.26, 36, 46
.. 56... bonding wire, 17.27, 37,
47.57...metal cap, 18.28,38,4
8,58...Low melting point glass.

Claims (1)

【特許請求の範囲】 1 少なくとも封着部、内外リード部材の配設予定部に高融
点ガラス絶縁層を被覆した低熱膨張合金からなる金属基
板と、基板絶縁層上面に成膜したAlまたはCu薄膜か
らなる内部リードと、内部リードと積層接続されるリー
ドフレームからなる外部リードと、金属基板面に固着し
た半導体チップを被包し低融点ガラスを介して前記金属
基板を封着しかつ少なくとも前記リードフレームを挾持
するキャップとから構成されたことを特徴とする半導体
パッケージ。 2 少なくとも封着部、内外リード部材の配設予定部に高融
点ガラス絶縁層を被覆した低熱膨張合金からなる金属基
板と、基板絶縁層上面に成膜したAlまたはCu薄膜か
らなる内部リードと、前記金属基板を貫通し高融点ガラ
スを介して立設するリードピンからなる外部リードと、
金属基板面に固着した半導体チップを被包し低融点ガラ
スを介して前記金属基板を封着するキャップとから構成
されたことを特徴とする半導体パッケージ。
[Scope of Claims] 1. A metal substrate made of a low thermal expansion alloy coated with a high melting point glass insulating layer at least at the sealing portion and the portion where the inner and outer lead members are to be disposed, and an Al or Cu thin film formed on the upper surface of the substrate insulating layer. an external lead consisting of a lead frame which is laminated and connected to the internal lead, and a semiconductor chip fixed to the surface of the metal substrate, which is encapsulated and sealed to the metal substrate via a low melting point glass, and at least the lead. A semiconductor package comprising: a cap that holds a frame; and a cap that holds a frame. 2. A metal substrate made of a low thermal expansion alloy coated with a high melting point glass insulating layer on at least the sealing portion and the portion where the inner and outer lead members are scheduled to be disposed, and an inner lead made of an Al or Cu thin film formed on the upper surface of the substrate insulating layer; an external lead consisting of a lead pin that penetrates the metal substrate and is erected through high melting point glass;
1. A semiconductor package comprising a cap that encloses a semiconductor chip fixed to a surface of a metal substrate and seals the metal substrate through a low-melting glass.
JP12306689A 1989-05-17 1989-05-17 Semiconductor package Pending JPH02303052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12306689A JPH02303052A (en) 1989-05-17 1989-05-17 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12306689A JPH02303052A (en) 1989-05-17 1989-05-17 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH02303052A true JPH02303052A (en) 1990-12-17

Family

ID=14851351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12306689A Pending JPH02303052A (en) 1989-05-17 1989-05-17 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH02303052A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04111752U (en) * 1991-03-18 1992-09-29 京セラ株式会社 Package cage for storing semiconductor elements
JPH0563130A (en) * 1991-08-30 1993-03-12 Sumitomo Special Metals Co Ltd Lead frame and manufacture thereof, and semiconductor package

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182748A (en) * 1984-02-29 1985-09-18 Fujitsu Ltd Package of semiconductor device and assembly thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182748A (en) * 1984-02-29 1985-09-18 Fujitsu Ltd Package of semiconductor device and assembly thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04111752U (en) * 1991-03-18 1992-09-29 京セラ株式会社 Package cage for storing semiconductor elements
JPH0563130A (en) * 1991-08-30 1993-03-12 Sumitomo Special Metals Co Ltd Lead frame and manufacture thereof, and semiconductor package

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