JPH0471231A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH0471231A JPH0471231A JP18259890A JP18259890A JPH0471231A JP H0471231 A JPH0471231 A JP H0471231A JP 18259890 A JP18259890 A JP 18259890A JP 18259890 A JP18259890 A JP 18259890A JP H0471231 A JPH0471231 A JP H0471231A
- Authority
- JP
- Japan
- Prior art keywords
- deposited
- film
- contact hole
- tin
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005121 nitriding Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 229910052723 transition metal Inorganic materials 0.000 claims description 2
- 150000003624 transition metals Chemical class 0.000 claims description 2
- 229910052725 zinc Inorganic materials 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 11
- 230000004888 barrier function Effects 0.000 abstract description 8
- 238000000137 annealing Methods 0.000 abstract description 7
- 229910052726 zirconium Inorganic materials 0.000 abstract description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 229910000838 Al alloy Inorganic materials 0.000 abstract 1
- 229910008479 TiSi2 Inorganic materials 0.000 abstract 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910001149 41xx steel Inorganic materials 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体素子の製造方法、中でもその配線部の形
成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a wiring portion thereof.
（従来の技術）
従来、半導体素子における電極部および配線部分は第２
図に示す構造のように形成されており、その主要な製造
工程は第３図に示す通りである。(Prior art) Conventionally, the electrode portion and wiring portion of a semiconductor element are
It is formed as shown in the figure, and its main manufacturing process is as shown in FIG.
先ず第３図（ａ）のように、半導体基板１に図示しない
拡散層、素子分離層などを形成した後、絶縁膜２（例え
ばＢＰＳＧ）を形成し、そこにホトリソグラフィ、エツ
チング技術で前記拡散層などの下地に貫通するコンタク
トホール３を開孔する。その後全面にＴｉＮ、ＺｒＮな
どの膜４をスパッタ法により堆積する。これをＮｉｌ
またはＮＨ３のガス中でランプアニール（加熱）するこ
とにより直接窒化すると（ｂ）図のように絶縁膜２の一
部ではＴｉＮ、、ＺｒＮなとのナイトライド５となり、
コンタクトホール３の底部ではメタルとＳｉが反応して
シリサイド６が形成される。即ちナイトライド／シリサ
イドの２層構造が形成され、コンタクト抵抗が低く良好
なコンタクト特性のバリアメタルが形成される。First, as shown in FIG. 3(a), after forming a diffusion layer, an element isolation layer, etc. (not shown) on a semiconductor substrate 1, an insulating film 2 (for example, BPSG) is formed, and the diffusion layers are formed thereon using photolithography and etching techniques. A contact hole 3 penetrating through a base such as a layer is formed. Thereafter, a film 4 of TiN, ZrN, etc. is deposited over the entire surface by sputtering. Nil this
Or, if it is directly nitrided by lamp annealing (heating) in NH3 gas, nitrides 5 such as TiN, ZrN, etc. are formed in a part of the insulating film 2 as shown in the figure (b).
At the bottom of the contact hole 3, metal and Si react to form silicide 6. That is, a two-layer structure of nitride/silicide is formed, and a barrier metal with low contact resistance and good contact characteristics is formed.
その上にＡ１合金膜６をスパッタ法で堆積しホトリソグ
ラフィ、エツチングにより配線パターンを形成して第２
図の構造を得る。On top of that, an A1 alloy film 6 is deposited by sputtering, and a wiring pattern is formed by photolithography and etching.
Get the structure of the diagram.
前述のＴｉＮ％ＺｒＮなどの膜４はＡＩ系合金と下地基
板のＳｉとの反応を防ぎ、またＡ１合金中のＳｉがコン
タクトホール３の底部にエピタキシャル成長するのを防
ぐためのバリアメタルとして働くとともにＡＩ系合金配
線の寿命を長くする効果を期待して形成するものである
。The film 4 such as TiN%ZrN mentioned above acts as a barrier metal to prevent the reaction between the AI alloy and the Si of the base substrate, and also to prevent the Si in the A1 alloy from epitaxially growing at the bottom of the contact hole 3. It is formed with the expectation that it will have the effect of extending the life of the alloy wiring.
（発明が解決しようとする課題）
しかしながら、以上述べた製法では基板上で形成される
ナイトライド／シリサイドの比が制御できず、しかも窒
化よりシリサイド化の方が速いため十分な厚さのナイト
ライドが得られずバリア性が不十分になるという問題が
生じていた。(Problems to be Solved by the Invention) However, with the manufacturing method described above, the ratio of nitride/silicide formed on the substrate cannot be controlled, and since silicidation is faster than nitridation, a sufficient thickness of nitride cannot be obtained. The problem has been that barrier properties are insufficient.
（課題を解決するための手段）
本発明は前述の課題を解決するために、最初に薄いＴｉ
、Ｚｒ膜を堆積して熱窒化を行ない、Ｓｉ基基土上薄い
シリサイドを持つナイトライド／シリサイド構造を形成
した後、再びＴｉ、Ｚｒなどを堆積し熱窒化を行ない、
その２度目に堆積したＴｉ％Ｚｒなとの全てをナイトラ
イドとし、コンタクトホール内においてもナイトライド
な厚く形成するようにしたものである。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention first uses thin Ti.
After depositing a Zr film and performing thermal nitridation to form a nitride/silicide structure with thin silicide on the Si base, Ti, Zr, etc. are deposited again and thermal nitridation is performed,
All of the Ti%Zr deposited the second time is made into nitride, and the nitride is formed thickly even in the contact hole.
（作用）
前述したように本発明の方法によれば、コンタクトホー
ルの底部においても厚いナイトライドな形成することが
できるので、バリア性の高いナイトライドが得られる。(Function) As described above, according to the method of the present invention, a thick nitride can be formed even at the bottom of the contact hole, so a nitride with high barrier properties can be obtained.
（実施例） 第１図に本発明の実施例の工程断面図を示す。(Example) FIG. 1 shows a process sectional view of an embodiment of the present invention.
先ず、（ａ）図に示すように拡散層、分離層、トランジ
スタなどを形成した半導体基板１上にＣＶＤ絶縁膜（例
えばＢＰＳＧ）２を６０００人はど堆積する。その絶縁
膜２に、下地を上層配線に接続するためのコンタクトホ
ール３をホトリソグラフィ、エツチング技術で開孔する
。その後その上全面にＴｉ膜を３００人はどスパッタ法
により堆積する。本実施例ではコ゛ｉ膜を使用したが、
これはＺｒ、Ｈｆ、Ｖ、Ｎｂ、Ｔａ、ＣｒＭｏ、Ｗなど
高融点窒化物を形成する遷移金属であればどれでもよい
。堆積したＴｉ膜をＮ２中でランプアニール（Ｎ、２５
００ＳＣＣＮ、７５０℃、３０ｓｅｃアニール）を行な
うことにより絶縁膜２の上にＴｉＮ膜２４ができるとと
もに、コンタクトホール３底部には薄いＴｉＮ （ナイ
トライド）と薄いＴｉ５ｉｉ２５（シリサイド）が形成
される。First, as shown in Figure (a), a CVD insulating film (for example, BPSG) 2 is deposited by 6,000 people on a semiconductor substrate 1 on which a diffusion layer, an isolation layer, a transistor, etc. are formed. A contact hole 3 is formed in the insulating film 2 by photolithography and etching techniques to connect the underlying layer to the upper wiring. Thereafter, a Ti film is deposited over the entire surface by 300-person sputtering. In this example, a co-i film was used, but
This may be any transition metal that forms a high melting point nitride, such as Zr, Hf, V, Nb, Ta, CrMo, and W. The deposited Ti film was lamp annealed in N2 (N, 25
By performing annealing (00SCCN, 750° C., 30 seconds), a TiN film 24 is formed on the insulating film 2, and thin TiN (nitride) and thin Ti5ii25 (silicide) are formed at the bottom of the contact hole 3.
次に（ｂ）図のように、再びＴｉ膜２６を７００人はど
スパッタ法で堆積し、これをＮ２ガス中でランプアニー
ル（Ｎ、２５００ＳＣＣＮ、８００℃％６０ｓｅｃアニ
ール）してＴｉ膜２６を完全にＴｉＮ化する。この２度
目に堆積したＴｉ膜２６は１回目のアニールで形成され
たＴｉＮ２４上に堆積されているので、Ｔｉ５ｉｉ、Ｓ
ｉなどと接触していない。従ってそれ以上のシリサイド
化は進行せず、全てＴｉＮとなる。Next, as shown in the figure (b), a Ti film 26 is again deposited by sputtering with 700 people, and this is lamp annealed in N2 gas (N, 2500 SCCN, 800°C% 60 sec annealing) to form a Ti film 26. Completely converted to TiN. The Ti film 26 deposited for the second time is deposited on the TiN 24 formed in the first annealing, so Ti5ii, S
There is no contact with i etc. Therefore, silicidation does not proceed any further, and all becomes TiN.
この後（Ｃ）図に示すように、前記まで形成された構造
の上全面にＡ１合金２７を７０００人はどスパッタ法で
堆積し、ホトリソグラフィ、エツチング技術で配線を形
成する。前述でアニールはＮ２ガス中としたが熱論ＮＨ
，ガス中でもよい。Thereafter, as shown in Figure (C), an A1 alloy 27 is deposited over the entire surface of the structure formed so far by the sputtering method, and wiring is formed by photolithography and etching techniques. In the above, annealing was performed in N2 gas, but thermal theory NH
, even in gas.
（発明の効果）
以上説明したように、本発明の製造方法によればＴｉ、
７．ｒなどの直接窒化によるバリアメタル形成に際して
、最初に薄いＴｉ、Ｚｒ膜を堆積して窒化を行ない、そ
の後再びＴｉ、Ｚｒなどの膜を堆積して窒化するように
したので、コンタクトホール底部においても厚いナイト
ライドな形成することができ、直接窒化の利点を生かし
つつバリア性の高いナイトライドな形成することができ
る。(Effects of the Invention) As explained above, according to the manufacturing method of the present invention, Ti,
7. When forming a barrier metal by direct nitriding of R, etc., we first deposited a thin Ti or Zr film and nitrided it, and then deposited a Ti or Zr film again and nitrided it, so even at the bottom of the contact hole. A thick nitride can be formed, and a nitride with high barrier properties can be formed while taking advantage of direct nitriding.
第１図は本発明の実施例の工程断面図、第２図は従来例
の構造図、第３図は従来例の工程断面図である。
１−−”−−一半導体基板、
３−一−−−コンタクトホール、
２４−一−−ＴｉＮ膜（ナイトライド）、２５− −
ＴｉＳｉｘ （シリサイド）、２６−−−− Ｔ
ｉ膜、
２７−−−−Ａ １合金。
＃賢明りＸ１５１列のニオ呈釘１１刀
第
図
〜６
−、−１
従来例６−）横張〕図
〜１
提東例６エ程藺内圀FIG. 1 is a process sectional view of an embodiment of the present invention, FIG. 2 is a structural diagram of a conventional example, and FIG. 3 is a process sectional view of a conventional example. 1--"--1 semiconductor substrate, 3-1--contact hole, 24-1--TiN film (nitride), 25--
TiSix (silicide), 26----T
i film, 27----A 1 alloy. #Jikuri
Claims (1)
クトホールを形成する工程、 （ｂ）その上にＴｉ、Ｚｎなど高融点窒化物を形成する
遷移金属を堆積し、それをＮ＿２、ＮＨ＿３などのガス
中で加熱して窒化する工程、 （ｃ）その上にさらに前記遷移金属を堆積する工程、 （ｄ）それを再びＮ＿２、ＮＨ＿３などのガス中で加熱
することにより窒化する工程、 とを含むことを特徴とする半導体素子の製造方法。[Claims] A method for manufacturing a semiconductor device, which includes: (a) forming an insulating film on a semiconductor substrate and forming a contact hole in a part of the insulating film; (b) depositing a high melting point nitride such as Ti or Zn thereon; (c) further depositing the transition metal thereon; (d) depositing it again in N_2, NH_3; A method for manufacturing a semiconductor device, comprising the steps of: nitriding by heating in a gas such as;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18259890A JPH0471231A (en) | 1990-07-12 | 1990-07-12 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18259890A JPH0471231A (en) | 1990-07-12 | 1990-07-12 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0471231A true JPH0471231A (en) | 1992-03-05 |
Family
ID=16121089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18259890A Pending JPH0471231A (en) | 1990-07-12 | 1990-07-12 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0471231A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393703A (en) * | 1993-11-12 | 1995-02-28 | Motorola, Inc. | Process for forming a conductive layer for semiconductor devices |
| US6051281A (en) * | 1996-10-01 | 2000-04-18 | Tokyo Electron Limited | Method of forming a titanium film and a barrier metal film on a surface of a substrate through lamination |
| US6537621B1 (en) | 1996-10-01 | 2003-03-25 | Tokyo Electron Limited | Method of forming a titanium film and a barrier film on a surface of a substrate through lamination |
-
1990
- 1990-07-12 JP JP18259890A patent/JPH0471231A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393703A (en) * | 1993-11-12 | 1995-02-28 | Motorola, Inc. | Process for forming a conductive layer for semiconductor devices |
| US5623166A (en) * | 1993-11-12 | 1997-04-22 | Motorola, Inc. | Al-Ni-Cr conductive layer for semiconductor devices |
| US6051281A (en) * | 1996-10-01 | 2000-04-18 | Tokyo Electron Limited | Method of forming a titanium film and a barrier metal film on a surface of a substrate through lamination |
| US6537621B1 (en) | 1996-10-01 | 2003-03-25 | Tokyo Electron Limited | Method of forming a titanium film and a barrier film on a surface of a substrate through lamination |
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