JPH0469990U - - Google Patents
Info
- Publication number
- JPH0469990U JPH0469990U JP1990113743U JP11374390U JPH0469990U JP H0469990 U JPH0469990 U JP H0469990U JP 1990113743 U JP1990113743 U JP 1990113743U JP 11374390 U JP11374390 U JP 11374390U JP H0469990 U JPH0469990 U JP H0469990U
- Authority
- JP
- Japan
- Prior art keywords
- data
- value
- input
- calculates
- pieces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000037430 deletion Effects 0.000 claims description 6
- 238000012217 deletion Methods 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Control By Computers (AREA)
- Selective Calling Equipment (AREA)
Description
第１図はこの考案の実施例を示すブロツク図、
第２図はダウンカウンタの回路例を示す図、第３
図は第２図のダウンカウンタの動作を説明するた
めのタイムチヤート、第４図はダウンカウンタの
他の回路例を示す図、第５図は第４図のダウンカ
ウンタの動作を説明するためのタイムチヤート、
第６図はこの考案を適用するシステムの一例を示
すブロツク図、第３図は第６図のシステムのデー
タフレーム信号の伝播態様を示す図、第８図およ
び第９図は初期フレーム信号を示す図である。
２０……データ削除システム、３０……データ
入出力部、４０……削除個数検出回路、５０……
出力データ数設定回路、８０……ダウンカウンタ
。
Figure 1 is a block diagram showing an embodiment of this invention.
Figure 2 is a diagram showing an example of a down counter circuit;
The figure is a time chart for explaining the operation of the down counter in Figure 2, Figure 4 is a diagram showing another example of the down counter, and Figure 5 is a time chart for explaining the operation of the down counter in Figure 4. time chart,
FIG. 6 is a block diagram showing an example of a system to which this invention is applied, FIG. 3 is a diagram showing the propagation mode of the data frame signal in the system of FIG. 6, and FIGS. 8 and 9 show the initial frame signal. It is a diagram. 20... Data deletion system, 30... Data input/output unit, 40... Deletion number detection circuit, 50...
Output data number setting circuit, 80...down counter.
Claims (1)
ータからＢ個（Ｂ＜Ａ）のデータを削除してＣ（
＝Ａ−Ｂ）個のデータを出力するデータ削除シス
テムにおける前記値Ｂを前記出力データ数Ａおよ
び入力データ数Ｃから求める削除個数検出装置に
おいて、 前記出力データ数Ａを各ビツトが全て論理値１
になる数に設定する出力データ数設定手段と、 その初期状態における各ビツトが全て論理値１
に設定され、この初期値を前記入力個数Ｃだけダ
ウンカウントして前記値Ｂを求めるダウンカウン
タと、 を具えることを特徴とする削除個数検出装置。 (2) Ａ個のデータが入力されるとこのＡ個のデ
ータからＢ個（Ｂ＜Ａ）のデータを削除してＣ（
＝Ａ−Ｂ）個のデータを出力するデータ削除シス
テムにおける前記値Ｂを前記出力データ数Ａおよ
び入力データ数Ｃから求める削除個数検出装置に
おいて、 前記出力データ数Ａを各ビツトが全て論理値１
になる数に設定する出力データ数設定手段と、 その初期状態における各ビツトが全て論理値０
に設定され、この初期値を前記入力個数Ｃに１加
えた数だけダウンカウントして前記値Ｂを求める
ダウンカウンタと、 を具えることを特徴とする削除個数検出装置。[Scope of claim for utility model registration] (1) When A pieces of data are input, B pieces of data (B<A) are deleted from this A piece of data and C (
In a data deletion system that outputs =A-B) pieces of data, in a deletion number detection device that calculates the value B from the output data number A and the input data number C,
output data number setting means to set the number to be , and each bit in its initial state is a logical value of 1.
and a down counter that calculates the value B by counting down the initial value by the input number C. (2) When A data is input, B data (B<A) is deleted from A data and C(
In a data deletion system that outputs =A-B) pieces of data, in a deletion number detection device that calculates the value B from the output data number A and the input data number C,
output data number setting means to set the number to be , and each bit in its initial state is all logical value 0.
and a down counter that calculates the value B by counting down the initial value by the input number C plus 1.
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11374390U JPH0753346Y2 (en) | 1990-10-30 | 1990-10-30 | Deleted number detection device |
| PCT/JP1990/001707 WO1991010306A1 (en) | 1989-12-26 | 1990-12-26 | Serial controller |
| EP91901533A EP0507947B1 (en) | 1989-12-26 | 1990-12-26 | Serial controller |
| US07/861,862 US5461617A (en) | 1989-12-26 | 1990-12-26 | Serial controller |
| KR1019920701477A KR960013967B1 (en) | 1989-12-26 | 1990-12-26 | Serial control device |
| DE69030816T DE69030816T2 (en) | 1989-12-26 | 1990-12-26 | SERIAL CONTROL UNIT |
| EP96106642A EP0726665A2 (en) | 1989-12-26 | 1990-12-26 | Serial controller |
| US08/436,931 US5587995A (en) | 1989-12-26 | 1995-05-08 | Serial controller |
| US08/751,796 US5784308A (en) | 1989-12-26 | 1996-11-18 | Binary subtraction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11374390U JPH0753346Y2 (en) | 1990-10-30 | 1990-10-30 | Deleted number detection device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0469990U true JPH0469990U (en) | 1992-06-22 |
| JPH0753346Y2 JPH0753346Y2 (en) | 1995-12-06 |
Family
ID=31861351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11374390U Expired - Lifetime JPH0753346Y2 (en) | 1989-12-26 | 1990-10-30 | Deleted number detection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0753346Y2 (en) |
-
1990
- 1990-10-30 JP JP11374390U patent/JPH0753346Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0753346Y2 (en) | 1995-12-06 |
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