JPH0469928A - Method of forming pattern of tungsten wiring - Google Patents

Abstract

PURPOSE: To prevent short-circuiting at the hole gap inside a tungsten wiring and that between tungsten wires by eliminating an oxide film that is doped densely by wet etching, using tungsten on a polycrystalline silicon film as an etching mask, and performing the dry etching of the polycrystalline silicon film at a part that is not covered with tungsten. CONSTITUTION: An oxide film 19 that is doped densely is deposited at the upper part of a polycrystalline silicon 18. The oxide film 19 is etched and the polycrystalline silicon 18 is exposed, and a tungsten wiring part 15 is formed on it, where a residue 20 of tungsten is formed at the upper part of the oxide film 19. When a reagent solution for etching of the oxide treated by a buffer agent is used, the oxide film 19 and the residue 20 of tungsten on it are eliminated as the same time, and only the tungsten wiring part 15 remains on the polycrystalline silicon 18. By properly setting an etching speed, only one portion of the upper part of the tungsten wiring part 15 is etched, and all the other parts of the polycrystalline silicon 18 are etched except a part that is covered with the tungsten wiring part 15, thus completing the tungsten wiring pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a tungsten wiring pattern using a tungsten film used in metal wiring.

(Prior Art) Conventionally, a large number of elements are formed on a semiconductor substrate through various manufacturing processes, and then metal layers are wired to electrically connect these elements.

This metal layer is created by a photomasking process and a metal etching process performed after depositing a thin metal film on the surface of the semiconductor substrate.

Currently, the metal material commonly used in semiconductor manufacturing processes is aluminum (A1) containing a moderate proportion of silicon (Sj).

However, when a semiconductor device using aluminum as a metal wiring material is used for a long period of time, the metal atoms move through the metal due to the electrons moving in the metal, and the aluminum wiring film becomes thinner, especially in areas with steps. In this case, an electromigration phenomenon that leads to wire breakage may occur, and the semiconductor device may become inoperable. In particular, as semiconductor devices become more highly integrated, the metal wiring film becomes thinner, which increases the ohmic resistance in the contact area, which not only makes the electromigration phenomenon more likely to occur, but also has a negative effect on the operating speed of the semiconductor device. give.

Recently, tungsten, which has a large atomic radius and a large mass, has a relatively low ohmic resistance, so tungsten is selectively deposited by chemical vapor deposition (CVD) only in the contact area with a step where the above phenomenon is likely to occur. It has been used as a metal wiring material to compensate for the defects of aluminum wiring films and improve the operating speed of semiconductor devices.

That is, FIG. 3 shows a cross-sectional view of metal wiring formed by the conventional method of forming a tungsten wiring pattern.

As shown in the figure, after a first insulating film 2 is formed on a semiconductor substrate 1, the first insulating film 2 is doped. Next, an insulating film 3 is deposited on the first insulating film 2 using a conventional chemical vapor deposition method (C
A pattern for vapor deposition of the tungsten wiring portion 5 is formed through a photomasking process and an etching process.

Next, an adhesive layer 4 is deposited on the pattern to facilitate the deposition of the tungsten wiring part 5, and then the tungsten wiring part 5 is selectively deposited on the adhesive layer 4 by a chemical vapor deposition method.
It is deposited on top and grows. Further, an etch-back process is performed to remove the broken line portion shown in the figure.

(Problems to be Solved by the Invention) However, in the method for forming a tungsten wiring pattern described above, when tungsten is wired on a surface with a step, holes 6 are generated and the tungsten wiring portion 5 is During the etch-back process, the surface of the insulating film 3 becomes very rough, and tungsten residue 7 is present on the insulating film 3. There is also the problem that the tungsten residue 7 may cause short circuits between the tungsten wires during various subsequent processes.

Further, when an insulating film is deposited on the insulating film 3 having a very rough surface in order to protect the tungsten wiring portion 5, there is a problem that the surface of the insulating film also becomes rough.

Therefore, the present invention is intended to solve the above-mentioned problems of the prior art, and its purpose is that when forming a tungsten wiring pattern using a tungsten film used in metal wiring, pores are generated inside the tungsten wiring. It is an object of the present invention to provide a method for forming a tungsten wiring pattern without causing short-circuits between tungsten wirings.

Another object of the present invention is to provide a method for forming a tungsten wiring pattern without degrading the surface roughness of an insulating film deposited as a protective film after forming the tungsten wiring pattern.

[Structure of the Invention] (Means for Solving the Problems) The present invention for solving the above problems provides that after forming a polycrystalline silicon film on a first insulating film formed on a semiconductor substrate, the polycrystalline silicon film is a first step of doping the film; a second step of forming a heavily doped oxide film on the polycrystalline silicon film and then exposing the polycrystalline silicon film to form a metal wiring pattern; A third step of selectively depositing tungsten on the exposed surface of the crystalline silicon film
a fourth step of removing the highly doped oxide film by wet etching, using the tungsten on the polycrystalline silicon film as an etching mask;
The method is characterized by comprising a fifth step of dry etching the portions of the polycrystalline silicon film that are not covered with the tungsten.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view showing the state of tungsten wiring formed according to an embodiment of the present invention.

As shown in the figure, the wiring state of the tungsten is such that after polycrystalline silicon (polysilicon) 18 is formed on the first insulating film 12 formed on the semiconductor substrate 11, the polycrystalline silicon 8 is doped; Next, a tungsten wiring portion 5 used as a wiring film is grown on the polycrystalline silicon 18 by selective chemical vapor deposition (CVD).
Further, on the tungsten wiring portion 15 and the first insulating film 12
A second insulating film 13 is deposited thereon.

Such a semiconductor element is electrically connected to other elements via a tungsten wiring section]5. The tungsten wiring portion 15 is electrically connected to doped polycrystalline silicon 18, and the polycrystalline silicon 8 is connected to the semiconductor element of the semiconductor substrate 11 via a contact region (not shown) in the first insulating film 12. electrically connected.

The tungsten wiring state shown in FIG. 1 is formed through the semiconductor device manufacturing process shown in FIGS. 2A to 2E.

In other words, FIGS. 2A to 2E are cross-sectional views of metal interconnections that are formed by repeating various semiconductor element manufacturing processes on the semiconductor substrate 11, and then interconnect these semiconductor elements. are shown for each process.

As shown in FIG. 2A, a first insulating film 12 is deposited on the semiconductor substrate 11 by chemical vapor deposition (CVD), and then polycrystalline silicon 18 is deposited to a thickness of 500 angstroms by the same chemical vapor deposition method. The polycrystalline silicon 18 is then doped with phosphorus (P) in a conventional manner.

Here, although not shown, the contact portion is the first insulating film 1
It is formed within 2. The semiconductor substrate 11 is then connected to the doped polycrystalline silicon 18 via the contact area.
electrically connected to.

FIG. 2B is a cross-sectional view of the metal wiring after the region where tungsten is to be deposited is formed. That is, the highly doped oxide film 19 is highly susceptible to wet etching.
The polycrystalline silicon 18 is deposited by a chemical vapor deposition method. In this case, phosphorus is implanted in the 8-15% oxide range, and optionally arsenic (As) may be used to increase the etch ratio. The heavily doped oxide film 19 is formed into a predetermined pattern using a photomasking process and an etching process.

Here, in the case of doping with phosphorus, the oxide film 19 is formed as a phosphorus silicate glass film (PSG), but it may be formed as an arsenic silicate glass film (ASG) or a spin glass (SOG). A similar effect can be obtained even if it is formed as a film.

During the above etching step, the heavily doped oxide film 19 is etched to expose the polycrystalline silicon 18, and this exposed portion becomes a region where tungsten metal will grow in a later step.

FIG. 2C shows a cross-sectional view of the metal interconnect after tungsten is deposited, and the tungsten interconnect 15 is formed on the polycrystalline silicon 18 by selective chemical vapor deposition. In this case, tungsten hexafluoride (WF6) and silane (S
IH4) and a reaction gas mixed with hydrogen (H2) gas as a catalyst are used, and when the reaction gas reaches 300° C., it reacts and evaporates tungsten onto the polycrystalline silicon 18 to form the tungsten wiring portion 15. Ru. Here, since the area where tungsten should be selectively deposited is wide,
A tungsten residue 20 is formed on top of the oxide film 19.

The second diagram shows a cross-sectional view of the metal wiring after removing the tungsten residue 20 formed on the top of the oxide film 19.

That is, a buffered oxide etching reagent (
When using BOE) solution, the oxide film 19 and the oxide film 19
The upper tungsten residue 20 is removed at the same time, leaving only the tungsten wiring portion 15 on the polycrystalline silicon 18.

In FIG. 2E, the polycrystalline silicon 18 is connected to the tungsten wiring part 1.
5 is used as an etching mask to show a cross-sectional view of metal wiring when dry etching is performed.

This dry etching is called reactive ion etching (RI).
E) The etching speed ratio between the tungsten wiring portion 15 and the polycrystalline silicon 18 was adjusted from ]:1 to 1.5 by adjusting the gas amount, pressure, etching time, etc. can be done.

Therefore, by appropriately setting the above etching speed ratio, only the upper part of the tungsten wiring part 15 is etched, and the polycrystalline silicon 18 is etched leaving only the part covered by the tungsten wiring part 15. All portions are etched to complete the tungsten wiring pattern as shown in FIG. 2E.

Next, a second insulating film 1 is formed to form a protective layer using a conventional method.
3 is deposited, the metal wiring shown in FIG. 1 is completed.

Therefore, since tungsten is selectively deposited and grown using the patterning of the oxide film 19, even if tungsten is deposited on a stepped portion to form a tungsten interconnect, pores will occur inside the tungsten interconnect. You can prevent it from happening.

Further, by removing the oxide film 19 by wet etching, the tungsten residue 20 is also removed at the same time, and no electrical short circuit will occur due to the residue 20.

Furthermore, when tungsten is deposited on the first insulating film 12, there is no need for any adhesive layer and no etch-back process, so the process can be simplified. In addition, since dry etching is performed after forming the tungsten wiring pattern, the upper part of the tungsten wiring part 15 becomes smooth, and the second insulating film 13 to be vapor deposited becomes smooth.
The surface also becomes smooth.

In other words, this embodiment can solve the problems associated with forming metal wiring using tungsten, thereby improving the operating speed of a semiconductor device using tungsten metal wiring. Further, even if the semiconductor element is used for a long period of time, there is no fear of disconnection of the tungsten metal wiring.

The present invention is not limited to the above-described embodiments, but can be implemented in any appropriate manner by making appropriate design changes.

[Effects of the Invention] As explained above, according to the present invention, a first step of doping the polycrystalline silicon film after forming the polycrystalline silicon film on the first insulating film formed on the semiconductor substrate; a second step of forming a highly doped oxide film on the polycrystalline silicon film and then exposing the polycrystalline silicon film to form a metal wiring pattern; and selectively forming a metal wiring pattern on the exposed surface of the polycrystalline silicon film. The third step is to deposit tungsten on the
a fourth step of removing the highly doped oxide film by wet etching, using the tungsten on the polycrystalline silicon film as an etching mask;
The fifth step is dry etching of the polycrystalline silicon film in the portions not covered with tungsten, so when forming a tungsten wiring pattern using a tungsten film used for metal wiring, the inside of the tungsten wiring is etched. No pores are generated, and no short circuit occurs between tungsten wires. Furthermore, after forming the tungsten wiring pattern, the surface roughness of the insulating film deposited as a protective film is not deteriorated.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the wiring state of tungsten formed according to an embodiment of the present invention, and FIGS. 2A to 2E show how various semiconductor elements formed on a semiconductor substrate 11 are interconnected. Cross-sectional view of metal wiring FIG. 3 is a cross-sectional view of metal wiring formed by a conventional method of forming a tungsten wiring pattern. 11... Semiconductor substrate 12... First insulating film 13.
...Second insulating film 15...Tungsten wiring part 18
...Polycrystalline silicon 19...Oxide film 20...Residue FIG, 1 FIG, 3

Claims (5)

[Claims] (1) A first step of doping the polycrystalline silicon film after forming a polycrystalline silicon film on a first insulating film formed on a semiconductor substrate, and doping the polycrystalline silicon film at a high concentration. a second step of exposing the polycrystalline silicon film after forming an oxide film to form a metal wiring pattern; a third step of selectively depositing tungsten on the exposed surface of the polycrystalline silicon film; a fourth step of removing the doped oxide film by wet etching; and using the tungsten on the polycrystalline silicon film as an etching mask, dry etching the portion of the polycrystalline silicon film that is not covered with the tungsten. A method for forming a tungsten wiring pattern, comprising a fifth step. (2) The highly doped oxide film in the second step is a phosphorus silicate glass film (PSG), an arsenic silicate glass film (ASG), or a spin glass (SOG).
2. The method for forming a tungsten wiring pattern according to claim 1, wherein the tungsten wiring pattern is a film. (3) The method for forming a tungsten interconnect pattern according to claim (1), wherein the second step of forming the metal interconnect pattern includes a photomasking step and an etching step. (4) In the third step, tungsten hexafluoride (WF
Claim (1) characterized in that when a mixed gas of _6) and silane (SiH_4) reaches 300°C using hydrogen (H_2) gas as a catalyst, tungsten is vapor-deposited.
) A method for forming a tungsten wiring pattern. (5) A claim characterized in that in the fifth step, the etching rate ratio of tungsten and polycrystalline silicon is adjusted to 1:1 to 1:5 by adjusting the gas amount, pressure, etching time, etc. (2) A method of forming a tungsten wiring pattern as described above.