JPH046900U - - Google Patents
Info
- Publication number
- JPH046900U JPH046900U JP4764690U JP4764690U JPH046900U JP H046900 U JPH046900 U JP H046900U JP 4764690 U JP4764690 U JP 4764690U JP 4764690 U JP4764690 U JP 4764690U JP H046900 U JPH046900 U JP H046900U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- sample
- hold circuit
- output
- inductance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Networks Using Active Elements (AREA)
Description
第１図は本考案に係る周波数補償付サンプルホ
ールド回路の一実施例を示す構成回路図、第２図
は第１図回路の周波数特性を示す特性曲線図、第
３図は従来のアナログ信号出力回路を示すブロツ
ク図、第４図は第３図回路の周波数特性を示す特
性曲線図である。
２……サンプルホールド回路、Ｒ１……第１の
抵抗、Ｌ……インダクタンス、Ｃ……キヤパシタ
ンス、Ｒ２……第２の抵抗。
Fig. 1 is a configuration circuit diagram showing one embodiment of the sample-and-hold circuit with frequency compensation according to the present invention, Fig. 2 is a characteristic curve diagram showing the frequency characteristics of the circuit shown in Fig. 1, and Fig. 3 is a conventional analog signal output. FIG. 4 is a block diagram showing the circuit, and FIG. 4 is a characteristic curve diagram showing the frequency characteristics of the circuit shown in FIG. 2...Sample and hold circuit, R1 ...first resistance, L...inductance, C...capacitance, R2 ...second resistance.
Claims (1)
端が接続する第１の抵抗と、 直列に接続するインダクタンスとキヤパシタン
スを具備し、前記第１の抵抗と並列に接続する回
路と、 前記第１の抵抗の他端にその一端が接続し、コ
モンにその他端が接続する第２の抵抗とを備え、 サンプルホールド回路の周波数特性を補償した
信号を第２の抵抗の一端から出力するように構成
したことを特徴とする周波数補償付サンプルホー
ルド回路。[Claims for Utility Model Registration] A sample-and-hold circuit, a first resistor whose one end is connected to the output terminal of the sample-and-hold circuit, and an inductance and a capacitance connected in series, and which are connected in parallel with the first resistor. and a second resistor, one end of which is connected to the other end of the first resistor, and the other end of which is connected to the common, and a signal that compensates for the frequency characteristics of the sample and hold circuit is transmitted to the second resistor. A sample hold circuit with frequency compensation, characterized in that it is configured to output from one end of a resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4764690U JP2508378Y2 (en) | 1990-05-09 | 1990-05-09 | Sample-hold circuit with frequency compensation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4764690U JP2508378Y2 (en) | 1990-05-09 | 1990-05-09 | Sample-hold circuit with frequency compensation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH046900U true JPH046900U (en) | 1992-01-22 |
| JP2508378Y2 JP2508378Y2 (en) | 1996-08-21 |
Family
ID=31563760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4764690U Expired - Fee Related JP2508378Y2 (en) | 1990-05-09 | 1990-05-09 | Sample-hold circuit with frequency compensation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2508378Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4954383U (en) * | 1972-08-15 | 1974-05-14 | ||
| JPS50108285U (en) * | 1974-02-09 | 1975-09-04 |
-
1990
- 1990-05-09 JP JP4764690U patent/JP2508378Y2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4954383U (en) * | 1972-08-15 | 1974-05-14 | ||
| JPS50108285U (en) * | 1974-02-09 | 1975-09-04 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2508378Y2 (en) | 1996-08-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |