JPS62100712U - - Google Patents
Info
- Publication number
- JPS62100712U JPS62100712U JP19382985U JP19382985U JPS62100712U JP S62100712 U JPS62100712 U JP S62100712U JP 19382985 U JP19382985 U JP 19382985U JP 19382985 U JP19382985 U JP 19382985U JP S62100712 U JPS62100712 U JP S62100712U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- variable impedance
- terminal
- signal generation
- coil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
Landscapes
- Filters And Equalizers (AREA)
- Amplifiers (AREA)
Description
第１図は本考案の歪信号発生回路の一実施例を
示す回路図、第２図はその等価回路図、第３図は
従来の歪信号発生回路の回路図、第４図は微調整
用の可変コンデンサの断面図である。
２…三端子トランス、３…入力端、４…出力端
、５…ダイオード、６…可変抵抗器、７…可変コ
ンデンサ。
Figure 1 is a circuit diagram showing one embodiment of the distortion signal generation circuit of the present invention, Figure 2 is its equivalent circuit diagram, Figure 3 is a circuit diagram of a conventional distortion signal generation circuit, and Figure 4 is for fine adjustment. FIG. 2 is a sectional view of a variable capacitor of FIG. 2... Three-terminal transformer, 3... Input end, 4... Output end, 5... Diode, 6... Variable resistor, 7... Variable capacitor.
Claims (1)
続してあるコイルと、前記コイルの中間の端子と
接地との間に接続してある可変インピーダンス回
路と、前記入力端子及び前記出力端子の間に接続
してある非線形素子とからなり、前記入力端子に
加えられる信号に対する前記可変インピーダンス
回路及び前記非線形素子のインピーダンスをそれ
ぞれＺ１及びＺ２とするとき前記可変インピーダ
ンス回路のインピーダンスＺ１はＺ２／４に調整
されることを特徴とする歪信号発生回路。 A coil having one end connected to an input terminal and the other end connected to an output terminal, a variable impedance circuit connected between the intermediate terminal of the coil and ground, and the input terminal and the output terminal. and a connected nonlinear element, and when the impedances of the variable impedance circuit and the nonlinear element with respect to the signal applied to the input terminal are Z 1 and Z 2 respectively, the impedance Z 1 of the variable impedance circuit is Z 2 / 4. A distortion signal generation circuit characterized in that the distortion signal generation circuit is adjusted to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19382985U JPS62100712U (en) | 1985-12-17 | 1985-12-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19382985U JPS62100712U (en) | 1985-12-17 | 1985-12-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62100712U true JPS62100712U (en) | 1987-06-26 |
Family
ID=31150219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19382985U Pending JPS62100712U (en) | 1985-12-17 | 1985-12-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62100712U (en) |
-
1985
- 1985-12-17 JP JP19382985U patent/JPS62100712U/ja active Pending