JPS6424600U - - Google Patents
Info
- Publication number
- JPS6424600U JPS6424600U JP11961687U JP11961687U JPS6424600U JP S6424600 U JPS6424600 U JP S6424600U JP 11961687 U JP11961687 U JP 11961687U JP 11961687 U JP11961687 U JP 11961687U JP S6424600 U JPS6424600 U JP S6424600U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- input
- switch element
- operational amplifier
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Amplifiers (AREA)
Description
第１図はこの考案の一実施例を説明するための
接続図、第２図は従来の技術を説明するための接
続図、第３図は従来の技術の不都合を説明するた
めのグラフである。
１……入力端子、２……演算増幅器、３……第
１入力抵抗器、４……第１バツフア増幅器、５…
…第１スイツチ素子、６……ホールド用コンデン
サ、７……第１帰還抵抗器、８……出力端子、１
１……第２入力抵抗器、１２……第２バツフア増
幅器、１３……第２スイツチ素子、１４……第２
帰還抵抗器。
Fig. 1 is a connection diagram for explaining one embodiment of this invention, Fig. 2 is a connection diagram for explaining the conventional technique, and Fig. 3 is a graph for explaining the disadvantages of the conventional technique. . DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Operational amplifier, 3... First input resistor, 4... First buffer amplifier, 5...
...First switch element, 6... Hold capacitor, 7... First feedback resistor, 8... Output terminal, 1
1... Second input resistor, 12... Second buffer amplifier, 13... Second switch element, 14... Second
feedback resistor.
Claims (1)
に接続したホールド用コンデンサと、反転入力端
子に一端が接続され、他端が第１入力抵抗器を通
じて入力端子に接続した第１スイツチ素子と、こ
の第１スイツチ素子と第１入力抵抗器との接続点
と演算増幅器の出力端子の間に接続した第１帰還
抵抗器とを具備したサンプルホールド回路におい
て、 Ｂ 上記演算増幅器の非反転入力端子と入力端子
の間に接続され、上記第１入力抵抗器と等しい抵
抗値を持つ第２入力抵抗器と、位相反転機能及び
利得を持つ第２バツフア増幅器と、第１スイツチ
素子と同期してオン、オフ駆動される第２スイツ
チ素子から成る直列回路と、 Ｃ 第２バツフア増幅器と上記第２入力抵抗器と
の接続点に一端が接続され、他端が上記演算増幅
器の出力端子に接続され、上記第１帰還抵抗器と
等しい抵抗値を持つ第２帰還抵抗器と、 を付加して成るサンプルホールド回路。[Claims for Utility Model Registration] A. A hold capacitor connected between the inverting input terminal and the output terminal of the operational amplifier, one end of which is connected to the inverting input terminal, and the other end connected to the input terminal through the first input resistor. In a sample-and-hold circuit comprising a first switch element connected and a first feedback resistor connected between a connection point between the first switch element and the first input resistor and an output terminal of the operational amplifier, B. a second input resistor connected between the non-inverting input terminal and the input terminal of the operational amplifier and having a resistance value equal to that of the first input resistor; a second buffer amplifier having a phase inverting function and gain; A series circuit consisting of a second switch element that is driven on and off in synchronization with the switch element; one end connected to the connection point between the second buffer amplifier and the second input resistor, and the other end connected to the operational amplifier. a second feedback resistor connected to the output terminal of the circuit and having a resistance value equal to that of the first feedback resistor;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11961687U JPS6424600U (en) | 1987-08-03 | 1987-08-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11961687U JPS6424600U (en) | 1987-08-03 | 1987-08-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6424600U true JPS6424600U (en) | 1989-02-09 |
Family
ID=31365001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11961687U Pending JPS6424600U (en) | 1987-08-03 | 1987-08-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6424600U (en) |
-
1987
- 1987-08-03 JP JP11961687U patent/JPS6424600U/ja active Pending
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