JPH04677A - Method and system for wiring assigned wiring length - Google Patents

Method and system for wiring assigned wiring length

Info

Publication number
JPH04677A
JPH04677A JP2100335A JP10033590A JPH04677A JP H04677 A JPH04677 A JP H04677A JP 2100335 A JP2100335 A JP 2100335A JP 10033590 A JP10033590 A JP 10033590A JP H04677 A JPH04677 A JP H04677A
Authority
JP
Japan
Prior art keywords
wiring
point position
route
length
relay point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2100335A
Other languages
Japanese (ja)
Inventor
Yasuyuki Fujiwara
康之 藤原
Yutaka Sekiyama
裕 関山
Jiro Kusuhara
楠原 治郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2100335A priority Critical patent/JPH04677A/en
Publication of JPH04677A publication Critical patent/JPH04677A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0005Apparatus or processes for manufacturing printed circuits for designing circuits by computer

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To attain route determination with arbitrary assigned wiring length by giving a means to determine a searching line for setting a relay point to a position so that the sum of the distance between a starting point and the relay point and the distance between the relay point and an end point may be the assigned wiring length neither too much nor too little. CONSTITUTION:The assigned wiring length of a section (S,E) is found while using the total 4 layers of the (x) direction, (y) direction, oblique +45 deg. direction and oblique -45 deg. direction wiring layers simultaneously regradless of the size relation of assigned wiring length L and Manhattan distance. After setting a relay point T so as to satisfy delta (S,T)+delta (T,E)=L to the wiring object section (S,E) in advance, the shortest wiring route searching is executed with a labyrinth method, a segment searching method, etc., by using the (x) and (y) direction and oblique + or -45 deg. direction wiring layers simultaneously to the plural sections (S,T) and (T,E) divided by the relay point T and a wiring route is determined. The delta (S,T) and the delta (T,E) mean the minimum distance able to be realized by using the above-mentioned 4 wiring layers to the sections (S,T) and (T,E) repectively. Thus, the route can be determined by the arbitrary assigned wiring length.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、プリント基板、集積回路等の配線パターンを
計算機を用いて自動決定する方法及びシステムに係り、
特に、信号遅延と回路動作特性を考慮し、所望の信号に
対する配線パターンを指定された配線長にて自動決定す
るのに好適な配線長指定配線方法及び配線長指定配線シ
ステムに関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method and system for automatically determining wiring patterns of printed circuit boards, integrated circuits, etc. using a computer.
In particular, the present invention relates to a wire length designation wiring method and a wire length designation wiring system suitable for automatically determining a wiring pattern for a desired signal with a designated wire length in consideration of signal delay and circuit operating characteristics.

〔従来の技術〕[Conventional technology]

プリント基板、集積回路等において、信号遅延と回路動
作特性を考慮し、所望の配線区間に対し指定された配線
長りで配線経路を決定する方法として、例えば、特開昭
59−29247号等に記載された技術がある。
For printed circuit boards, integrated circuits, etc., a method of determining a wiring route with a specified wiring length for a desired wiring section by considering signal delay and circuit operating characteristics is disclosed in, for example, Japanese Patent Laid-Open No. 59-29247. There is a technique described.

所望の配線区間が(S、E)として与えられたとき、指
定された配線長しで配線経路の決定を要求される場合、
実際に得られる配線経路長ρ(S。
When a desired wiring section is given as (S, E) and a wiring route is required to be determined with a specified wiring length,
The actual wiring path length ρ(S).

E)に対しては、一般に、次の条件が課せられる。For E), the following conditions are generally imposed:

L−ΔL≦Q(S、E)≦L+ΔL    ・・・(1
)但し、(1)式において、ΔLは許容誤差である。
L-ΔL≦Q(S,E)≦L+ΔL...(1
) However, in equation (1), ΔL is an allowable error.

この(1)式の条件を満たす従来の配線経路決定方法は
、与えられた配線区間を配線する場合に、水平方向(X
方向)配線層と垂直方向(y方向)配線層をペアとする
2層を用いて、配線経路探索することにより配線経路の
決定を行なう方法である。
The conventional wiring route determination method that satisfies the condition of equation (1) is to route a given wiring section in the horizontal direction (X
In this method, a wiring route is determined by searching for a wiring route using two layers in which a wiring layer in the direction (direction) and a wiring layer in the vertical direction (y direction) are paired.

以下従来技術による配線方法を図面により説明する。The wiring method according to the prior art will be explained below with reference to the drawings.

第9図から第11図は、従来技術による配線経路の決定
方法を説明する図である。
FIGS. 9 to 11 are diagrams for explaining a method of determining a wiring route according to the prior art.

従来の配線経路決定方法では、第9図に示すように、配
線対象区間(S、E)に対しあらかじめ中継点Tを、 d(s、T)+d(T、E)=L       ・・・
(2)を満足するように設定した後、第10図に示すよ
うに、中継点Tによって分割された複数の区間(S、T
)、(T、E)に対しそれぞれ迷路法、線分探索法等を
用いて配線経路の決定を行なっていた。但し、(2)式
において、d(S、T)、d(T。
In the conventional wiring route determination method, as shown in Fig. 9, relay points T are determined in advance for the wiring target section (S, E) as follows: d(s, T) + d(T, E) = L...
After setting to satisfy (2), as shown in Fig. 10, a plurality of sections (S, T
), (T, E), the wiring routes were determined using the maze method, line segment search method, etc., respectively. However, in equation (2), d(S,T), d(T.

E)はそれぞれ区間(S、T)、(T、E)に対するX
方向、Y方向を用いた最短距離すなわちマンハッタン距
離を意味する。
E) are X for the intervals (S, T) and (T, E), respectively.
direction, meaning the shortest distance using the Y direction, ie, the Manhattan distance.

第11図は、(2)式を満足する中継点Tの設定方法の
1例を示している。中継点Tの設定にあたっては、まず
、点Sを通過するX方向軸、X方向軸に平行な直線nx
1+Q’/x、点Eを通過するX方向軸、X方向軸に平
行な直線Ωx2.Qyzを求めた上で、 QXL、Qx
z、 Qyty Qyzからそれぞれ距離dQにある中
継点設定用探索線Tx1゜Txz、Tyl、Tyzを、
領域RX1.RxztRyt、Ryzの内部として決定
する。ここで、距離dQは、2点(S、E)間のX方向
距離Lx、y方向距離Lyを用いて、 d Q=(L−(Lx+Ly))/2     −(3
)として求めることができる。また領域Rx 1゜Rx
 zg R’/ 11 R’j 2については、例えば
領域RX1は、直線Ωx1に関し点Eと反対側の領域と
2直1iAQy1pQyxにはさまれた帯状の領域の共
通領域として容易に求めることができる。中継点Tは、
これらの探索線TXI、TX21 TyttTyz上で
あり、かつ配線可能な未使用の格子点の中から選択する
ことで設定できる。
FIG. 11 shows an example of a method for setting the relay point T that satisfies equation (2). In setting the relay point T, first, the X-direction axis passing through the point S, and the straight line nx parallel to the X-direction axis
1+Q'/x, X direction axis passing through point E, straight line Ωx2 parallel to the X direction axis. After finding Qyz, QXL, Qx
z, Qyty The relay point setting search lines Tx1°Txz, Tyl, Tyz, which are each at a distance dQ from Qyz,
Area RX1. RxztRyt is determined as internal to Ryz. Here, the distance dQ is calculated using the distance Lx in the X direction and the distance Ly in the y direction between the two points (S, E), dQ=(L-(Lx+Ly))/2-(3
) can be obtained as Also, the area Rx 1°Rx
Regarding zg R'/11 R'j 2, for example, the region RX1 can be easily determined as the common region of the region on the opposite side of the point E with respect to the straight line Ωx1 and the band-shaped region sandwiched between the two straight lines 1iAQy1pQyx. The relay point T is
It can be set by selecting from unused lattice points that are on these search lines TXI, TX21 TyttTyz and can be wired.

このように、(2)式を満足する中継点Tを設定し、中
継点によって分割された区間(S、T)。
In this way, a relay point T that satisfies equation (2) is set, and the section (S, T) is divided by the relay point.

(T、E)を最短に配線経路探索することにより、指定
配線長しに対し、過不足のない配線経路長を実現するこ
とができる。
By searching for the shortest wiring route (T, E), it is possible to realize a wiring route length that is just the right length for the specified wiring length.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、前記従来技術は配線経路探索を水平方向配線層
と垂直方向配線層のみ用いて行なっていたため、指定可
能な配線長りは配線対象区間(S。
However, in the prior art, the wiring route search is performed using only the horizontal wiring layer and the vertical wiring layer, so the length of the wiring that can be specified is limited to the wiring target section (S).

E)のマンハッタン距離より大きくなければならず、配
線対象区間のマンハッタン距離より短く配線長りを指定
する必要性のある信号遅延条件の厳しい配線区間に対し
ては、配線経路の決定が不可能であるという問題を有し
ていた。
It is impossible to determine a wiring route for a wiring section with severe signal delay conditions, where it is necessary to specify a wiring length that must be larger than the Manhattan distance in E) and shorter than the Manhattan distance of the wiring target section. I had a problem with that.

本発明の目的は、前述した従来技術の問題点を解決し、
プリント基板、集積回路等に対する配線経路の決定を、
信号遅延と回路動作特性を考慮し、任意の指定配線長で
経路決定することを可能とした配線長指定配線方法及び
配線長指定配線システムを提供することにある。
The purpose of the present invention is to solve the problems of the prior art described above,
Determine wiring routes for printed circuit boards, integrated circuits, etc.
It is an object of the present invention to provide a wire length designated wiring method and a wire length designated wiring system that make it possible to determine a route with an arbitrary designated wire length in consideration of signal delay and circuit operation characteristics.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、前記目的は、以下の手段により達成さ
れる。
According to the present invention, the above object is achieved by the following means.

(a)  水平方向、垂直方向配線層に加えて、斜め方
向配線層を有する少なくとも3層以上の配線層を同時に
配線対象層として、迷路法、線分探索法等による最短配
線経路の発見が可能な配線パターン決定システムを用い
る。
(a) In addition to horizontal and vertical wiring layers, at least three wiring layers having diagonal wiring layers are simultaneously used as wiring target layers, and the shortest wiring route can be found using the maze method, line segment search method, etc. A wiring pattern determination system is used.

(b)  配線対象区間(S、E)に対する中継点Tの
設定を、2点(S、T)間及び2点(T、E)間の距離
を、上記斜め方向配線層を含む少なくとも3層以上の配
線層を配線対象層として実現可能な最小距離として算出
する方法により、実行する。
(b) Set the relay point T for the wiring target section (S, E), and set the distance between the two points (S, T) and the distance between the two points (T, E) to at least three layers including the diagonal wiring layer. This is carried out by a method of calculating the minimum distance that can be achieved by using the above wiring layer as a wiring target layer.

以下第3図から第8図を用いて上記説明を補足する。第
3図から第8図は、斜め方向配線層を含む少なくとも3
層以上の配線層を同時に配線対象層として決定する配線
パターン決定システムにおいて、上記本発明により配線
経路の決定処理を行なった1例として、配線対象区間(
S、E)に対する配線経路決定処理を、水平方向(X方
向)配線層、垂直方向(X方向)配線層、斜め+45゜
方向配線層、斜め一45°方向配線層の計4層を同時に
用いながら、指定配線長りとマンハッタン距離の大小関
係に係らず、該区間(S、E)の配線経路長Q(S、E
)を前記(1)式で示す制約条件を満足するように実行
するようすを示している。
The above explanation will be supplemented below using FIGS. 3 to 8. 3 to 8 show at least three diagonal wiring layers.
In a wiring pattern determination system that simultaneously determines more than one wiring layer as a wiring target layer, as an example of a wiring route determination process according to the present invention, a wiring target section (
The wiring route determination process for S and E) is performed simultaneously using a total of four layers: a horizontal (X direction) wiring layer, a vertical (X direction) wiring layer, a diagonal +45° wiring layer, and a diagonal -45° wiring layer. However, regardless of the magnitude relationship between the specified wiring length and the Manhattan distance, the wiring route length Q (S, E) of the section (S, E)
) is executed so as to satisfy the constraint shown in equation (1) above.

本例では第3図に示すように、配線対象区間(S、E)
に対しあらかじめ中継点Tをδ(S、T)+δ(T、E
)=L       ・・・(4)を満足するように設
定した後、第4図に示すように、中継点Tによって分割
された複数の区間(S。
In this example, as shown in Figure 3, the wiring target section (S, E)
, the relay point T is set in advance by δ(S, T) + δ(T, E
)=L...After setting so as to satisfy (4), as shown in FIG. 4, a plurality of sections (S.

T)、(T、E)に対し、x、X方向及び斜め±45°
方向配線層を同時に用いて、迷路法、線分探索法等によ
り最短なる配線経路探索を行ない、配線経路を決定する
。但し、(4)式において、δ(S、T)、δ(T、E
)はそれぞれ区間(S、T)。
T), (T, E) x, X direction and oblique ±45°
Using the directional wiring layer at the same time, the shortest wiring route is searched by the maze method, line segment search method, etc., and the wiring route is determined. However, in equation (4), δ(S, T), δ(T, E
) are the intervals (S, T), respectively.

(T、E)に対する上記4つの配線層を用いて実現可能
な最小距離を意味する。
It means the minimum distance that can be realized using the above four wiring layers for (T, E).

次にこのような中継点の設定方法を説明する。Next, a method of setting such a relay point will be explained.

第5図に示すように、本例では2点(S、E)間のX方
向距離Lx、y方向距離Lyの関係に対し、4通り、ま
たその各々に対し指定配線長しの大きさに応じて3通り
の計12通りの中継点設定を行なっている。このうち第
6図、第7図、第8図はL x > L y     
          ・・・(5)L x<(Jr +
 1)* L y        ・・・(6)の関係
を満たす場合の設定方法を示している。ここで(6)式
の関係は、X方向配線層、X方向配線層のみを用いて実
現可能な(S、E)を結ぶ最小距離(マンハッタン距離
のことであり、Lx十Lyで与えられる)が、斜め+4
5″′方向配線層、斜め一45°方向配線層のみを用い
て実現可能な(S、E)を結ぶ最小距離(この場合、l
 −L xで与えられる)より大きいことを示す。この
うち、第6図、第7図、第8図はそれぞれ指定配線長し
が L <J「* L x       ・・・(7)1*
LX≦L<Lx+Ly      −(8)L≧Lx+
Ly      ・・・(9)の関係を満足する場合の
設定方法を示している。
As shown in Fig. 5, in this example, there are four different relationships between the distance Lx in the X direction and the distance Ly in the y direction between two points (S, E), and the specified wiring length for each of them. Accordingly, a total of 12 relay point settings are made, 3 ways. Of these, in Figures 6, 7, and 8, L x > L y
...(5) L x < (Jr +
1)*L y This shows a setting method when the relationship (6) is satisfied. Here, the relationship in equation (6) is the minimum distance (Manhattan distance, which is given by Lx + Ly) that connects (S, E) that can be realized using only the X-direction wiring layer and the X-direction wiring layer. But diagonal +4
The minimum distance (in this case, l
−L (given by x). Of these, the designated wiring lengths in Figures 6, 7, and 8 are L < J "* L x ... (7) 1 *
LX≦L<Lx+Ly −(8)L≧Lx+
Ly... shows a setting method when the relationship (9) is satisfied.

以下これを説明する。This will be explained below.

第6図は指定配線長しが(7)式を満足する場合の設定
方法を示している。中継点の設定にあたっては、まず点
Sを通過するX方向軸、X方向軸。
FIG. 6 shows a setting method when the designated wiring length satisfies equation (7). When setting the relay point, first set the X-direction axis that passes through point S, and the X-direction axis.

+45°方向軸、−45°方向軸に平行な4直線Q X
l、 Q yx、 mX1* myl、点Eを通過する
X方向軸、X方向軸、+45°方向軸、−45°方向軸
に平行な4直線QX 2+ Q y2t rn X 2
9m3’□を求めた上で、m3/1.my2から距離d
mにある中継点設定用探索線Tmx、 Tmz+ Q 
xt、 Q x2から距離dQにある中継点設定用探索
線TQ1゜TQ2をそれぞれ図に示す領域Rmt、 R
rr+z。
4 straight lines Q X parallel to +45° axis and -45° axis
l, Q yx, mX1* myl, 4 straight lines QX 2+ Q y2t rn
After finding 9m3'□, m3/1. distance d from my2
Search line for relay point setting at m, Tmx, Tmz+Q
xt, Q Regions Rmt, R in which the search lines for relay point setting TQ1°TQ2 located at a distance dQ from x2 are shown in the figure, respectively.
rr+z.

RQl、RQ2の内部として決定する。ここで距離dm
、clQは計算式 %式%)] により求めることができる。中継点Tはこれらの中継点
設定用探索線上にありかつ配線可能な未使用の格子点の
中から選択することで設定できる。
It is determined that it is inside RQl and RQ2. Here the distance dm
, clQ can be calculated using the following formula. The relay point T can be set by selecting from among the unused grid points that are on these search lines for relay point setting and can be wired.

第7図は指定配線長りが(8)式を満足する場合の設定
方法を示している。この場合、基本的な処理は第6図に
示す方法と同じであり特に、点S。
FIG. 7 shows a setting method when the designated wiring length satisfies equation (8). In this case, the basic processing is the same as the method shown in FIG.

点Eを通過する一45°方向軸に平行な直線rn/l。A straight line rn/l passing through point E and parallel to the 145° axis.

myzからぞれぞれ距離dmにある中継点設定用探索線
T m 1 、 T m zの決定方法は第6図に示す
方法と全く同じであり、距4Id mの計算は(10)
式により行なうことができる。しかし、点S9点Eを通
過するX方向軸に平行な直線Ωxx、Qx2から距離d
Qにある中継点設定用探索線TΩ1.TQzは、第6図
の場合とは相対的に異なる領域RQ1゜RQ 2の内部
として決定する。さらに、この場合、距離dQの算出は dQ=cL  ((AJ/T I)*Lx+Ly)]/
2・・・(12) により行なう。
The method for determining the search lines T m 1 and T m z for relay point setting, which are located at a distance dm from myz, is exactly the same as the method shown in Fig. 6, and the calculation of the distance 4Id m is as follows (10)
This can be done by formula. However, the distance d from the straight line Ωxx, Qx2, which passes through point S9 and point E, is parallel to the X direction axis.
Search line TΩ1 for relay point setting at Q. TQz is determined as being inside the region RQ1°RQ2, which is relatively different from the case of FIG. Furthermore, in this case, the distance dQ is calculated as dQ=cL ((AJ/T I)*Lx+Ly)]/
2... Perform according to (12).

第8図は指定配線長しが(9)式を満足する場合の設定
方法を示している。この場合も上記の2つの場合と同様
であるが、第7図に示す場合と異なるのは、点S9点E
を通過する一45°方向軸に平行な直線m Y 1 +
 m ’l 2がら、それぞれ距1idmにある中継点
設定用探索線Tm工、Tmzの決定方法である。この場
合、探索線Tmx、Tmzの決定は、第7図の場合とは
相対的に異なる領域Rmx。
FIG. 8 shows a setting method when the specified wiring length satisfies equation (9). This case is also the same as the above two cases, but the difference from the case shown in FIG. 7 is that point S9 and point E
A straight line m Y 1 + parallel to the -45° axis passing through
This is a method for determining search lines Tm and Tmz for setting relay points, which are located at a distance of 1idm from m'l2. In this case, the search lines Tmx and Tmz are determined in a region Rmx that is relatively different from the case of FIG.

Rm xの内部として行なう。さらに、この場合、距離
dmの算出は dm=[L−(Lx  (J薯2−1)本Ly)]/2
・・・(■3) により行なう。
This is done as the inside of Rm x. Furthermore, in this case, the calculation of the distance dm is dm=[L-(Lx (J薯2-1)Ly)]/2
...Perform according to (■3).

以上(5)、 (6)式の関係を満たす場合の中継点の
設定方法について述べたが、これ以外の場合についても
同様に中継点を設定することができる。
Although the method for setting relay points in the case where the relationships of equations (5) and (6) are satisfied has been described above, relay points can be similarly set in cases other than this.

〔作用〕[Effect]

上記手段を用いた配線長指定配線方法では、水平方向、
垂直方向配線層に加えて、斜め方向配線層を有する少な
くとも3層以上の配線層を同時に配線対象層とした上で
、配線対象区間に対する中継点の設定に関し、該区間の
始点と中継点間及び中継点と該区間の終点間の距離を、
上記斜め方向配線層を含む少なくとも3層以上の配線層
を配線対象層として実現可能な最小距離として定義して
いる。そしてその定義に従って、上記手段を用いた配線
長指定配線方法では、配線対象区間のマンハッタン距離
と指定配線長の大小に係らず、中継点設定用探索線を、
上記始点と中継点間の距離と上記中継点と終点間の距離
の和が過不足なく指定配線長になるような位置に決定す
る手段を与えるので、結果として任意の指定配線長によ
る経路決定が可能となる。
In the wiring length specified wiring method using the above method, horizontal direction,
In addition to the vertical wiring layer, at least three wiring layers including diagonal wiring layers are simultaneously set as the wiring target layer, and regarding the setting of relay points for the wiring target section, between the starting point and the relay point of the section, and The distance between the relay point and the end point of the section is
At least three or more wiring layers including the diagonal wiring layer are defined as the minimum distance that can be realized as a wiring target layer. According to the definition, in the wiring length specified wiring method using the above means, the search line for relay point setting is
It provides a means for determining a position such that the sum of the distance between the starting point and the relay point and the distance between the relay point and the end point is the specified wiring length, so as a result, route determination using any specified wiring length is possible. It becomes possible.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図及び第2図により、前
述した第3図から第8図に示す本発明の詳細な説明する
図により補足しながら、説明する。
Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 and 2, supplemented by detailed explanations of the present invention shown in FIGS. 3 to 8 described above.

第1図は本発明の一実施例の方法を説明するフローチャ
ート、第2図は本発明の一実施例の方法を実行する処理
システムの構成を示すブロック図である。
FIG. 1 is a flowchart illustrating a method according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a processing system that executes the method according to an embodiment of the present invention.

本発明の一実施例による配線方法では、第2図に示すよ
うな処理システムにより、第1図に示すフローチャート
に従って実行される。本発明の方法を実行する処理シス
テムは、第2図に示すように、第1図に示すフローチャ
ートに従った自動配線処理及びシステム全体の制御を行
なうコンピュータ201と、プリント基板、集積回路等
の配線層の構成、各配線層における配線方向等を定義し
た実装系情報ファイル202と、配線対象区間及び該区
間に対する配線条件等を格納したネット情報ファイル2
03と、配線パターン情報を格納したパターン情報格納
ファイル204と、コンピュータ201において実行さ
れる自動配線処理に対し入出力するファイル名等のパラ
メータを与えるために使用するコンソールデイスプレィ
装置205と、自動配線実行後の未配線情報、統計情報
等の各種情報を出力するリスト出力装置206とにより
構成されている。
A wiring method according to an embodiment of the present invention is executed by a processing system as shown in FIG. 2 according to a flowchart shown in FIG. As shown in FIG. 2, a processing system for carrying out the method of the present invention includes a computer 201 that performs automatic wiring processing according to the flowchart shown in FIG. 1 and controls the entire system, and wiring for printed circuit boards, integrated circuits, etc. A mounting system information file 202 that defines layer configurations, wiring directions in each wiring layer, etc., and a net information file 2 that stores wiring target sections, wiring conditions for the sections, etc.
03, a pattern information storage file 204 that stores wiring pattern information, a console display device 205 used to provide parameters such as file names to be input and output to the automatic wiring process executed in the computer 201, and an automatic wiring system. The list output device 206 outputs various information such as unwired information and statistical information after execution.

このように構成された処理システムによる配線方法の具
体例を第1図のフローチャートにより。
A specific example of the wiring method using the processing system configured as described above is shown in the flowchart of FIG.

前述した第3図から第8図に示す本発明の詳細な説明す
る図により補足しながら、以下に説明する。
The present invention will be explained below, supplemented by detailed illustrations of the present invention shown in FIGS. 3 to 8 mentioned above.

まず、配線対象区間(S、E)、指定配線長りおよびそ
の許容誤差ΔLをネット情報格納ファイル203から入
力し、配線層の構成、各配線層における配線方向等を実
装系情報ファイル202から入力し、配線層の配線パタ
ーンをパターン情報格納ファイル204から入力し配線
処理に必要な環境を設定する(101)。次に、X方向
配線層。
First, the wiring target section (S, E), specified wiring length, and its tolerance ΔL are input from the net information storage file 203, and the configuration of wiring layers, wiring direction in each wiring layer, etc. are input from the mounting system information file 202. Then, the wiring pattern of the wiring layer is input from the pattern information storage file 204, and the environment necessary for wiring processing is set (101). Next is the X direction wiring layer.

y方向配線層、斜め+45°方向配線層、斜め一45°
方向配線層の計4層を同時に用いて実現可能な2点S、
Eを結ぶ最小距離δ(S、E)を算出する(102)。
y direction wiring layer, diagonal +45° direction wiring layer, diagonal -45°
2 points S that can be realized by simultaneously using a total of 4 layers of directional wiring layers,
The minimum distance δ(S, E) connecting E is calculated (102).

ここで該最小距離δ(S、E)と指定配線長りの比較を
行ない(103)、もし、L−ΔL〈δ(S、E)<L
+ΔL   ・・・(14)を満足するならば、配線対
象区間(S、E)に対する最短なる配線経路探索を実行
した後(104)、配線経路探索により決定した配線パ
ターンをパターン情報格納ファイル204に出力して(
109)、処理を終了する。
Here, the minimum distance δ(S, E) is compared with the designated wiring length (103), and if L−ΔL<δ(S,E)<L
+ΔL...If (14) is satisfied, after executing the shortest wiring route search for the wiring target section (S, E) (104), the wiring pattern determined by the wiring route search is stored in the pattern information storage file 204. Output (
109), the process ends.

もしく14)式を満たさない場合には、上記最小距離δ
(S、E)と指定配線長りの比較を再度行ない(105
)、もし δ(S、E)≦L−ΔL        ・・・(15
)を満足するならば、配線対象区間(S、E)に対する
中継点Tを、2点S、T問および2点T、E間を結ぶ最
小距離δ(S、T)、δ(T、E)に対して、 δ(S、T)+δ(T、E)=L       ・・・
(16)を満足するように設定する(106.第3図参
照)。
Or, if formula 14) is not satisfied, the above minimum distance δ
(S, E) and the specified wiring length are compared again (105
), if δ(S, E)≦L−ΔL...(15
), then the relay point T for the wiring target section (S, E) is defined as the minimum distance δ(S, T), δ(T, E) connecting the two points S, T and the two points T, E. ), δ(S,T)+δ(T,E)=L...
Set so that (16) is satisfied (106. See Figure 3).

尚詳細には、このような中継点Tは第5図から第8図に
示す方法により設定することができる。まず第5図に示
すように、2点S、Eに対するX方向距離Lx、y方向
距離Lyを算出した後、Lx。
In detail, such a relay point T can be set by the method shown in FIGS. 5 to 8. First, as shown in FIG. 5, after calculating the distance Lx in the X direction and the distance Ly in the y direction with respect to the two points S and E, Lx.

Ly、及びLの関係が図中のどの場合に相当するか検索
する。次にその場合に応じて、第6図がら第8図に示す
ような中継点を設定可能な探索線Tm工、Tmz+ T
Qr、TD2を決定する。ここで第6図、第7図、第8
図はそれぞれ、第5図における場合■、■、■に対応し
た探索線の決定方法を示している。そして最後に、求ま
った中継点設定可能な探索線上の格子点の中から配線可
能な未使用の格子点を選択することで、(16)式を満
足する中継点Tを求めることができる。
A search is made to determine which case in the diagram the relationship between Ly and L corresponds to. Next, depending on the case, a search line Tm construction, Tmz + T, which can set relay points as shown in FIGS.
Determine Qr and TD2. Here, Figures 6, 7, and 8
Each figure shows a method for determining the search line corresponding to cases (2), (2), and (2) in FIG. 5, respectively. Finally, by selecting an unused lattice point that can be wired from among the lattice points on the search line where the relay point can be set, it is possible to find the relay point T that satisfies the equation (16).

以上のようにして求めた中継点Tにより分解された2つ
の区間(S、T)、(T、E)に対し、ステップ107
,108で示す最短なる配線経路探索を実行した後(第
4図参照)、配線経路探索により決定した配線パターン
をパターン情報格納ファイル204に出力して(109
)、処理を終了する。
Step 107
, 108 (see FIG. 4), the wiring pattern determined by the wiring route search is output to the pattern information storage file 204 (109).
), the process ends.

一方、判定105において、(15)式を満足しない場
合は、上記最小距離δ(S、E)と指定配線長しの関係
が、 δ(S、E)>L+ΔL        ・・・(17
)となることを意味し、このような配線経路の発見は物
理的に不可能であるのでただちに処理を終了する。
On the other hand, in judgment 105, if formula (15) is not satisfied, the relationship between the minimum distance δ(S, E) and the specified wiring length is δ(S, E)>L+ΔL (17
), and since it is physically impossible to discover such a wiring route, the process is immediately terminated.

以上、本発明による配線長指定配線方法の一実施例を説
明したが、本実施例によれば配線対象区間の始点位置、
終点位置間のX方向距離、y方向距離と指定配線長の関
係に応じて、斜め配線層を含んだ少なくとも3層以上の
配線層を対象とした中継点の設定及び配線経路探索を、
配線対象区間のマンハッタン距離との大小に係らず実行
可能であり、物理的に配線経路の発見が可能な限り、任
意の指定配線長で配線パターンを決定することができる
An embodiment of the wiring length specified wiring method according to the present invention has been described above. According to this embodiment, the starting point position of the wiring target section,
Setting relay points and searching wiring routes for at least three or more wiring layers, including diagonal wiring layers, according to the relationship between the distance in the X direction, the distance in the y direction, and the specified wiring length between end point positions.
This is possible regardless of the size of the Manhattan distance of the wiring target section, and as long as the wiring route can be physically discovered, the wiring pattern can be determined with any specified wiring length.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、配線対象区間のマンハッタン距離と指
定される配線長との大小に係らず、任意の配線長で配線
パターンの自動決定が可能であり、信号遅延や回路動作
特性を高精度に考慮した配線設計を可能とするという効
果がある。
According to the present invention, it is possible to automatically determine a wiring pattern with an arbitrary wiring length, regardless of the magnitude of the Manhattan distance of the wiring target section and the specified wiring length, and to accurately determine signal delays and circuit operating characteristics. This has the effect of making it possible to take wiring design into consideration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の方法を説明するフローチャ
ート、第2図は本発明の一実施例の方法を実行する処理
システムの構成を示すブロック図、第3図から第8図は
本発明の一実施例の方法を説明する図、第9図から第1
1図は従来技術による配線経路の決定方法を説明する図
である。 S・・・配線対象区間の始点、E・・・配線対象区間の
終点、T・・・中継点、V 1 t V 2 t・・・
・・・ビア(中継穴)、px、pyl Pas・=配線
経路、T Q xt T fl SrTmz、Tmz、
Txt、Txz、Tyt、Tyz°°°中継点設定用探
索線、RQl、RQz、Rml、Rmz。 RXl、RX2.Ryx、Ryz−中継点設定用探索線
の決定が許される領域。
FIG. 1 is a flowchart explaining a method according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a processing system that executes a method according to an embodiment of the present invention, and FIGS. Figures 9 to 1 for explaining the method of one embodiment of the invention.
FIG. 1 is a diagram illustrating a method for determining a wiring route according to the prior art. S...Start point of the wiring target section, E...End point of the wiring target section, T...Relay point, V1 t V2 t...
... Via (relay hole), px, pyl Pas・= wiring route, T Q xt T fl SrTmz, Tmz,
Txt, Txz, Tyt, Tyz°°° relay point setting search line, RQl, RQz, Rml, Rmz. RXl, RX2. Ryx, Ryz - area where determination of search line for relay point setting is permitted.

Claims (1)

【特許請求の範囲】 1、プリント基板、集積回路等における信号遅延時間制
約を考慮した配線パターンを、斜め方向配線層を含む少
なくとも3層以上の配線層を同時に配線対象層として決
定する配線長指定配線方法において、下記の(a)ない
し(e)の配線経路決定手続きを有することを特徴とす
る配線長指定配線方法。 (a)配線経路を決定すべき配線対象区間に対し、該配
線対象区間の始点位置、終点位置、及び該配線対象区間
に対する配線経路長許容範囲の上限値、下限値を入力し
、手続き(b)を実行する。 (b)上記始点位置と終点位置を結ぶ、上記配線対象層
を用いて実現可能な、最小距離を算出し、手続き(c)
を実行する。 (c)上記始点位置と終点位置を結ぶ最小距離と上記配
線経路長許容範囲とを比較し、該最小距離が該配線経路
長の許容範囲内ならば、該始点位置から該終点位置に至
る最短なる配線経路探索を行なった後、配線経路決定手
続きを終了する。 (d)中継点を、上記始点位置と該中継点位置を結ぶ上
記配線対象層上での最小距離と、該中継点位置と上記終
点位置を結ぶ上記配線対象層上での最小距離の和が、上
記配線経路長の許容範囲内になるように設定し、手続き (e)を実行する。 (e)上記始点位置から上記中継点位置に至る最短なる
配線経路探索及び、上記中継点位置から上記終点位置に
至る最短なる配線経路探索を行なった後、配線経路決定
手続きを終了する。 2、プリント基板、集積回路等における信号遅延時間制
約を考慮した配線パターンを、斜め方向配線層を含む少
なくとも3層以上の配線層を同時に配線対象層として決
定する配線長指定配線システムにおいて、 (a)配線経路を決定すべき配線対象区間に対し、該配
線対象区間の始点位置、終点位置、及び該配線対象区間
に対する配線経路長許容範囲の上限値、下限値を入力す
る手段、 (b)上記始点位置と終点位置を結ぶ、上記配線対象層
を用いて実現可能な、最小距離を算出する手段、 (c)上記始点位置と終点位置を結ぶ最小距離と上記配
線経路長許容範囲とを比較する手段、(d)中継点を、
上記始点位置と該中継点位置を結ぶ上記配線対象層上で
の最小距離と、該中継点位置と上記終点位置を結ぶ上記
配線対象層上での最小距離の和が、上記配線経路長の許
容範囲内になるように設定する手段、 (e)上記始点位置から上記中継点位置に至る最短なる
配線経路探索及び、上記中継点位置から上記終点位置に
至る最短なる配線経路探索を行なう手段、 を有することを特徴とする配線長指定配線システム。
[Claims] 1. Wiring length specification that simultaneously determines a wiring pattern that takes into account signal delay time constraints in printed circuit boards, integrated circuits, etc., with at least three wiring layers including diagonal wiring layers as wiring target layers. A wiring method for specifying a wiring length, characterized in that the wiring method includes the following wiring route determination procedures (a) to (e). (a) For the wiring target section for which the wiring route is to be determined, input the starting point position, end point position, and upper and lower limits of the permissible wiring route length range for the wiring target section, and proceed in step (b). ). (b) Calculate the minimum distance that can be realized using the wiring target layer connecting the starting point position and the ending point position, and proceed to step (c)
Execute. (c) Compare the minimum distance connecting the starting point position and the ending point position with the wiring route length tolerance range, and if the minimum distance is within the wiring route length tolerance range, the shortest distance from the starting point position to the ending point position. After performing the wiring route search, the wiring route determination procedure ends. (d) The sum of the minimum distance on the wiring target layer connecting the relay point between the start point position and the relay point position and the minimum distance on the wiring target layer connecting the relay point position and the end point position is , the wiring path length is set to be within the permissible range, and procedure (e) is executed. (e) After searching for the shortest wiring route from the starting point position to the relay point position and searching for the shortest wiring route from the relay point position to the end point position, the wiring route determination procedure is ended. 2. In a wiring length specified wiring system in which a wiring pattern that takes into account signal delay time constraints in printed circuit boards, integrated circuits, etc., at least three wiring layers including diagonal wiring layers are simultaneously determined as wiring target layers, (a ) Means for inputting, for a wiring target section for which a wiring route is to be determined, the starting point position and end point position of the wiring target section, and the upper and lower limit values of the permissible wiring route length range for the wiring target section; (b) the above; means for calculating the minimum distance connecting the starting point position and the ending point position that can be realized using the wiring target layer; (c) comparing the minimum distance connecting the starting point position and the ending point position with the wiring route length tolerance range; means, (d) a relay point;
The sum of the minimum distance on the wiring target layer connecting the starting point position and the relay point position and the minimum distance on the wiring target layer connecting the relay point position and the end point position is the allowable wiring route length. (e) means for searching for the shortest wiring route from the starting point position to the relay point position and searching for the shortest wiring route from the relay point position to the end point position; A wire length specified wiring system characterized by having:
JP2100335A 1990-04-18 1990-04-18 Method and system for wiring assigned wiring length Pending JPH04677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2100335A JPH04677A (en) 1990-04-18 1990-04-18 Method and system for wiring assigned wiring length

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2100335A JPH04677A (en) 1990-04-18 1990-04-18 Method and system for wiring assigned wiring length

Publications (1)

Publication Number Publication Date
JPH04677A true JPH04677A (en) 1992-01-06

Family

ID=14271273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2100335A Pending JPH04677A (en) 1990-04-18 1990-04-18 Method and system for wiring assigned wiring length

Country Status (1)

Country Link
JP (1) JPH04677A (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963566A (en) * 1986-03-28 1990-10-16 Otsuka Pharmaceutical Co., Ltd. Benzimidazolyl-sulfinyl-tetrahydroquinolines
US6687893B2 (en) 2001-01-19 2004-02-03 Cadence Design Systems, Inc. Method and apparatus for pre-computing routes for multiple wiring models
US6858935B1 (en) 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Simulating euclidean wiring directions using manhattan and diagonal directional wires
US6858928B1 (en) * 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Multi-directional wiring on a single metal layer
US6859916B1 (en) 2001-06-03 2005-02-22 Cadence Design Systems, Inc. Polygonal vias
US6882055B1 (en) 2001-06-03 2005-04-19 Cadence Design Systems, Inc. Non-rectilinear polygonal vias
US6889372B1 (en) 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US6892371B1 (en) 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US6895567B1 (en) 2001-06-03 2005-05-17 Cadence Design Systems, Inc. Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs
US6895569B1 (en) 2001-06-03 2005-05-17 Candence Design Systems, Inc. IC layout with non-quadrilateral Steiner points
US6951005B1 (en) 2001-06-03 2005-09-27 Cadence Design Systems, Inc. Method and apparatus for selecting a route for a net based on the impact on other nets
US6951006B1 (en) 2002-01-22 2005-09-27 Cadence Design Systems, Inc. Decomposing IC regions and embedding routes
US6976238B1 (en) 2001-06-03 2005-12-13 Cadence Design Systems, Inc. Circular vias and interconnect-line ends
US7310793B1 (en) 2001-06-03 2007-12-18 Cadence Design Systems, Inc. Interconnect lines with non-rectilinear terminations
US7340711B2 (en) 2004-06-04 2008-03-04 Cadence Design Systems, Inc. Method and apparatus for local preferred direction routing
US7412682B2 (en) 2004-06-04 2008-08-12 Cadence Design Systems, Inc Local preferred direction routing
US7441220B2 (en) 2000-12-07 2008-10-21 Cadence Design Systems, Inc. Local preferred direction architecture, tools, and apparatus
US7594196B2 (en) 2000-12-07 2009-09-22 Cadence Design Systems, Inc. Block interstitching using local preferred direction architectures, tools, and apparatus
US7707537B2 (en) 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US8201128B2 (en) 2006-06-16 2012-06-12 Cadence Design Systems, Inc. Method and apparatus for approximating diagonal lines in placement

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5929247A (en) * 1982-08-11 1984-02-16 Hitachi Ltd Method for wiring printed circuit board
JPS62216075A (en) * 1986-03-11 1987-09-22 Fujitsu Ltd Automatic wiring system with designated length

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5929247A (en) * 1982-08-11 1984-02-16 Hitachi Ltd Method for wiring printed circuit board
JPS62216075A (en) * 1986-03-11 1987-09-22 Fujitsu Ltd Automatic wiring system with designated length

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963566A (en) * 1986-03-28 1990-10-16 Otsuka Pharmaceutical Co., Ltd. Benzimidazolyl-sulfinyl-tetrahydroquinolines
US6889372B1 (en) 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US6900540B1 (en) 2000-12-07 2005-05-31 Cadence Design Systems, Inc. Simulating diagonal wiring directions using Manhattan directional wires
US6858935B1 (en) 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Simulating euclidean wiring directions using manhattan and diagonal directional wires
US6858928B1 (en) * 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Multi-directional wiring on a single metal layer
US8166442B2 (en) 2000-12-07 2012-04-24 Cadence Design Systems, Inc. Local preferred direction architecture
US6870255B1 (en) * 2000-12-07 2005-03-22 Cadence Design Systems, Inc. Integrated circuit wiring architectures to support independent designs
US7594196B2 (en) 2000-12-07 2009-09-22 Cadence Design Systems, Inc. Block interstitching using local preferred direction architectures, tools, and apparatus
US7441220B2 (en) 2000-12-07 2008-10-21 Cadence Design Systems, Inc. Local preferred direction architecture, tools, and apparatus
US6687893B2 (en) 2001-01-19 2004-02-03 Cadence Design Systems, Inc. Method and apparatus for pre-computing routes for multiple wiring models
US6915500B1 (en) 2001-06-03 2005-07-05 Cadence Design Systems, Inc. Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiring
US6882055B1 (en) 2001-06-03 2005-04-19 Cadence Design Systems, Inc. Non-rectilinear polygonal vias
US6895567B1 (en) 2001-06-03 2005-05-17 Cadence Design Systems, Inc. Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs
US6951005B1 (en) 2001-06-03 2005-09-27 Cadence Design Systems, Inc. Method and apparatus for selecting a route for a net based on the impact on other nets
US6895569B1 (en) 2001-06-03 2005-05-17 Candence Design Systems, Inc. IC layout with non-quadrilateral Steiner points
US6976238B1 (en) 2001-06-03 2005-12-13 Cadence Design Systems, Inc. Circular vias and interconnect-line ends
US7143383B1 (en) 2001-06-03 2006-11-28 Cadence Design Systems, Inc. Method for layout of gridless non manhattan integrated circuits with tile based router
US7310793B1 (en) 2001-06-03 2007-12-18 Cadence Design Systems, Inc. Interconnect lines with non-rectilinear terminations
US6859916B1 (en) 2001-06-03 2005-02-22 Cadence Design Systems, Inc. Polygonal vias
US6951006B1 (en) 2002-01-22 2005-09-27 Cadence Design Systems, Inc. Decomposing IC regions and embedding routes
US6892371B1 (en) 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US7412682B2 (en) 2004-06-04 2008-08-12 Cadence Design Systems, Inc Local preferred direction routing
US7707537B2 (en) 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US8010929B2 (en) 2004-06-04 2011-08-30 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US7340711B2 (en) 2004-06-04 2008-03-04 Cadence Design Systems, Inc. Method and apparatus for local preferred direction routing
US8201128B2 (en) 2006-06-16 2012-06-12 Cadence Design Systems, Inc. Method and apparatus for approximating diagonal lines in placement

Similar Documents

Publication Publication Date Title
JPH04677A (en) Method and system for wiring assigned wiring length
US7673269B2 (en) Automatic trace determination apparatus and method
JP4859513B2 (en) Wiring design method and design apparatus therefor
JP4311244B2 (en) Wiring route determination method and system
EP1762953A1 (en) Automatic trace determination method
US5483481A (en) Automatic wiring device for design of semiconductor integrated circuit
KR102592599B1 (en) Method for verifying a layout designed for semiconductor integrated circuit and a computer system perforing the same
US6640332B2 (en) Wiring pattern decision method considering electrical length and multi-layer wiring board
JP4663473B2 (en) Semiconductor device design support apparatus, semiconductor device design support method, program capable of executing the method by computer, and recording medium recording the program
JPH10198722A (en) Production system for interactive wiring pattern
JPH1195407A (en) Photomask
US20090007049A1 (en) Automatic trace design method
US7536667B2 (en) Method of semiconductor device and design supporting system of semiconductor device
JP3184132B2 (en) Hierarchical layout design method
JPH01225335A (en) Automatic wiring processing apparatus
US5917206A (en) Gate array system in which functional blocks are connected by fixed wiring
JP2986279B2 (en) Wiring method and printed circuit board design system
JP2936089B2 (en) Method of creating shape data for mold processing
JPH06309414A (en) Method for supporting wiring
JP3589988B2 (en) Clock skew improvement method
JPH0550029B2 (en)
JPH03204777A (en) Display device for circuit connecting information
JPH0683911A (en) Method and device for determining wiring path
JPH01305474A (en) Method for supporting wiring for unwired section
JPH02203587A (en) Printed wiring board