JPH04677A - Method and system for wiring assigned wiring length - Google Patents

Method and system for wiring assigned wiring length

Info

Publication number
JPH04677A
JPH04677A JP10033590A JP10033590A JPH04677A JP H04677 A JPH04677 A JP H04677A JP 10033590 A JP10033590 A JP 10033590A JP 10033590 A JP10033590 A JP 10033590A JP H04677 A JPH04677 A JP H04677A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
wiring
direction
assigned
δ
relay point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10033590A
Inventor
Yasuyuki Fujiwara
Jiro Kusuhara
Yutaka Sekiyama
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0005Apparatus or processes for manufacturing printed circuits for designing circuits by computer

Abstract

PURPOSE: To attain route determination with arbitrary assigned wiring length by giving a means to determine a searching line for setting a relay point to a position so that the sum of the distance between a starting point and the relay point and the distance between the relay point and an end point may be the assigned wiring length neither too much nor too little.
CONSTITUTION: The assigned wiring length of a section (S,E) is found while using the total 4 layers of the (x) direction, (y) direction, oblique +45° direction and oblique -45° direction wiring layers simultaneously regradless of the size relation of assigned wiring length L and Manhattan distance. After setting a relay point T so as to satisfy δ (S,T)+δ (T,E)=L to the wiring object section (S,E) in advance, the shortest wiring route searching is executed with a labyrinth method, a segment searching method, etc., by using the (x) and (y) direction and oblique ±45° direction wiring layers simultaneously to the plural sections (S,T) and (T,E) divided by the relay point T and a wiring route is determined. The δ (S,T) and the δ (T,E) mean the minimum distance able to be realized by using the above-mentioned 4 wiring layers to the sections (S,T) and (T,E) repectively. Thus, the route can be determined by the arbitrary assigned wiring length.
COPYRIGHT: (C)1992,JPO&Japio
JP10033590A 1990-04-18 1990-04-18 Method and system for wiring assigned wiring length Pending JPH04677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10033590A JPH04677A (en) 1990-04-18 1990-04-18 Method and system for wiring assigned wiring length

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10033590A JPH04677A (en) 1990-04-18 1990-04-18 Method and system for wiring assigned wiring length

Publications (1)

Publication Number Publication Date
JPH04677A true true JPH04677A (en) 1992-01-06

Family

ID=14271273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10033590A Pending JPH04677A (en) 1990-04-18 1990-04-18 Method and system for wiring assigned wiring length

Country Status (1)

Country Link
JP (1) JPH04677A (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963566A (en) * 1986-03-28 1990-10-16 Otsuka Pharmaceutical Co., Ltd. Benzimidazolyl-sulfinyl-tetrahydroquinolines
US6687893B2 (en) 2001-01-19 2004-02-03 Cadence Design Systems, Inc. Method and apparatus for pre-computing routes for multiple wiring models
US6859916B1 (en) 2001-06-03 2005-02-22 Cadence Design Systems, Inc. Polygonal vias
US6858935B1 (en) 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Simulating euclidean wiring directions using manhattan and diagonal directional wires
US6858928B1 (en) * 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Multi-directional wiring on a single metal layer
US6882055B1 (en) 2001-06-03 2005-04-19 Cadence Design Systems, Inc. Non-rectilinear polygonal vias
US6889372B1 (en) 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US6892371B1 (en) 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US6895567B1 (en) 2001-06-03 2005-05-17 Cadence Design Systems, Inc. Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs
US6895569B1 (en) 2001-06-03 2005-05-17 Candence Design Systems, Inc. IC layout with non-quadrilateral Steiner points
US6951005B1 (en) 2001-06-03 2005-09-27 Cadence Design Systems, Inc. Method and apparatus for selecting a route for a net based on the impact on other nets
US6951006B1 (en) 2002-01-22 2005-09-27 Cadence Design Systems, Inc. Decomposing IC regions and embedding routes
US6976238B1 (en) 2001-06-03 2005-12-13 Cadence Design Systems, Inc. Circular vias and interconnect-line ends
US7310793B1 (en) 2001-06-03 2007-12-18 Cadence Design Systems, Inc. Interconnect lines with non-rectilinear terminations
US7340711B2 (en) 2004-06-04 2008-03-04 Cadence Design Systems, Inc. Method and apparatus for local preferred direction routing
US7412682B2 (en) 2004-06-04 2008-08-12 Cadence Design Systems, Inc Local preferred direction routing
US7441220B2 (en) 2000-12-07 2008-10-21 Cadence Design Systems, Inc. Local preferred direction architecture, tools, and apparatus
US7594196B2 (en) 2000-12-07 2009-09-22 Cadence Design Systems, Inc. Block interstitching using local preferred direction architectures, tools, and apparatus
US7707537B2 (en) 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US8201128B2 (en) 2006-06-16 2012-06-12 Cadence Design Systems, Inc. Method and apparatus for approximating diagonal lines in placement

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5929247A (en) * 1982-08-11 1984-02-16 Hitachi Ltd Method for wiring printed circuit board
JPS62216075A (en) * 1986-03-11 1987-09-22 Fujitsu Ltd Automatic wiring system with designated length

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5929247A (en) * 1982-08-11 1984-02-16 Hitachi Ltd Method for wiring printed circuit board
JPS62216075A (en) * 1986-03-11 1987-09-22 Fujitsu Ltd Automatic wiring system with designated length

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963566A (en) * 1986-03-28 1990-10-16 Otsuka Pharmaceutical Co., Ltd. Benzimidazolyl-sulfinyl-tetrahydroquinolines
US6889372B1 (en) 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US7594196B2 (en) 2000-12-07 2009-09-22 Cadence Design Systems, Inc. Block interstitching using local preferred direction architectures, tools, and apparatus
US6858935B1 (en) 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Simulating euclidean wiring directions using manhattan and diagonal directional wires
US6858928B1 (en) * 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Multi-directional wiring on a single metal layer
US6870255B1 (en) * 2000-12-07 2005-03-22 Cadence Design Systems, Inc. Integrated circuit wiring architectures to support independent designs
US6900540B1 (en) 2000-12-07 2005-05-31 Cadence Design Systems, Inc. Simulating diagonal wiring directions using Manhattan directional wires
US8166442B2 (en) 2000-12-07 2012-04-24 Cadence Design Systems, Inc. Local preferred direction architecture
US7441220B2 (en) 2000-12-07 2008-10-21 Cadence Design Systems, Inc. Local preferred direction architecture, tools, and apparatus
US6687893B2 (en) 2001-01-19 2004-02-03 Cadence Design Systems, Inc. Method and apparatus for pre-computing routes for multiple wiring models
US6895567B1 (en) 2001-06-03 2005-05-17 Cadence Design Systems, Inc. Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs
US6895569B1 (en) 2001-06-03 2005-05-17 Candence Design Systems, Inc. IC layout with non-quadrilateral Steiner points
US6915500B1 (en) 2001-06-03 2005-07-05 Cadence Design Systems, Inc. Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiring
US6882055B1 (en) 2001-06-03 2005-04-19 Cadence Design Systems, Inc. Non-rectilinear polygonal vias
US6859916B1 (en) 2001-06-03 2005-02-22 Cadence Design Systems, Inc. Polygonal vias
US6976238B1 (en) 2001-06-03 2005-12-13 Cadence Design Systems, Inc. Circular vias and interconnect-line ends
US7143383B1 (en) 2001-06-03 2006-11-28 Cadence Design Systems, Inc. Method for layout of gridless non manhattan integrated circuits with tile based router
US7310793B1 (en) 2001-06-03 2007-12-18 Cadence Design Systems, Inc. Interconnect lines with non-rectilinear terminations
US6951005B1 (en) 2001-06-03 2005-09-27 Cadence Design Systems, Inc. Method and apparatus for selecting a route for a net based on the impact on other nets
US6951006B1 (en) 2002-01-22 2005-09-27 Cadence Design Systems, Inc. Decomposing IC regions and embedding routes
US6892371B1 (en) 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US7412682B2 (en) 2004-06-04 2008-08-12 Cadence Design Systems, Inc Local preferred direction routing
US7340711B2 (en) 2004-06-04 2008-03-04 Cadence Design Systems, Inc. Method and apparatus for local preferred direction routing
US7707537B2 (en) 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US8010929B2 (en) 2004-06-04 2011-08-30 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US8201128B2 (en) 2006-06-16 2012-06-12 Cadence Design Systems, Inc. Method and apparatus for approximating diagonal lines in placement

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