JP4663473B2 - Semiconductor device design support apparatus, semiconductor device design support method, program capable of executing the method by computer, and recording medium recording the program - Google Patents

Description

  The present invention relates to a semiconductor device design support apparatus, a semiconductor device design support method, a program that can be executed by a computer, and a recording medium that records the program, and in particular, includes a substrate and a chip disposed on the substrate. The present invention relates to a semiconductor device design support apparatus that supports the design of a semiconductor device.

  In recent years, with the progress of LSI manufacturing process technology, the degree of integration of LSIs on a substrate has further increased, and the concept of SiP (system in a package) has come out. SiP is a technology for manufacturing a minute system by three-dimensionally mounting a plurality of IC chips and passive elements on a minute printed board. Compared to SoC (System On a Chip), in which circuits are written on a silicon chip, i) Mass production is possible with existing chips, ii) Small capital investment, and iii) Small quantity It has advantages such as advantageous for the production of various varieties.

  Conventionally, in the design of this SiP, the designer has designed the terminals of the SiP substrate by replacing them, but the LSI chip terminals have been dealt with by requesting another department.

  In addition, although it is not the technique regarding SiP, there exists patent document 1 as a literature which shows the technique regarding the conventional semiconductor chip design, for example.

JP 2004-31891 A

  However, in the conventional design, the connection state between the terminals is determined by humans. The wiring shape was also manual wiring based on experience. Therefore, it was unclear whether the terminals were really designed to have the shortest wiring between the terminals.

  Furthermore, the chip-side terminals are dealt with by requesting another department, and there is a high possibility that information transmission errors will occur.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device design support apparatus and a semiconductor device design support method that are compatible with support for designing a semiconductor device in which a terminal of a substrate and a terminal of a chip disposed on the substrate are connected by electrical wiring. The present invention proposes a program that can be executed by a computer and a recording medium that records the program.

According to a first aspect of the present invention, there is provided a semiconductor device design that supports a design of a semiconductor device having a substrate and a chip disposed on the substrate, wherein a terminal of the substrate and a terminal of the chip are connected by electrical wiring. In the support device, by changing the position of the terminal of the substrate or the chip, when at least one of the wirings connected to the terminal intersects at least one of the other wirings, Check whether the position can be changed, change the position of the terminal if it can be changed, and change the position of the terminal so that if the wiring connected to the terminal does not intersect with other wiring, Terminal position changing means that does not change the position of the terminal is provided.

In an SiP, when an LSI chip is mounted and wired, it is often wired by wire bonding. When a high-frequency signal passes through a wire wired in the air, if the wiring is parallel, the influence of the signal of the adjacent wiring is large, and noise is generated.

A second aspect of the present invention is the semiconductor device design support apparatus according to the first aspect, wherein the terminal position changing means is a length of a parallel portion of a wiring connected to the terminal whose position is changed and another wiring. The position of the terminal is changed on the basis of the condition regarding.

The longer the distance in which the wirings are parallel, the greater the possibility that the signals between the wirings interfere with each other to generate noise. According to the second aspect of the present invention, since the wirings are designed not to be parallel to a certain distance, it is possible to prevent the generation of noise.

The invention according to claim 3 is the semiconductor device design support apparatus according to claim 1 or 2, wherein the terminal position changing unit changes the position of the terminal of the substrate, and Chip terminal position change processing means for changing the position of the terminal of the chip is provided.

The invention according to claim 4 is the semiconductor device design support apparatus according to any one of claims 1 to 3, wherein the terminal position changing means includes a wiring connected to the terminal whose position is changed and another wiring. The position of the terminal is changed based on the condition regarding the distance.

In general, noise due to a signal between wirings decreases as the wiring interval increases. According to the fourth aspect of the invention, since the wiring is performed so that the interval between the signal lines becomes larger than a certain value, the generation of noise can be prevented.

The invention according to claim 5 is the semiconductor device design support apparatus according to any one of claims 1 to 4, wherein a replacement destination terminal satisfying a predetermined condition is determined for a specified replacement target terminal. Terminal replacement destination determination processing means is provided, and the terminal position changing means replaces the position of the replacement target terminal and the position of the replacement destination terminal determined by the terminal replacement destination determination processing means.

A sixth aspect of the present invention is the semiconductor device design support apparatus according to any one of the first to fifth aspects, wherein the three-dimensional layout or wiring design is supported .

According to a seventh aspect of the present invention, there is provided a semiconductor device design that supports a design of a semiconductor device having a substrate and a chip disposed on the substrate, wherein a terminal of the substrate and a terminal of the chip are connected by electrical wiring. In the support device, when the positions of the first terminal and the second terminal are exchanged for the two first and second terminals of the substrate or the chip, the first terminal and the second terminal When at least one of the wirings connected to the two terminals intersects with at least one of the other wirings, it is checked whether the positions of the first and second terminals are interchangeable. When the positions of the second terminal are exchanged and the positions of the first terminal and the second terminal are exchanged, the wiring connected to the first terminal and the second terminal is another wiring. When not intersecting with the first and previous Those having a terminal position changing means not to swap the position of the second terminal.

According to an eighth aspect of the present invention, there is provided a semiconductor device design that includes a substrate and a chip disposed on the substrate, and supports a design of a semiconductor device in which a terminal of the substrate and a terminal of the chip are connected by electrical wiring. In the support method, the terminal position changing unit changes the position of the terminal of the substrate or the chip, so that at least one of the wirings connected to the terminal intersects with at least one of the other wirings. If checks whether the position of the terminal can be changed, cross by change the position of the terminal if it can be modified to change the position of the terminal, wiring connected to the terminals with another wiring If not, the step of not changing the position of the terminal is included.

The invention according to claim 9 is a program for causing a computer to execute the semiconductor device design support method according to claim 8.

The invention according to claim 10 is a computer-readable recording medium for recording the program according to claim 9.

As described above, according to the present invention, it is possible to simultaneously design the positions of the terminals of the substrate and the terminals of the chip. Unlike the design of the position of the terminal of the SiP substrate on the premise of the position of the terminal of the LSI chip, this design enables the design of the terminal of the substrate and the terminal of the chip together. Become. Further, it becomes unnecessary to request other departments to deal with the chip-side terminal, and it is possible to prevent transmission errors between departments. Furthermore, according to the present invention, the terminal of the substrate and the terminal of the chip can be arranged so that, for example, the area and volume of the connection between them can be minimized three-dimensionally, and the manufacturing cost can be minimized. It becomes. Further, the terminals can be automatically arranged, and an arrangement equivalent to the arrangement / wiring quality by a skilled engineer is possible.

As described above, in an SiP, when an LSI chip is mounted and wired, it is often wired by wire bonding. When a high-frequency signal passes through a wire wired in the air, if the wiring is parallel, the influence of the signal of the adjacent wiring is large, and noise is generated. On the other hand, according to the present invention, it is possible to prevent the wiring from being parallel so that the terminal position changing means crosses the wiring, and the generation of noise can be prevented. In addition, the longer the distance in which the wirings are parallel, the greater the possibility that the signals between the wirings interfere with each other to generate noise. On the other hand, according to the second aspect of the present invention, since the wirings are designed not to be parallel to a certain distance, it is possible to prevent the generation of noise.

  FIG. 1 is a schematic block diagram of a SiP design support apparatus according to an embodiment of the present invention.

  Referring to FIG. 1, a SiP design support apparatus 1 includes a control unit 3, a terminal of an SiP substrate that is electrically connected (hereinafter referred to as “PAD”), and a terminal of an LSI chip (hereinafter referred to as “chip terminal”). ), And an automatic rewiring processing unit 7 for performing wiring from the PAD to the VIA / terminal on the SiP substrate. The terminal processing unit 5 includes a terminal replacement destination determination processing unit 9 that determines a replacement destination terminal with respect to a replacement target terminal selected by a user, and a terminal position change processing unit 11 that changes the position of the terminal. The terminal replacement destination determination processing unit 9 includes a PAD replacement destination determination processing unit 13 that performs replacement destination determination processing regarding PAD and a chip terminal replacement destination determination processing unit 15 that performs replacement destination determination processing regarding chip terminals. In addition, the terminal position change processing unit 11 includes a PAD position change processing unit 17 that performs a position change process on the PAD and a chip terminal position change processing unit 19 that performs a position change process on the chip terminal.

  Here, in the change, only the connection information is changed without changing the PAD position on the substrate and the terminal position of the chip. That is, in the SiP design support apparatus 1, information on which PAD and terminal are connected is given between the PAD on the substrate and the terminal of the LSI chip. When the connected PAD and terminal are changed, the physical position is not changed, and only the connection information between the PAD and the terminal is changed. Therefore, it seems that the position of the changed PAD and the terminal has moved to the position after the change, but in reality, the position is not changed but only the connection information is changed. In addition, redrawing of the wire connected to the position-changed PAD or terminal is also performed.

  The automatic rewiring processing unit 7 performs one-layer, 45 ° wiring from the PAD to the VIA / terminal on the substrate using the maze method. Here, the maze method is one of the wiring algorithms, and the wiring area is divided on the mesh, numbered in a ripple pattern from the wiring base point to the end point, and the shortest when the number reaches the end point. This is a method to determine the shortest wiring route from the start point to the end point by the number

  An example of the operation of the SiP design support apparatus 1 of FIG. 1 will be described with reference to FIG. FIG. 2 is a diagram illustrating an example of the terminal position change by the SiP design support apparatus 1 of FIG. 1, and the connection state between the PAD 25 to 39 of the SiP substrate 21 and the chip terminal of the LSI chip 23 before and after the change. FIG. FIG. 2A is a diagram illustrating an example of the connection state between the PAD and the chip terminal before the change, and FIG. 2B is a diagram illustrating an example of the connection state between the PAD and the chip terminal after the change.

  Referring to FIG. 2A, an LSI chip 23 is disposed on the SiP substrate 21, and the SiP substrate 21 has four PADs 25, 27, 29, 31 on one side with the LSI chip 23 interposed therebetween. There are four PADs 33, 35, 37, 39 on the other side. The PADs 25 to 39 of the SiP substrate 21 and the chip terminals of the LSI chip 23 are connected to the closest chip terminals of the six PADs 25, 29, 31, 33, 35 and 39, respectively, while the PAD 27 is the chip closest to the PAD 37. Connected to the terminal 41, the PAD 37 is connected to the chip terminal 43 closest to the PAD 27.

  In the connected state as shown in FIG. 2A, the positions of the PAD 27 and PAD 37 are exchanged, or the positions of the chip terminal 41 and the chip terminal 43 are exchanged, so that as shown in FIG. The total connection between the PAD and the chip terminal of the LSI chip is the shortest. The SiP design support apparatus 1 in FIG. 1 performs processing for changing the positions of such PADs and chip terminals.

  Next, an example of the operation of the SiP design support apparatus 1 in FIG. 1 will be described with reference to FIG. FIG. 3 is a flowchart showing an example of the operation of the SiP design support apparatus 1 of FIG.

  First, the control unit 3 in FIG. 1 performs initial setting (step STM1 in FIG. 3). This initial setting is performed, for example, by checking an argument or reading a parameter file, an input file, or a control file.

  Next, the terminal processing unit 5 in FIG. 1 performs a process of changing the position of the PAD and the chip terminal (step STM2 in FIG. 3). An example of the process of changing the position of the PAD or the chip terminal will be described later with reference to FIGS.

  Next, the automatic rewiring processing unit 7 in FIG. 1 performs automatic rewiring processing from the PAD to the VIA / terminal on the substrate (step STM3 in FIG. 3). An example of this automatic rewiring process will be described later with reference to FIG. Then, the process of FIG. 3 ends.

  Next, an example of the terminal position changing process in step STM2 in FIG. 3 will be described with reference to FIG. FIG. 4 is a flowchart showing an example of the terminal position changing process in step STM2 of FIG.

  First, the terminal processing unit 5 in FIG. 1 determines whether or not the terminal to be exchanged selected by the user is a PAD (step STE1 in FIG. 4). If the terminal to be exchanged is a PAD, the process of step STE2 in FIG. 4 is performed, and if it is not a PAD, the process of step STE5 in FIG. 4 is performed.

  In step STE2 of FIG. 4, the terminal processing unit 5 of FIG. 1 determines whether an exchange destination is designated. If it is specified, the process of step STE4 in FIG. 4 is performed, and if not specified, the process of step STE3 in FIG. 4 is performed.

  In step STE3 in FIG. 4, the PAD conversion destination determination processing unit 9 in FIG. 1 performs a PAD exchange destination determination process. An example of the PAD exchange destination determination process will be described later with reference to FIGS. And the process of step STE4 of FIG. 4 is performed.

  In step STE4 in FIG. 4, the PAD position change processing unit 17 in FIG. 1 performs a PAD position change process. An example of the PAD position changing process will be described later with reference to FIGS. Then, the terminal processing unit 5 in FIG. 1 ends the processing in FIG.

  In step STE5 in FIG. 4, the terminal processing unit 5 in FIG. 1 determines whether an exchange destination is designated. If it is designated, the process of step STE7 in FIG. 4 is performed, and if not designated, the process of step STE6 in FIG. 4 is performed.

  In step STE6 in FIG. 4, the terminal conversion destination determination processing unit 13 in FIG. 1 performs a chip terminal replacement destination determination process. This chip terminal replacement destination determination process is the same as the PAD replacement destination determination process in step STE3 of FIG. And the process of step STE7 of FIG. 4 is performed.

  In step STE7 in FIG. 4, the chip terminal position change processing unit 19 in FIG. 1 performs chip terminal position change processing. This chip terminal position changing process is the same as the PAD position changing process in step STE4 of FIG. Then, the terminal processing unit 5 in FIG. 1 ends the processing in FIG.

  Next, an example of the PAD exchange destination determination process in step STE3 in FIG. 4 will be described with reference to FIGS. In this PAD exchange destination determination process, when there is one selected PAD, an exchange destination PAD is automatically determined for the selected PAD to be exchanged. The replacement PAD is determined based on rules such as a spacing rule described with reference to FIG. 7 and a parallel wiring length rule described with reference to FIG. At this time, by designating a specific net, a PAD that intersects the wire of the designated net after wire connection is recognized as an exchange partner. Note that the PAD of the designated net has a FIX attribute and is not subject to exchange with another PAD.

  FIG. 5 is a flowchart showing an example of the PAD exchange destination determination process in step STE3 of FIG.

  First, the PAD exchange destination determination processing unit 13 in FIG. 1 sets the selected PAD to be exchanged as PAD_A (step STT1 in FIG. 5).

  Next, the PAD exchange destination determination processing unit 13 in FIG. 1 acquires PADs from unprocessed PADs in a predetermined order, and sets the acquired PAD as PAD_B (step STT2 in FIG. 5). The order of acquisition is, for example, the order close to PAD_A or the order of priorities if priority is specified.

  Next, the PAD exchange destination determination processing unit 13 in FIG. 1 determines whether or not there is a designated net and if the wire of PAD_A is connected from the location of PAD_B, it does not cross the wire of the designated net (FIG. 5). Step STT3). If there is a designated net and does not intersect, the process of step STT6 in FIG. 5 is performed, otherwise the process of step STT4 in FIG. 5 is performed.

  In step STT4 of FIG. 5, the PAD exchange destination determination processing unit 13 of FIG. 1 checks the possibility of exchanging PAD_A and PAD_B. An example of the process for checking the exchangeability will be described later with reference to FIG.

  Next, the PAD exchange destination determination processing unit 13 in FIG. 1 determines whether or not PAD_A and PAD_B can be exchanged based on the result of the process in step STT4 in FIG. 5 (step STT5 in FIG. 5). If it is exchangeable, the process of step STT7 in FIG. 5 is performed, and if not, the process of step STT6 in FIG. 5 is performed.

  In step STT6 in FIG. 5, the PAD exchange destination determination processing unit 13 in FIG. 1 determines whether or not processing has been performed on all PADs. If the process is being performed, the process ends in error, and if not, the process of step STT2 in FIG. 5 is performed.

  In step STT7 of FIG. 5, the PAD exchange destination determination processing unit 13 of FIG. 1 designates PAD_B as the exchange destination of PAD_A.

  Next, the PAD exchange destination determination processing unit 13 in FIG. 1 determines whether or not there is a designated net (step STT8 in FIG. 5). If there is a designated net, the PAD of the corresponding net is set as FIX (step STT9 in FIG. 5), and the processing in FIG. 5 is terminated. If there is no designated net, the process of FIG. 5 is terminated.

  As described above, as shown in the flowchart of FIG. 5, the exchange destination PAD is determined for the exchange target PAD selected by the user.

  Next, an example of the process of checking the exchangeability of PAD_A and PAD_B in step STT4 in FIG. 5 will be described with reference to FIG. FIG. 6 is a flowchart showing an example of processing for checking the exchangeability of PAD_A and PAD_B in step STT4 of FIG.

  First, the PAD exchange destination determination processing unit 13 in FIG. 1 temporarily deletes the wire (step STC1 in FIG. 6). This temporary wire deletion process is performed for LINE (information connecting the PAD on the substrate side and the terminal on the LSI side) connected to PAD_A or PAD_B when the terminal of the LSI chip is connected to PAD_A or PAD_B. In this process, the bonding wire information (WIRE information) that is connected to the LSI chip terminal (PORTINST) is temporarily deleted.

  Next, the PAD replacement destination determination processing unit 13 in FIG. 1 provisionally performs wiring with the position of PAD_B as a new position of PAD_A (step STC2 in FIG. 6).

  Next, the PAD exchange destination determination processing unit 13 in FIG. 1 determines whether or not connection is possible (step STC3 in FIG. 6). If the connection is possible, the process of step STC4 in FIG. 6 is performed, and if not, the process of step STC8 in FIG. 6 is performed. An example of the determination of the possibility of connection will be described later with reference to FIGS.

  In step STC4 in FIG. 6, the PAD exchange destination determination processing unit 13 in FIG. 1 returns the connected wire length to the upper routine. Next, the connected wire shape is returned to the upper routine (step STC5 in FIG. 6). Next, the temporarily deleted wire is restored (step STC6 in FIG. 6), PAD_A and PAD_B are determined to be exchangeable (step STC7 in FIG. 6), and the processing in FIG. 6 is terminated.

  In step STC8 of FIG. 6, the PAD exchange destination determination processing unit 13 of FIG. 1 restores the temporarily deleted wire. Next, it is determined that PAD_A and PAD_B are not exchangeable (step STC9 in FIG. 6), and the processing in FIG. 6 is terminated.

  As described above, the exchangeability of PAD_A and PAD_B is checked as shown in the flowchart of FIG.

  Next, with reference to FIG. 7 and FIG. 8, an example of the determination of the connection possibility in step STC3 of FIG. 6 will be described.

  FIG. 7 is a diagram illustrating a bonding wire in a three-dimensional space that is newly created. With reference to FIG. 7, the spacing rule, that is, the rule relating to the bonding wire interval from the terminal of the arranged LSI chip to the PAD on the substrate will be described.

  Referring to FIG. 7, bond wire coordinates in a newly created three-dimensional space are P0, P1, P2, P3, and P4. Then, the distances between the other wires and the line segments P1-P2, P2-P3, P3-P4 are obtained, and the minimum value of the obtained distances is the distance between the other wires and the line segments P1-P2, P2-P3, P3-P4. And

  If the distance between the new bonding wire and the other wire is shorter than the specified distance, a spacing rule error occurs and the wire cannot be connected. In this way, a spacing rule with other wires is specified, and shape calculation satisfying this rule is performed.

  Subsequently, referring to FIG. 8, when there are a plurality of bonding wires from the terminals of the LSI chip to be arranged to the PAD on the substrate, the designated wires are wired in parallel. A rule regarding the minimum value of the distance will be described. FIG. 8 is a diagram showing the length of a parallel portion with respect to another wire when performing wire shape calculation. The length of the parallel portion is calculated when the wire A0-A1 whose shape has been calculated and the other wires B0-B1 are three-dimensionally parallel and within a certain distance. In FIG. 8, point A0 and point A1, point B0 and point B1 are points such that vector A0A1 and vector B0B1 are in the same direction, and point B0 ′ and point B1 ′ are point B0 and point B1, respectively. This is a point projected on the straight line A0-A1 in a direction perpendicular to the straight line A0-A1.

  FIG. 8A shows the length | A0-B1 ′ of the parallel part of the line segment A0-A1 and the line segment B0-B1 when the point B1 ′ is present on the line segment A0-A1 and there is no point B0 ′. FIG. With reference to FIG. 8A, a method of calculating the length | A0−B1 ′ | of the parallel portion will be described.

  Referring to FIG. 8A, if a unit vector obtained by dividing vector A0A1 by its length is vector e and the inner product of vector x and vector y is (x, y), the length of the parallel portion | A0−B1 ′ | is obtained by | (vector A0B1, vector e) |.

  There are six positional relationships between the points A0, A1, B0 ', and B1'. Below, with reference to FIG.8 (b)-(e), the length of the parallel part in each case is demonstrated.

  Referring to FIG. 8B, when line segment A0-A1 includes line segment B0′-B1 ′, that is, (A0B0, e)> = 0, (A0B1, e)> 0, (A1B0 ′, e) When <0, (A1B0, e) <= 0, the length of the parallel portion is the length of the line segment B0′-B1 ′.

  Referring to FIG. 8C, when the line segment A0-A1 has a point B0 'and no point B1', that is, (A0B0, e)> = 0, (A0B1, e)> 0, (A1B0 When ', e) <0 and (A1B0, e)> = 0, the length of the parallel portion is the length of the line segment B0′-A1.

  Similarly, when there is a point B1 ′ between the line segments A0-A1 and no point B0 ′, that is, (A0B0, e) <= 0, (A0B1, e)> 0, (A1B0 ′, e) < When 0 and (A1B0, e) <= 0, the length of the parallel portion is the length of the line segment A0-B1 ′.

  Referring to FIG. 8D, when the line segment A0-A1 and the line segment B0'-B1 'do not overlap, that is, (A0B0, e)> = 0, (A0B1, e)> 0, (A1B0' , E)> 0 and (A1B0, e)> = 0, the length of the parallel portion is zero.

  Similarly, when the line segment A0-A1 and the line segment B0′-B1 ′ do not overlap, that is, (A0B0, e) <= 0, (A0B1, e) <0, (A1B0 ′, e) <0, When A1B0, e) <= 0, the length of the parallel part is zero.

  Referring to FIG. 8E, when line segment A0-A1 is included in line segment B0′-B1 ′, that is, (A0B0, e) <= 0, (A0B1, e)> 0, (A1B0 ′ , E) <0, (A1B0, e)> = 0, the length of the parallel portion is the length of the line segment A0-A1.

  As described above, the length of the parallel portion is calculated. If this length is greater than the specified value, a parallel wiring length error occurs and it is determined that the wire cannot be connected.

  Next, an example of the PAD position change process in step STE4 in FIG. 4 will be described with reference to FIGS. 9 and 10 are flowcharts showing an example of the PAD position change process in step STE4 of FIG. 9 and 10, the positions of the other PADs are changed so that the position of the PAD pushed away by the movement of the PAD to be exchanged becomes optimum. Then, the positions of other PADs are changed so that the positions of the PADs changed at this time are optimized again. By repeating this process, only the minimum necessary PAD is repositioned. It is assumed that the PAD once positioned is not moved.

  First, the PAD position change processing unit 17 in FIG. 1 sets PAD to be exchanged as PAD_A and PAD_B as the exchange destination PAD (step STP1 in FIG. 9).

  Next, the PAD position change processing unit 17 in FIG. 1 exchanges the positions of PAD_A and PAD_B (step STP2 in FIG. 9). An example of the process of exchanging the position of the PAD will be described later with reference to FIG.

  Next, the PAD position change processing unit 17 in FIG. 1 determines whether there is a designated net and whether the PAD of the designated net is not FIX (step STP3 in FIG. 9). If the designated net is present and the PAD of the designated net is not FIX, the process of step STP5 in FIG. 9 is performed, and if not, the process of step STP4 in FIG. 9 is performed.

  In step STP4 in FIG. 9, the PAD position change processing unit 17 in FIG. 1 performs a position change process for PAD_B. An example of the PAD position changing process will be described later with reference to FIG. Then, the processes in FIGS. 9 and 10 are terminated.

  In step STP5 of FIG. 9, the PAD position change processing unit 17 of FIG. 1 determines whether or not the wire of the designated net intersects the wire of the exchanged PAD_A. If it intersects, the process of step STP6 in FIG. 9 is performed, and if not, the process of step STP7 in FIG. 10 is performed.

  In step STP6 in FIG. 9, the PAD position change processing unit 17 in FIG. 1 sets the PAD of the designated net to FIX. Then, the processes in FIGS. 9 and 10 are terminated.

  In step STP7 in FIG. 10, the PAD position change processing unit 17 in FIG. 1 acquires PADs from the unprocessed PADs in a predetermined order, and sets the acquired PAD as PAD_C. The order of acquisition is, for example, the order close to PAD_A, or the order of priority if priority is specified.

  Next, the PAD position change processing unit 17 in FIG. 1 determines whether or not the wire connecting the designated net terminal and PAD_C intersects the wire of PAD_A (step STP8 in FIG. 10). If they intersect, the process of step STP9 in FIG. 10 is performed, otherwise the process of step STP7 in FIG. 10 is performed.

  In step STP9 in FIG. 10, the PAD position change processing unit 17 in FIG. 1 connects a wire between PAD_C and the terminal of the designated net.

  Next, the PAD position change processing unit 17 in FIG. 1 determines whether or not the connection has been established in step STP9 in FIG. 10 (step STP10 in FIG. 10). If the connection is successful, the process of step STP11 in FIG. 10 is performed, and if not, the process of step STP7 in FIG. 10 is performed.

  In step STP11 in FIG. 10, the PAD position change processing unit 17 in FIG. 1 exchanges the position of the PAD_C and the PAD of the designated net. Next, the PAD of the designated net is set to FIX (step STP12 in FIG. 10).

  Next, the PAD position change processing unit 17 in FIG. 1 determines whether or not the wire of the designated net has been connected (step STP13 in FIG. 10). If the connection has been established, the PAD_B position changing process is performed (step STP14 in FIG. 10), the PAD_C position changing process is performed (step STP15 in FIG. 10), and the processes in FIGS. 9 and 10 are terminated. The position changing process in steps STP14 and STP15 in FIG. 10 is the same as the PAD position changing process in step STP4 in FIG. If the connection cannot be made, the processes in FIGS. 9 and 10 are terminated.

  As described above, as shown in the flowcharts of FIGS. 9 and 10, the PAD position changing process in step STE4 of FIG. 4 is performed.

  Next, an example of the PAD_A and PAD_B exchange process in step STP2 in FIG. 9 will be described with reference to FIG. FIG. 11 is a flowchart showing an example of the process of step STP2 of FIG.

  First, the PAD position change processing unit 17 in FIG. 1 performs a connection point change process (step STW1 in FIG. 11). Specifically, first, for the LINE connected to PAD_A, the position of PAD_B is changed to the new position of PAD_A, the connection point of PAD_A-> NET-> LINE is changed, WIRE information is present, and PORTINST is connected. If so, PAD_A-> NET-> LINE (-> WIRE) is freed. For the LINE connected to PAD_B, the connection point of PAD_B-> NET-> LINE is changed with the position of PAD_A as the new position of PAD_B.

  Next, the PAD position change processing unit 17 in FIG. 1 exchanges the electrical connection of PAD_A with PAD_B (step STW2 in FIG. 11), and exchanges the electrical connection of PAD_B with PAD_A (step STW3 in FIG. 11). ). Next, the PAD position change processing unit 17 in FIG. 1 stores that PAD_A and PAD_B have been exchanged (step STW4 in FIG. 11). Then, the process of FIG.

  Next, the PAD position changing process in step STP4 of FIG. 9 will be described with reference to FIG. FIG. 12 is a flowchart showing an example of the position change process of PAD_B in step STP4 of FIG.

  First, the PAD position change processing unit 17 in FIG. 1 performs PAD_Y that makes the wire of PAD_B the shortest if there is a PAD that can be exchanged with PAD_B (hereinafter referred to as PAD_Y) among all PADs. Then, the wire shape of PAD_B at that time is stored (step STX1 in FIG. 12).

  Next, the PAD position change processing unit 17 in FIG. 1 determines whether PAD_Y has been found (step STX2 in FIG. 12). If found, the process of step STX3 in FIG. 12 is performed, and if not, the process of step STX4 in FIG. 12 is performed.

  In step STX3 in FIG. 12, the PAD position change processing unit 17 in FIG. 1 exchanges the position of PAD_Y stored with PAD_B. Then, the process of step STX1 in FIG. 12 is performed.

  In step STX4 in FIG. 12, the PAD position change processing unit 17 in FIG. 1 determines whether or not the wire originally connected to PAD_B complies with the rule. If the rule is observed, a wire is created (step STX5 in FIG. 12), and the process in FIG. 12 is terminated. If not, a warning is given (step STX6 in FIG. 12), and the processing in FIG. 12 is terminated.

  Next, an example of the automatic rewiring process in step STM3 in FIG. 3 by the automatic rewiring processor 7 in FIG. 1 will be described with reference to FIG. FIG. 13 is a flowchart showing an example of the automatic rewiring process in step STM3 of FIG.

  First, the automatic rewiring processing unit 7 in FIG. 1 creates a wiring grid and a wiring prohibited area according to the LAYER wiring width (maximum common divisor) connected to the zone of the substrate in the control file (step STR1 in FIG. 13).

  Next, the automatic rewiring processing unit 7 in FIG. 1 performs the existing wiring deletion process and the board wiring process on the PAD that has been replaced (step STR2 in FIG. 13). Here, the existing wiring deletion process is a process of deleting a wiring figure when the NET is a board wiring. The board wiring process searches for the path of the board wiring by the maze method when the NET is the board wiring. A LINE is created by a short path, and the LINE is a NET wiring pattern.

  Next, the automatic rewiring processing unit 7 in FIG. 1 deletes the wiring grid (step STR3 in FIG. 13). Then, the process of FIG. 13 ends.

  As described above, the SiP design support apparatus 1 of FIG. 1 can change the position of the terminal of the substrate and the position of the terminal of the chip at the same time, and automatically perform the rewiring process.

  Regarding the change of the position of the terminals of the PAD and the LSI chip on the substrate, as shown in FIG. 4, not only one of them may be fixed and the other may be moved, but both may be moved automatically. That is, for example, by changing one (for example, PAD on a substrate), the other (for example, a terminal of an LSI chip) may be changed.

1 is a schematic block diagram of a SiP design support apparatus 1 according to an embodiment of the present invention. FIG. 3 is a diagram showing an example of terminal position change by the SiP design support apparatus 1 of FIG. 1, and shows a connection state between PADs 25 to 39 of the SiP substrate 21 and the chip terminals of the LSI chip 23 before and after the change. is there. It is a flowchart which shows an example of operation | movement of the SiP design assistance apparatus 1 of FIG. It is a flowchart which shows an example of the terminal position change process of step STM2 of FIG. FIG. 5 is a flowchart showing an example of a PAD exchange destination determination process in step STE3 of FIG. It is a flowchart which shows an example of the process of a check of the exchangeability of PAD_A and PAD_B of step STT4 of FIG. It is a figure for demonstrating the spacing rule used for judgment of the connection possibility of step STC3 of FIG. 6, Comprising: It is a figure which shows the bonding wire in the three-dimensional space newly created. It is a figure for demonstrating the parallel wiring length rule used for judgment of the connection possibility of step STC3 of FIG. 6, Comprising: It is a figure which shows the length of the parallel part with respect to another wire when performing wire shape calculation. It is a 1st flowchart which shows an example of the PAD position change process of step STE4 of FIG. It is a 2nd flowchart which shows an example of the PAD position change process of step STE4 of FIG. FIG. 10 is a flowchart showing an example of an exchange process of PAD_A and PAD_B in step STP2 of FIG. It is a flowchart which shows an example of the position change process of PAD_B of step STP4 of FIG. It is a flowchart which shows an example of the automatic rewiring process of step STM3 of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 SiP design support apparatus 3 Control part 5 Terminal position change process part 7 Automatic rewiring process part 9 PAD exchange destination determination process part 11 PAD position change process part 13 Chip terminal exchange destination determination process part 15 Chip terminal position change process part

Claims (10)

A semiconductor device design support apparatus for supporting a design of a semiconductor device having a substrate and a chip disposed on the substrate, wherein a terminal of the substrate and a terminal of the chip are connected by electrical wiring,
For the terminals of the substrate or the chip,
By changing the position of the terminal, when at least one of the wiring connected to the terminal intersects with at least one other wiring, examine the position of the terminal is if we can change, the if it can be modified Change the terminal position ,
A semiconductor device design support apparatus comprising terminal position changing means that does not change the position of a terminal when the wiring connected to the terminal does not intersect with another wiring by changing the position of the terminal.   2. The semiconductor device design support according to claim 1, wherein the terminal position changing unit changes the position of the terminal based on a condition relating to a length of a parallel portion of a wiring connected to the terminal whose position is to be changed and another wiring. apparatus. The terminal position changing means is
Board terminal position change processing means for changing the position of the terminal of the board;
The semiconductor device design support apparatus according to claim 1, further comprising a chip terminal position change processing unit that changes a position of a terminal of the chip.   4. The semiconductor device design according to claim 1, wherein the terminal position changing unit changes the position of the terminal based on a condition relating to a distance between a wiring connected to the terminal whose position is changed and another wiring. Support device. A terminal replacement destination determination processing means for determining a replacement destination terminal that satisfies a predetermined condition for a specified replacement target terminal;
The terminal position changing means exchanges the position of the terminal to be exchanged and the position of the exchange destination terminal determined by the terminal exchange destination decision processing means,
The semiconductor device design support apparatus according to claim 1.   6. The semiconductor device design support apparatus according to claim 1, which supports three-dimensional arrangement or wiring design. A semiconductor device design support apparatus for supporting a design of a semiconductor device having a substrate and a chip disposed on the substrate, wherein a terminal of the substrate and a terminal of the chip are connected by electrical wiring,
For the two first and second terminals of the substrate or the chip,
When the positions of the first terminal and the second terminal are exchanged, when at least one of the wirings connected to the first terminal and the second terminal intersects with at least one of the other wirings, determine whether the position of the first and the second terminal is replaceable, to swap the position of said first and said second terminal when replaceable,
When the positions of the first terminal and the second terminal are exchanged, and the wiring connected to the first terminal and the second terminal does not intersect with the other wiring, the first and second A semiconductor device design support apparatus comprising terminal position changing means that does not exchange the positions of the terminals . A semiconductor device design support method for supporting a design of a semiconductor device having a substrate and a chip disposed on the substrate, wherein a terminal of the substrate and a terminal of the chip are connected by electrical wiring,
The terminal position changing means is the terminal of the substrate or the chip,
By changing the position of the terminal, when at least one of the wiring connected to the terminal intersects with at least one other wiring, examine the position of the terminal is if we can change, the if it can be modified Change the terminal position ,
A semiconductor device design support method including a step of not changing a position of a terminal when the wiring connected to the terminal does not intersect with another wiring by changing the position of the terminal .   A program for causing a computer to execute the semiconductor device design support method according to claim 8.   A computer-readable recording medium for recording the program according to claim 9.

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