JP2001298089A - Method of designing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, when positions of block pins are determined without considering wiring led around blocks in a design of a semiconductor integrated circuit, wiring between distant blocks, which detours the blocks, is formed and thus timing violation occurs due to this long-distance wiring. SOLUTION: The center of gravity of a connection block is obtained and surrounded by a rectangular frame (rectangle forming step 102). Whether an obstacle exists in the rectangular frame is confirmed (obstacle confirming step 103). If an obstacle exists, the center of gravity of the rectangular frame and that of the obstacle are compared (center of gravity comparing step 104). Based on the result, the rectangular frame is extended (rectangle extending step 105). The block side of a connection block that is brought into contact with the rectangular frame for the first time due to extension of the rectangular frame is determined as a block pin positioning side for all blocks (positioning side determining step 106).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-scale LSI design method for dividing design data into a plurality of hierarchical blocks and performing design for each block. In particular, the present invention solves a timing problem caused by wiring between blocks. The present invention relates to a method for designing a semiconductor integrated circuit.

[0002]

2. Description of the Related Art With the recent miniaturization of processes, the development of large-scale, high-speed semiconductor integrated circuits has become active.
On the other hand, due to the influence of miniaturization, the delay caused by the wiring has become dominant over the inherent delay of the cell. Therefore, it is important to perform the design in consideration of the timing from the initial design stage.

For this reason, in the design of a large-scale data semiconductor integrated circuit, a hierarchical design in which a design is performed for each block is performed. The layout is performed for each block in which the hierarchical division has been performed, and the wiring process between cells in different blocks is performed as follows.
There is a method in which block pins for relaying wiring are provided in each block, and those block pins are connected in a top hierarchy to complete wiring.

However, in the hierarchical design, there is a problem that unless the layout design is completed for all the blocks, the wiring length of the wiring between blocks, which greatly affects the timing, cannot be known.

In order to solve this problem, a method of estimating the floor plan of the top hierarchy and estimating the wiring length between blocks in the initial stage of design, and designing each block in consideration of the wiring length has been used.

A conventional method of designing a semiconductor integrated circuit will be described with reference to FIG.

FIG. 35 is an example of a flowchart of a method of designing a semiconductor integrated circuit.
501 is a floor plan process, 3502 is a timing constraint generation process, 3503 is a logic synthesis process, 3504 is a block layout process, 3505 is a timing verification process in a block, 3506 is a top layout process, 3507 is a hierarchical timing verification process, and 3508 is a driving capability. The optimization step, 3509 indicates a cell replacement step, and END indicates the end of the processing.

Each step will be described along the flow of the method of designing a semiconductor integrated circuit.

First, a floor plan process 3501 is shown in FIG.
This will be described with reference to FIG. FIG. 36 shows a floor plan process 3501.
In the figure, 3601 is a block arrangement step, 3602 is a block pin temporary arrangement step,
Reference numeral 3603 denotes a block pin main placement step, and 3604 denotes a virtual wiring step between blocks.

In a block arranging step 3601, a block arranging position is examined in consideration of the number of connections of each functional block, a signal flow, and the like. At this time, the block area is estimated for the unlaid-out block, and the block shape and the block arrangement position are examined based on the area estimation result. After the shapes and arrangement positions of all the blocks are determined, the process proceeds to the examination of the arrangement positions of the block pins.

As a general block pin arranging method, there is a method of automatically arranging pins by using an automatic block pin arranging function which is a function of a semiconductor automatic design tool (CAD tool). An example of a case where the block pin arrangement position is determined using the automatic block pin arrangement function will be described in a block pin temporary arrangement step 3602 and a block pin main arrangement step 3603.

In the block pin provisional placement step 3602, a block side located closest to the connection destination block is searched for in each block having a connection relation, and the block side is set as a provisional block pin placement side. After the provisional side of the block pins is determined for all connection relations, the process proceeds to the block pin main placement step 3603.

In the block pin main arranging step 3603, the block pins allocated to each block side of each block are arranged so as to satisfy a predetermined rule of a pin interval. At this time, block pins are considered so as to have a horizontal or vertical positional relationship so that wiring is not bent in the virtual wiring between blocks generated in the virtual wiring between blocks 3604 in the next process. After the arrangement positions of all the block pins are determined, the process proceeds to the inter-block virtual wiring step 3604.

In an inter-block virtual wiring step 3604, block pins are connected by inter-block virtual wiring. that time,
Wiring is performed so that the wiring distance of the virtual wiring between blocks is minimized.

Here, block pin provisional placement step 360
The block pin real placement step 3603 and the inter-block virtual wiring step 3604 will be described with reference to FIG. 37 showing an example of a floor plan.

FIG. 37 shows an example of a result of determining a block pin arrangement position by using a block pin automatic arrangement function of a CAD tool. Reference numeral 3701 denotes a block arrangement area, 3702 denotes a block A, 3703 denotes a block B, 3704 denotes a block C, 3705 denotes a block D, 3
706 is a block E, 3707 is each block pin, 37
Reference numeral 08 denotes a virtual wiring between blocks connecting the respective block pins.

Block A3702 and Block D37
It is assumed that there is a connection relationship between the block pins 3707 and 3707 of FIG.
7 will be described.

First, in the block pin provisional placement step 3602, for each block having a connection relationship, a block side present at a position closest to the connection destination block is searched and set as a block pin placement side. That is, block A370
In the block side of block 2, the right side existing closest to the connection destination block D3705 is searched, and the block pin 370 is searched.
It is assumed that the arrangement side is 7. On the other hand, the left side located closest to the connection destination block A3702 is searched for in the block side of the block D3705, and is set as the arrangement side of the block pin 3707. After the arrangement side of the block pin 3707 is determined in all connection relations, the process proceeds to the block pin actual arrangement step 3603.

Next, in the block pin main arranging step 3603, the block pins 3707 determined for each block side of each block are arranged so as to satisfy a predetermined rule of a pin interval. At this time, the block pins 3707 are considered so as to have a horizontal or vertical positional relationship. After all the block pin arrangement positions are determined, the process proceeds to the inter-block virtual wiring step 3604.

In the inter-block virtual wiring step 3604, the virtual wiring 3 between the block pins 3707 and 3707 is connected.
Connect with 708. At this time, wiring is performed so that the inter-block virtual wiring 3708 becomes the shortest.

By determining the block pin arrangement position by using the block pin automatic arrangement function of the CAD tool in the method described above, the wiring distance of the inter-block virtual wiring 3708 connecting the block pins 3707, 3707 is minimized. It is general to determine the arrangement position of the block pins 3707 as described above.

After the generation of the virtual wiring between blocks, the process proceeds to a timing constraint generation step 3502.

In the timing constraint generation step 3502, a timing constraint for each functional block is generated based on the virtual wiring between blocks estimated in the floor plan step 3501.
After generating the timing constraint, the process proceeds to a logic synthesis step 3503.

In the logic synthesis step 3503, logic synthesis is performed so as to satisfy the timing constraint generated in the timing constraint generation step 3502, connection information in each block is generated, and the process proceeds to the block layout step 3504.

In the block layout step 3504, a layout is performed for each functional block based on the connection relation information generated in the logic synthesis step 3503.

At this time, a timing constraint generation step 3502
The timing-driven layout is performed using the timing constraint generated in step (1). The timing-driven layout is a function for adding a timing constraint to each path or each net, and performing cell arrangement and wiring between cells while considering the given timing constraint.

After the layout data has been generated, the flow proceeds to an intra-block timing verification step 3505. In the intra-block timing verification step 3505, it is verified whether the layout data generated in the block layout step 3504 satisfies the timing constraint. If all the timing constraints are satisfied, the block layout design is completed.
If no timing problem has occurred, the process moves to the top layout step 3506.

In the top layout step 3506, the layout data of each functional block generated in the block layout step 3504 is assembled into a top layer, and connections between blocks are made based on the connection relation information of the top layer. After the top layout is completed, the hierarchical timing verification step 3507
Move on to

In the hierarchical timing verification step 3507, comprehensive timing verification within each functional block and between blocks is performed. If all the desired timings of the entire circuit are satisfied, the design of the semiconductor integrated circuit is completed.

However, in-block timing verification step 3
When a timing problem occurs in the step 505 and the hierarchical timing verification step 3507, it is checked whether the timing constraint can be satisfied by paying attention to the path that failed to satisfy the timing constraint and partially changing the cells to enhance the driving capability of the cell.

As a result of the confirmation, if the timing constraint can be satisfied by partial cell replacement, first, the driving capacity optimization step 3508 and the block layout step 350
4. Based on the actual wiring of the layout data created in the top layout process 3506, for a path that could not satisfy the timing constraint, a cell having the same logic and capable of satisfying the timing constraint is specified, and the cell change information is specified. Generate

Next, in a cell exchange step 3509, the corresponding cells in the layout data are exchanged based on the cell change information generated in the drive capacity optimization step 3508,
Partial cell rearrangement and rewiring between cells are performed to improve timing problems.

As a result of the check, if the timing constraint cannot be satisfied by partial cell replacement, the floor plan is reviewed in the floor plan step 3501 and the timing constraint is reviewed in the timing constraint generation step 3502.

With the above configuration and design flow,
It is the flow of the conventional design method to improve all the timing problems and complete the design of the semiconductor integrated circuit.

[0035]

However, the above-mentioned conventional method for designing a semiconductor integrated circuit has the following problems.

A problem in the case where the automatic block pin arrangement function of the CAD tool is used in the floor plan process 3501 will be described with reference to FIG.

FIG. 38 is an example showing the problem of the automatic block pin arrangement function of the CAD tool. Reference numeral 3801 denotes a block arrangement area, and reference numerals 3802 to 3806 denote blocks A to.
E, 3807 denotes each block pin, 3808 denotes a virtual wiring between blocks connecting the block pins 3807, 3807, 38
09 is a block pin 38 bypassing block C3804.
10 shows the inter-block wiring connecting the blocks 07 and 3807.

Block A3802 and Block D38
It is assumed that there is a connection relationship between the block pins 3807 and 3807 of FIG. 05, and a method of determining the position of each block pin 3807 will be described.

As described in the block pin tentative placement step, in each block having a connection relation, a block side located closest to the connection destination block is searched for.
Assuming that the side of the block pin is located, the right side of the block A3802 and the left side of the block D3805 are the block pins 380.
7, 3807 are determined.

The block pins 380 determined for each block side of each block in the block pin real placement step
7, 3807 are arranged so as to satisfy a predetermined rule of a pin interval.

In the inter-block virtual wiring step, the inter-block virtual wiring 3808 connecting the arrangement positions of the block pins 3807 and 3807 is generated to be the shortest.

When the result of generating the inter-block virtual wiring is confirmed, the inter-block virtual wiring 3808 connecting the block pins 3807 and 3807 has the shortest distance between the block pins 3807 and 3807.
Although the connection between 3807 is made, if the on-block wiring of the block C3804 is prohibited in the top layout process, a long distance interblock wiring 3809 bypassing the block C3804 is generated.

However, due to the long distance wiring,
The possibility of timing violations increases. Even if a timing violation does not occur, the semiconductor design circuit includes a loss in operation speed and area.

Also, the shortest inter-block virtual wiring 3808
Also, the inter-block wiring length error occurs between the detour and the inter-block wiring 3809. Timing constraints are created based on the inter-block virtual wiring 3808, and are subjected to logic synthesis, layout, timing verification, and processes. These timing constraints change in the top layout process, and this wiring error between blocks is a cause. Therefore, there is a high possibility that a timing violation occurs.

In addition, when the timing of the timing violation occurs, if the block pin arrangement position is reviewed again in the floor plan process, the review is often performed manually from the wiring route and the block pin arrangement position for each connection unit. And the number of steps for reviewing the arrangement position of the block pins are required, and a large number of steps are required.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide an appropriate block pin arrangement method which does not generate inter-block wiring that bypasses blocks.

[0047]

SUMMARY OF THE INVENTION The present invention concerning a method of designing a semiconductor integrated circuit for solving the above-mentioned problems has been created based on the following concept.

If the block pin arrangement side is determined in the usual manner, there is a high possibility that the block pin arrangement side will be the opposite side of each block having a connection relationship. In this case, if there is an obstacle crossing the rectangular frame, the obstacle is This would be an obstacle to the connectivity area. In order to avoid long-distance wiring bypassing the block of the obstacle, it is necessary to set another block side other than the opposite side as the block pin arrangement side. The rectangular frame is extended to find a block pin arrangement side avoiding such an opposite side. It is desirable that the extension be performed rationally.

The center of gravity of the rectangular frame created from the center of gravity of each of the blocks having a connection relationship represents a connectable area between the blocks having a connection relationship. On the other hand, the center of gravity of the obstacle crossing the rectangular frame represents the degree of the influence of the obstacle on the connectable area by the obstacle. In expanding a rectangular frame for searching for a block pin arrangement side avoiding the opposite side, the expansion is preferably as small as possible. This is because the wiring length can be shortened as a result when the extension is smaller than when the extension is large. Since the rectangular frame is expanded, the obstacle is considered based on the obstacle.
The distance between the block side of the obstacle and the center of gravity of the rectangular frame in the direction in which the center of gravity of the rectangular frame exists with respect to the center of gravity of the obstacle, in other words, in the vector direction from the center of gravity of the obstacle to the center of gravity of the rectangular frame, is Is smaller than the distance between the block side of the obstacle and the center of gravity of the rectangular frame in the direction opposite to the vector direction. Therefore, the rectangular frame is extended in the vector direction from the center of gravity of the obstacle to the center of gravity of the rectangular frame.

Therefore, the block centroids of the connected blocks are determined by the rectangle generation step, a rectangular frame surrounding the block centroids is created, and the obstacle confirmation step checks whether there is an obstacle crossing the rectangular frame. If there is an obstacle, the extension direction of the rectangular frame is determined in accordance with the above logic based on a comparison between the center of gravity of the obstacle and the centroid of the rectangular frame in the centroid comparison step. Then, the rectangular frame is expanded in the expansion direction until the rectangular frame is in contact with the block side that is not the opposite side of the block having the connection relationship by the rectangular expansion step,
The block side in contact with the rectangular frame in the arrangement side determination step is set as the arrangement side of the block pin.

That is, determination of the block pin arrangement side avoiding the opposite side is rationally performed. As a result, it is not necessary to dispose the block pins on the side of the block where long-distance wiring that goes around the block occurs, and therefore, it is possible to prevent occurrence of timing violation due to long-distance wiring. In addition, it is possible to prevent a timing violation from occurring due to a wiring error between the blocks and the virtual wiring between the blocks.

In the above description, the expression “rectangular frame” is a narrow expression, and is generally referred to as a “search frame”. The search frame is a frame having as small an area as possible, surrounding the center of gravity of a plurality of blocks, and its shape is not particularly limited. Therefore, the above rectangular frame may be considered as a special form of the search frame.
In the present invention, it is not always necessary to be limited to a rectangular frame, and it can be widely interpreted as a search frame. A typical example of the shape of the search frame is a rectangle. In addition to the rectangle, a polygon having an arbitrary shape that may include a triangle and a closed curve shape approximating such a polygon are available.

Further, in the above description, the expression "center of gravity" is a narrow expression, and may be broadly referred to as "near the center of gravity". Nearby means any point within a circle of relatively small radius about the center of gravity. The radius can be arbitrarily determined, but any radius that supports the logic described above may be used.

In the above description, “obstacle” may be generally considered to be a block that becomes a hindrance to wiring, but is intended to include a case where a plurality of blocks become one obstacle. Instead of the expression "block", it describes "obstacle".

[0055]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be generally described.

The method of designing a semiconductor integrated circuit according to the first invention of the present application is a method of designing a semiconductor integrated circuit that realizes a desired function by arranging a plurality of functional blocks on a chip and connecting the functional blocks. A rectangle generation step of obtaining a block centroid of a plurality of connected blocks and creating a rectangular frame surrounding those block centroids, and an obstacle confirmation step of confirming whether there is an obstacle crossing the rectangular frame ,
A center-of-gravity comparing step of determining an extension direction of the rectangular frame from the center of gravity of the obstacle and the center of gravity of the rectangular frame; and a rectangle extension step of extending the rectangular frame in the extension direction until the rectangular frame contacts a block side of a block having a connection relationship. And an arrangement side determining step of setting a block side in contact with the rectangular frame as an arrangement side of a block pin.

The operation according to the first aspect of the invention is substantially the same as that described in the section of "Means for Solving the Problems". That is, since the determination of the side where the block pins are arranged is rationally performed, it is possible to realize the optimal short distance wiring while avoiding the long distance wiring bypassing the block of the obstacle, and to prevent the occurrence of timing violation. Becomes

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit designing method according to the first aspect, further comprising, after the arrangement side determining step, the block pins assigned to the same block pin arrangement side. Are arranged at equal intervals within the block pin arrangement side.

According to the second aspect, the intervals between adjacent block pins on the same block pin arrangement side are equalized, so that it is possible to prevent block pins from being intensively arranged beyond the limit. It becomes possible. That is, since the wiring congestion is avoided, it is possible to avoid a situation in which the wiring cannot be processed due to the wiring congestion. Therefore, it is possible to prevent the design from returning due to the change in the arrangement of the block pins, and to efficiently design the semiconductor integrated circuit. Further, it is possible to prevent an increase in the wiring length and an increase in the chip size due to the fact that the wiring does not pass through the congested portion due to the route. It is to be noted that the effect of realizing the optimal short-distance wiring in a state where the long-distance wiring due to the detour of the obstacle block according to the first invention is avoided and suppressing the occurrence of timing violation is exhibited. Needless to say.

In a third aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the first aspect of the present invention, further, after the placement side determining step, the arrangement positions of the block pins allocated to the same block pin placement side. And a designated arrangement step of arranging the block pins in accordance with the pin arrangement positions designated in the arrangement position designation step.

According to the third aspect of the present invention, it is possible to arrange a block pin at an arbitrary position on a block pin arrangement side, so that wiring can be performed in a bus net or the like with a uniform wiring length. It is easy to realize a desired wiring in a state where the difference in wiring length and the occurrence of errors are suppressed. In addition, according to the first aspect,
Needless to say, an effect of realizing optimal short-distance wiring while avoiding long-distance wiring due to detour of an obstacle block and suppressing occurrence of timing violation is exhibited.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit designing method according to the first aspect, further comprising a timing constraint list generating step of reading a timing constraint, and further comprising the step of: With priority given to the block pins with strict timing constraints read in the constraint list generation step, block pins with more strict timing constraints are arranged in order from the side closer to the center of gravity of the rectangular frame within the block pin arrangement side determined in the arrangement side determination step. It is characterized by including a timing constraint order placement step.

As the timing constraint, a wiring constraint such as a wiring length and a wiring capacitance determined for each inter-block wiring can be given as a typical example.

According to the fourth aspect of the present invention, the block pin having a stricter timing constraint is prioritized and arranged on the side closer to the center of gravity of the rectangular frame, that is, on the side closer to the counterpart block having the connection relationship. The arrangement position of the block pins can be determined so that the wiring length is shortened in the strict order, and the occurrence of a timing violation that greatly deviates from the timing constraint is suppressed, so that it is possible to reduce the processing for improving the timing violation. . It is to be noted that the effect of realizing the optimal short-distance wiring in a state where the long-distance wiring due to the detour of the obstacle block according to the first invention is avoided and suppressing the occurrence of timing violation is exhibited. Needless to say.

In a fifth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the first aspect of the present invention, there is further provided a temporary wiring length calculating step of temporarily arranging a block pin at the center of a block and calculating a temporary wiring length between blocks. A virtual timing verification step of performing a delay calculation based on the inter-block wiring length to verify whether or not the timing constraint is satisfied, and assigning a strict order of satisfying the timing constraint based on the result of the timing verification. And a verification result list generating step of generating the verification result list, and after the placement side determining step, in a strict order of satisfying the timing constraint indicated by the verification result list generated in the verification result list generating step. By giving priority to the stricter block pins, the rectangular frame center of gravity is set within the block pin arrangement side determined in the arrangement side determination step. Is characterized in that it comprises a continue sequentially arranged stricter block pin that order from the stomach side timing order placement process.

According to the fifth aspect of the invention, priority is given to a stricter block pin in the order of strictness of satisfying the timing constraint (timing verification result), and the side closer to the center of gravity of the rectangular frame, that is, the partner side having the connection relationship Since the block pins are arranged closer to the block, it is possible to determine the arrangement position of the block pins so that the wiring length becomes shorter in the order of the strictness of meeting the timing constraint (timing verification result), and the timing violation Can be suppressed. It is to be noted that the effect of realizing the optimal short-distance wiring in a state where the long-distance wiring due to the detour of the obstacle block according to the first invention is avoided and suppressing the occurrence of timing violation is exhibited. Needless to say.

The method for designing a semiconductor integrated circuit according to a sixth aspect of the present invention is the semiconductor integrated circuit design method according to the first aspect, further comprising, after the arrangement side determining step, all of the block pins arranged on the same block pin arrangement side. And an arrangement adjustment step of adjusting the arrangement of an excess block pin that cannot be arranged on the block pin arrangement side on a block side adjacent to the block pin arrangement side. And

According to the sixth aspect, when an overflow occurs in which all the corresponding block pins cannot be arranged on the determined block pin arrangement side, the overflowed block pins are arranged on the adjacent block side. Therefore, it is possible to avoid a design return due to an overflow, and to prevent an increase in the design period. It is to be noted that the effect of realizing the optimal short-distance wiring in a state where the long-distance wiring due to the detour of the obstacle block according to the first invention is avoided and suppressing the occurrence of timing violation is exhibited. Needless to say. The method of designing a semiconductor integrated circuit according to the seventh invention of the present application is the method of the first aspect.
In the invention, further, after the arrangement side determining step,
The method further comprises a block side center arranging step of arranging the block pins arranged on the same block pin arrangement side at the center of the block pin arrangement side.

According to the seventh aspect, since the block pins are arranged at the center of the side where the block pins are arranged, the timing constraint generated based on the result of connecting the block pins with the virtual wiring between the blocks becomes an average. As a result, even if the block pin arrangement position determined by the layout process becomes a pessimistic pin position or an optimistic pin position with respect to the estimation, the timing is such that the constraint is average, so that the timing constraint largely deviates from the timing constraint. Violations are less likely to occur. Further, even if a timing violation occurs, the timing constraint is not greatly deviated, so that the processing for improving the timing violation is reduced. It is to be noted that the effect of realizing the optimal short-distance wiring in a state where the long-distance wiring due to the detour of the obstacle block according to the first invention is avoided and suppressing the occurrence of timing violation is exhibited. Needless to say.

The method for designing a semiconductor integrated circuit according to an eighth aspect of the present invention is the semiconductor integrated circuit design method according to the first aspect, further comprising, after the arrangement side determining step, the block pins arranged on the block pin arrangement side being replaced by the block pins. It is characterized by including a pessimistic position arranging step of arranging the pin at the farthest position from the center of gravity of the rectangular frame on the side where the pins are arranged.

According to the eighth aspect, since the block pins are arranged farthest from the center of gravity of the rectangular frame on the side where the block pins are arranged, the timing constraint generated based on the result of connecting the block pins by virtual wiring between blocks is restricted. It is the most severe pessimism, and as a result, the block pin arrangement position determined by the layout process does not become a more pessimistic pin position than estimated, and the situation that timing constraints can not be satisfied does not occur, so timing Violation can be avoided. It is to be noted that the effect of realizing the optimal short-distance wiring in a state where the long-distance wiring due to the detour of the obstacle block according to the first invention is avoided and suppressing the occurrence of timing violation is exhibited. Needless to say.

In a ninth aspect of the present invention, in the method for designing a semiconductor integrated circuit according to the first aspect of the present invention, further, a connection determining step of determining whether a block side contacted by the rectangular frame is a connected block is provided. When it is determined that there is a connection, the arrangement side determining step of setting the block side in contact with the rectangular frame as the arrangement side of the block pin, a wiring area confirmation step of calculating the number of wires that can pass through the wiring area, It is characterized by including a wiring prohibited area generation step of providing a wiring prohibited area in an impossible wiring area.

According to the ninth aspect of the present invention, since the block pins are not arranged so as to exceed the passing capacity of the wiring in the wiring area, it is possible to avoid a situation in which the wiring cannot be passed due to a shortage of capacity in the wiring area. Becomes if,
If the wiring cannot pass through, the wiring wraps around through another wiring path. By avoiding this wraparound, it is possible to suppress the timing violation. It is to be noted that the effect of realizing the optimal short-distance wiring in a state where the long-distance wiring due to the detour of the obstacle block according to the first invention is avoided and suppressing the occurrence of timing violation is exhibited. Needless to say.

In the above description, an embodiment in which “rectangular frame” is replaced with “measures frame” and an embodiment in which “center of gravity” is replaced with “near the center of gravity” are also used. Of course it is possible.

(Specific Embodiment) Hereinafter, a specific embodiment of a method for designing a semiconductor integrated circuit according to the present invention will be described in detail with reference to the drawings.

(Embodiment 1) Embodiment 1 of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a flowchart of a process performed in a floor plan step of the method of designing a semiconductor integrated circuit according to the first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a block arrangement step, 102 denotes a rectangle generation step,
103 is an obstacle confirmation step, 104 is a center of gravity comparison step, 10
5 is a rectangle expansion step, 106 is an arrangement side determination step, 107 is a block pin arrangement position determination step, 108 is an inter-block virtual wiring step, and 109 is a conventional pin arrangement step. In this flow, the block pin arrangement side is determined when the layout is performed in the top-down design.

First, in the block arranging step 101, a block arranging position of each functional block is examined. At this time, the block shape and the block arrangement position are determined from the block area estimation result also for the unlaid-out block. After determining the shapes and arrangement positions of all the blocks, the process proceeds to the rectangle generation step 102.

The rectangle generating step 102 will be described with reference to FIG. 2 showing an example of a floor plan. FIG. 2 shows that the center of gravity of a block having a connection relationship is surrounded by a rectangular frame. Reference numeral 201 denotes a block arrangement area, 202 denotes a block A, 203 denotes a block B, 204 denotes a block C, and
05 denotes a block D, 206 denotes a block E, 207 denotes a center of gravity of the blocks A and D, and 208 denotes a rectangular frame.

In the rectangle generation step 102, the block centroids 207 of all the blocks having a connection relation are obtained. As a method of obtaining the block centroid 207, the barycentric coordinates of the block can be obtained by adding each half of the vertical size and the horizontal size of each block to the lower left coordinates of the current block arrangement position. Hereinafter, block A202 and block D
Assuming that there is a connection relationship with the block 205, a method for determining two types of block pin arrangement sides will be described.

All the block centroids 207 having a connection relationship
, A rectangular frame 208 of the minimum size is generated. In FIG. 2, a rectangular frame 208 surrounding the respective block centroids 207 and 207 of the block A 202 and the block D 205 is created. After the generation of the rectangular frame 208, the obstacle confirmation step 10
Move to 3.

In the obstacle confirmation step 103, the rectangular frame 208
Check that there are no obstacles crossing the road vertically or horizontally. As a confirmation method, the lower left coordinate of the block arrangement area 201 is set to the origin (0, 0), the X axis is set to the right, the Y axis is set to the upper side, and the lower left coordinate of the rectangular frame 208 is set to (X1, Y
1) The upper right coordinate is defined as (X2, Y2). Next, the lower left coordinate of the first block is defined as (x1, y1) and the upper right coordinate is defined as (x2, y2), and it is determined whether one of the following two obstacle confirmation conditional expressions is satisfied. . If either one of the blocks is satisfied, the block is an obstacle to the rectangular frame 208.

X 1 <x 1, X 2> x 2, Y 1> y 1, Y 2 <y 2 X 1> x 1, X 2 <x 2, Y 1 <y 1, Y 2> y 2 Here, the upper obstacle confirmation conditional expression is as shown in FIG. This corresponds to the case where the block 204 crossing the rectangular frame 208 up and down becomes an obstacle, and the lower obstacle confirmation conditional expression is a block 703 crossing the rectangular frame 709 left and right as shown in FIG.
Corresponds to the case where is an obstacle.

This check is performed for all blocks.
Check whether there is an obstacle crossing the rectangular frame. As a result of the confirmation, when there is an obstacle crossing the rectangular frame, the process proceeds to the center of gravity comparing step 104 of the next step. On the other hand, when there is no obstacle crossing the rectangular frame, the process proceeds to the conventional pin arrangement step 109.

The obstacle confirmation step 103 will be described using an example of a floor plan shown in FIG. In FIG. 2, the rectangular frame 2
In contrast to block 08, block C204 corresponds to the obstacle confirmation condition expression, and thus block C204 is an obstacle. Therefore, the process proceeds to the center-of-gravity comparing step 104.

In the example of the floor plan, the next step is the center-of-gravity comparing step 104. The conventional pin arrangement step 109, which is the next step when there is no obstacle, will be described here.

In the conventional pin arrangement step 109, the arrangement position of the block pins is determined by using the block pin arrangement method described in the section of [Prior Art].

In each block having a connection relation, a block side located closest to the connection destination block is searched to determine a block pin arrangement side. After the block side is determined, the block pin arrangement position is determined so as to satisfy a predetermined rule of the pin interval.

When determining the block pin arrangement position,
The pin position is determined in consideration of the horizontal or vertical positional relationship between the block pins as much as possible so that the wiring is not bent. After the block pin arrangement position is determined, the process returns to the rectangle generation step 102 in order to end the processing for this connection relation and start the processing for another connection relation.

In the center-of-gravity comparing step 104, the rectangular extension step 1
At 05, the direction in which the rectangular frame is expanded is determined to be one of four directions, up, down, left, and right.

A method for determining the extension direction will be described with reference to FIG.

FIG. 3 shows a flowchart of the center-of-gravity comparing step 104, that is, a flowchart for determining the extension direction. Reference numeral 301 denotes a rectangular frame / obstacle center-of-gravity calculating step; 302, a direction determining step; The decision step 304 is a left / right decision step.

First, a rectangular frame / obstacle center of gravity calculation step 301
Is used to determine the center of gravity of the rectangular frame and the center of gravity of the obstacle. As a method for obtaining the same, the center coordinates of the rectangular frame are obtained based on the vertical size and the horizontal size of the rectangular frame, similarly to the method for obtaining the block center of gravity. Also at the center of gravity of the obstacle, the center coordinates of the obstacle are obtained based on the vertical size and the horizontal size of the obstacle confirmed in the obstacle confirmation process.

Next, in the direction determining step 302, it is determined whether the extension direction is to be determined vertically or horizontally.
As a determination method, in the obstacle confirmation step 103, the direction in which the obstacle crosses the rectangular frame is set. In other words, if there is an obstacle that crosses the rectangular frame up and down,
Move to 3. If there is an obstacle that crosses the rectangular frame from side to side,
Move to the left / right determination step 304.

In the up / down determination step 303, the two types of center of gravity obtained in the rectangular frame / obstacle center of gravity calculation step 301 are compared, and the extension direction is determined to be upward or downward. As a determination method, a direction in which the rectangular frame centroid exists with respect to the obstacle centroid is set. That is, the coordinates of the center of gravity of the obstacle are (X _G , Y _G )
And the coordinates of the center of gravity of the rectangular frame are defined as (x _G , y _G ), and if Y _G <y _G holds, the upward direction is defined as the extension direction. If Y _G > y _G holds, the downward direction is defined as the extension direction.

After the extension direction is determined in the up / down determination step 303, the process proceeds to the rectangle extension step 105.

On the other hand, in the left / right determination step 304, a rectangular frame
The two types of centroids obtained in the obstacle centroid calculation step 301 are compared, and the extension direction is determined to the left or right. As a determination method, a direction in which the rectangular frame centroid exists with respect to the obstacle centroid is set. That is, when X _G > x _G holds, the left direction is set as the extension direction. When X _G <x _G holds, the right direction is set as the extension direction.

However, in the above comparison, Y _G = y _G
And when a, when it becomes an X _G = x _G performs the following processing. Regarding the congestion of the wiring, it is considered that the closer to the outside between the inside and the outside of the chip, the less the influence on the wiring congestion. Therefore, the center of gravity of the chip (Xc,
Yc) is obtained and compared with the center of gravity (X _G , Y _G ) of the obstacle or the center of gravity (x _G , y _G ) of the rectangular frame.

[0099] When the obstacle is across the rectangular frame in the vertical, if Yc <Y _G, the upward and extended direction. If Yc> Y _G , the downward direction is the extension direction. Further, if the obstacle is across the rectangular frame in the left and right, if Xc <X _G, the right direction and extended direction. Also, if Xc> X _G, the left and extended direction.

Further, if Yc = Y _G or Xc = X
_G may occur. For this, the extension direction is determined in advance in any direction, and the extension direction is followed. For example, it defined as the upward direction when the Xc = X _G, when the Xc = X _G and so on define the right direction.

After the extension direction is determined in the left / right determination step 304, the process proceeds to the rectangle extension step 105.

The center-of-gravity comparing step 104 will be described with reference to an example of a floor plan shown in FIG. FIG. 4 shows a rectangular frame centroid and an obstacle centroid of an example floor plan. Reference numerals 201 to 208 are as described above, and as a new element, reference numeral 209 represents a rectangular frame centroid.
Reference numeral 10 denotes the center of gravity of the obstacle.

First, a rectangular frame / obstacle center of gravity calculation step 301
, The center of gravity 209 of the rectangular frame is obtained based on the vertical and horizontal sizes of the rectangular frame 208. The coordinates are (x _G , y _G ). Next, an obstacle center of gravity 210 is obtained based on the vertical and horizontal sizes of the block C204 which is an obstacle block. The coordinates are (X _G , Y _G )
It is. Then, the process proceeds to the direction determining step 302.

In the direction determining step 302, the direction in which the obstacle block crosses the rectangular frame in the obstacle checking step 103 is checked. In the case of this floor plan, the block C204 that crosses the rectangular frame 208 up and down becomes an obstacle.

In the up / down determination step 303, two types of centroids are compared to determine the extension direction. In this floor plan, since the rectangular frame centroid 209 is located above the obstacle centroid 210, the extension direction is set to the upward direction. Is determined. After the extension direction is determined, the process proceeds to the rectangle extension step 105.

In the rectangular extension step 105, the center of gravity comparison step 1
The rectangular frame is extended in the extension direction determined in 04.
When performing the extension, the extension is performed up to the block side corresponding to the following two conditions.

The first condition is that there is a connection side and the block side was not in contact before expansion.

The second condition is that a block side exists in the direction in which an obstacle crosses the rectangular frame.

Specifically, when an obstacle crosses the rectangular frame up and down, the upper and lower sides are set, and when an obstacle crosses the rectangular frame left and right, the left and right sides are set. The expansion is performed until the rectangular frame contacts the block side corresponding to the above two conditions for the first time.

The rectangle expanding step 105 will be described with reference to an example of a floor plan shown in FIG. FIG. 5 shows the rectangular frame after the rectangular frame expansion. Center of gravity comparison step 104
In the extension direction, ie, the upward direction determined in
08 is extended until the upper side of the expanding rectangular frame 208 first contacts the upper and lower sides of the block having a connection relationship and which were not in contact before the expansion. After the extension, the process proceeds to the placement side determination step 106.

In the following, a description will be given assuming that the side contacting the rectangular frame 208 for the first time is the upper side of the block A202 by expanding the rectangular frame 208.

In the arrangement side determination step 106, the side of the connection-related block for the first time in contact with the rectangular frame obtained from the rectangular frame expansion result of the rectangle expansion step 105 is determined for each of the connection-related blocks. It is determined as the pin arrangement side.

The arrangement side determining step 106 will be described with reference to an example of a floor plan shown in FIG. FIG. 6 shows the block side determined as the block pin arrangement side. As a new element, reference numeral 211 indicates a block pin arrangement side.

On the basis of the result obtained from the rectangular frame expansion in the rectangular expansion step 105, the block pin arrangement side 211 of the current target net connected by the block A202 and the block D205, which are connected, has the upper side of the block A202 and the block A202. The upper side of D205 is determined.

After the determination of the block pin arrangement side of the target net, the processing of the target net is completed, and the process shifts to the processing of other nets in the same manner. The block pin arrangement positions or the block pin arrangement sides of all the nets are determined. Until the process, the steps from the rectangle generation step 102 to the placement side determination step 106 or the conventional pin placement step 109 are repeated. After the block pin placement sides have been determined for all nets, the process proceeds to the block pin placement position determination step 107.

In the block pin arrangement position determining step 107, the block pin arrangement position is determined within the block side determined in the arrangement side determining step 106. At this time, the pin position is determined so as to satisfy a predetermined rule of the pin interval. After all the block pin arrangement positions are determined, the process proceeds to the inter-block virtual wiring step 108.

In the inter-block virtual wiring step 108, based on the block pin arrangement positions determined in the block pin arrangement position determining step 107, an inter-block virtual wiring connecting the block pins with the shortest distance is generated. After that, the floor plan process is completed, and the processes after the timing constraint generation process are performed as before, to design the semiconductor integrated circuit.

Next, an explanation will be given using another example different from the floor plan used above.

After determining the shapes and arrangement positions of all the blocks in the block arrangement step 101, the rectangle generation step 1
Move to 02. The rectangle generation step 102 will be described with reference to an example of a floor plan shown in FIG.

FIG. 7 shows that the center of gravity of a block having a connection relation is surrounded by a rectangular frame. Reference numeral 701 denotes a block arrangement area, and reference numerals 702 to 707 denote blocks A, respectively.
F, 708 indicate the respective centers of gravity of the blocks A 702, B 703, and C 704, and 709 indicates a rectangular frame.

In the rectangle generation step 102, the block center of gravity 7 is determined based on the vertical and horizontal sizes of the respective blocks having a connection relationship.
08. Hereinafter, block A702, block B7
03, there is a connection relationship with the block C704,
A method for determining a block pin arrangement side will be described.

All the block centroids 708 having a connection relation
, A rectangular frame 709 of the minimum size is generated. In FIG. 7, block A 702, block B 703, block C
A rectangular frame 709 surrounding each block center of gravity 708. After the generation of the rectangular frame 709, the process proceeds to the obstacle confirmation step 103.

In the obstacle confirmation step 103 for confirming whether there is an obstacle crossing the rectangular frame 709 in the vertical or horizontal direction using the previously described obstacle confirmation conditional expression, the rectangular frame 7
Since block B703 corresponds to the obstacle confirmation conditional expression for block 09, block B703 becomes an obstacle. Therefore,
Move to the center of gravity comparison step 104.

The center-of-gravity comparing step 104 will be described with reference to the flowchart of FIG. 3 while referring to an example of a floor plan shown in FIG. FIG. 8 shows a rectangular frame center of gravity and an obstacle center of gravity of an example floor plan.
09 is as described above, and as new elements, reference numeral 710 indicates a rectangular frame center of gravity, and 711 indicates an obstacle center of gravity.

First, a rectangular frame / obstacle center of gravity calculation step 301
A rectangular frame center of gravity 710 is obtained based on the vertical and horizontal sizes of the rectangular frame 709. The coordinates are (x _G , y _G ). Next, an obstacle center of gravity 710 is obtained based on the vertical and horizontal sizes of the block B703 which is an obstacle block. The coordinates are (X _G , Y _G )
It is. Then, the process proceeds to the direction determining step 302.

In the direction determining step 302, the direction in which the obstacle block crosses the rectangular frame in the obstacle checking step 103 is checked. In the case of this floor plan, since the block B703 that crosses the rectangular frame 709 left and right becomes an obstacle, the process proceeds to the left / right determination step 304.

In the left / right determination step 304, two types of centroids are compared to determine the extension direction. However, in this floor plan, the rectangular frame centroid 710 is located leftward with respect to the obstacle centroid 711. Is determined. After the extension direction is determined, the process proceeds to the rectangle extension step 105.

The rectangle expanding step 105 will be described with reference to an example of a floor plan shown in FIG. FIG. 9 shows the rectangular frame after the rectangular frame has been expanded.
The rectangular frame 7 extends in the extension direction determined in
09 is extended. When performing the extension, the extension is performed up to the block side corresponding to the two conditions described above. Hereinafter, the rectangular frame 7
As a result of the extension of 09, the sides that first contact the rectangular frame 709 are the blocks A702, B703, and C704.
The description is made assuming that the left sides are simultaneously touched. After the extension, the process proceeds to the placement side determination step 106.

The placement side determination step 106 will be described with reference to an example of a floor plan shown in FIG. FIG. 10 shows a block side determined as a block pin arrangement side. As a new element, reference numeral 712 indicates a block pin arrangement side.

Based on the result obtained from the rectangular frame expansion in the rectangular expansion step 105, the block pin arrangement sides 712 of the current target net connected by the blocks A 702, B 703, and C 704 having a connection relationship are the block A
702, block B 703, and block C 704.

Next, a description will be given using still another example of the floor plan used above.

After the shapes and arrangement positions of all blocks are determined in the block arrangement step 101, the rectangle generation step 1
Move to 02. The rectangle generation step 102 will be described with reference to an example of a floor plan shown in FIG.

FIG. 11 shows that the center of gravity of a block having a connection relation is surrounded by a rectangular frame.
Is a block arrangement area, 1102 to 1107 are block A
F, 1108 are the block C1104 and the block E
The center of gravity 1109 of each 1106 indicates a rectangular frame.

As in the example of the floor plan described above,
A block center of gravity 1108 is obtained based on the vertical and horizontal sizes of each block having a connection relationship. Hereinafter, block C11
Assuming that there is a connection relationship between the block pin 04 and the block E1106, a method of determining a block pin arrangement side will be described.

[0135] All the block centroids 110 in connection relation
A minimum-size rectangular frame 1109 surrounding 8,1108 is generated. In FIG. 11, block C1104, block E1
A rectangular frame 1109 surrounding the respective block centroids 1108, 1108 of 106 is created. After the generation of the rectangular frame 1109, the process proceeds to the obstacle confirmation step 103.

In the obstacle confirmation step 103 for confirming whether there is an obstacle crossing the rectangular frame 1109 vertically or horizontally using the obstacle confirmation conditional expression described above,
In the example of the floor plan in FIG. 11, there is no block corresponding to the obstacle confirmation conditional expression for the rectangular frame 1109, and thus there is no obstacle. Therefore, the conventional pin arrangement process 1
Move to 09.

In the conventional pin arrangement step 109, the arrangement position of the block pins is determined by using the block pin arrangement method described in the section of [Prior Art].

In each of the blocks having a connection relationship, a block side present at a position closest to the connection destination block is searched to determine a block pin arrangement side. After the block pin arrangement side is determined, the block pin arrangement position is determined so as to satisfy a predetermined rule of the pin interval.

When deciding the block pin arrangement position,
The pin position is determined in consideration of the horizontal or vertical positional relationship between the block pins as much as possible so that the wiring is not bent. After the block pin arrangement position is determined, the process returns to the rectangle generation step 102 in order to end the processing for this connection relation and start the processing for another connection relation.

The conventional pin arrangement step 109 will be described with reference to an example of a floor plan shown in FIG. FIG. 12 shows the block pin arrangement positions determined by the conventional method. Reference numerals 1101 to 1109 are as described above. As a new element, reference numeral 1110 indicates the block pin arrangement positions. I have.

First, the block side existing closest to the block E1106 to which the block C1104 is connected is searched for as the right side of the block C1104, and the block C1104 is searched for.
The right side of 4 is determined as the arrangement side of the block pin. The block side of the block E1106 is connected to the block C of the connection destination.
Block E1106 located closest to 1104
Is searched for and determined as the arrangement side of the block pin.

Next, taking into account the positional relationship between the block pin arrangement sides of the block C1104 and the block E1106,
The block pin arrangement position 1110 is determined so that the block pins have a horizontal or vertical positional relationship as much as possible so that the wiring is not bent.

After the determination of the block pin placement side of the target net, the processing of the target net is completed, and the process shifts to the processing of other nets in the same manner. The block pin placement positions or the block pin placement sides of all the nets are determined. Until the process, the steps from the rectangle generation step 102 to the placement side determination step 106 or the conventional pin placement step 109 are repeated. After the block pin placement sides have been determined for all nets, the process proceeds to the block pin placement position determination step 107.

In the block pin arrangement position determination step 107, the block pin arrangement position is determined within the block side determined in the arrangement determination step 106. At this time, the block pin arrangement position is determined so as to satisfy a predetermined rule of the pin interval. After all the block pin arrangement positions are determined, the process proceeds to the inter-block virtual wiring step 108.

In the inter-block virtual wiring step 108, based on the block pin arrangement position determined in the block pin arrangement position determining step 107, an inter-block virtual wiring connecting the block pins with the shortest distance is generated. After that, the floor plan process is completed, and the processes after the timing constraint generation process are performed as before, to design the semiconductor integrated circuit.

Next, an explanation will be given using another example different from the floor plan used above.

After determining the shapes and arrangement positions of all the blocks in the block arrangement step 101, the rectangle generation step 1
Move to 02. The rectangle generation step 102 will be described with reference to an example of a floor plan shown in FIG.

FIG. 13 shows that the center of gravity of a block having a connection relation is surrounded by a rectangular frame.
Denotes a block arrangement area, 1302 to 1307 denote blocks A to F, 1308 denotes a center of gravity of each of the block B 1303 and the block F 1308, and 1309 denotes a rectangular frame.

As in the case of the floor plan described above,
The block centroids 1308, 1308 are obtained based on the vertical and horizontal sizes of the respective blocks having a connection relationship. Hereinafter, it is assumed that there is a connection relationship between the block B1303 and the block F1307, and a method of determining a block pin arrangement side will be described.

All the block centroids 130 having connection relations
A rectangular frame 1309 of the minimum size that surrounds 8,1308 is generated. In FIG. 13, respective block centroids 1308 and 130 of the block B1303 and the block F1307 are shown.
A rectangular frame 1309 surrounding 8 is created. After the generation of the rectangular frame 1309, the process proceeds to the obstacle confirmation step 103.

In the obstacle checking step 103 for checking whether there is an obstacle crossing the rectangular frame 1309 vertically or horizontally using the obstacle checking conditional expression described above, the obstacle checking conditional expression for the rectangular frame 1309 is used. Since there is no corresponding block, there is no obstacle in the example of the floor plan in FIG. Therefore, the process proceeds to the conventional pin arrangement step 109.

In the conventional pin arrangement step 109, the arrangement position of the block pins is determined by using the block pin arrangement method described in the section of "Prior Art".

The conventional pin placement step 109 will be described with reference to an example of a floor plan shown in FIG. FIG. 14 shows the block pin arrangement positions determined by the conventional method. Reference numerals 1301 to 1309 are as described above, and as a new element, reference numeral 1310 indicates the block pin arrangement positions. I have.

First, the block side existing closest to the block F1307 to which the block B1303 is connected is searched for as the right side of the block B1303.
3 is determined as the arrangement side of the block pin. Also, on the block side of the block F1307, the connection destination block B
Block F1307 existing closest to 1303
Is searched for and determined as the arrangement side of the block pin.

Next, in consideration of the positional relationship between the block pin arrangement sides of the block B1303 and the block F1307,
The block pin arrangement position 1310 is determined so that the block pins have a horizontal or vertical positional relationship as much as possible so that the wiring is not bent.

After the determination of the block pin arrangement side of the target net, the processing of the target net is completed, and the process shifts to the processing of other nets in the same manner. The block pin arrangement positions or the block pin arrangement sides of all the nets are determined. Until the process, the steps from the rectangle generation step 102 to the placement side determination step 106 or the conventional pin placement step 109 are repeated. After the block pin placement sides have been determined for all nets, the process proceeds to the block pin placement position determination step 107.

In the block pin arrangement position determining step 107, the block pin arrangement position is determined within the block side determined in the arrangement determining step 106. At this time, the pin position is determined so as to satisfy a predetermined rule of the pin interval. After all the block pin arrangement positions are determined, the process proceeds to the inter-block virtual wiring step 108.

In the inter-block virtual wiring step 108, based on the block pin arrangement position determined in the block pin arrangement position determining step 107, an inter-block virtual wiring connecting the block pins with the shortest distance is generated. After that, the floor plan process is completed, and the processes after the timing constraint generation process are performed as before, to design the semiconductor integrated circuit.

According to the semiconductor integrated circuit design method (block pin placement side determination method) of the first embodiment configured as described above, the block pins are placed on the block sides where wiring that goes around the block occurs. Since no long-distance inter-block wiring is generated, it is possible to prevent occurrence of timing violation caused by long-distance wiring. Further, it is possible to prevent a timing violation from occurring due to a wiring error between the virtual wiring between blocks and the wiring between blocks.

(Embodiment 2) Embodiment 2 of the present invention will be described with reference to the drawings.

FIG. 15 is a diagram showing a flowchart of a process performed in a floor plan process of the method of designing a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG.
Reference numerals 1501 are block arrangement steps, 1502 is a rectangle generation step, 1503 is an obstacle confirmation step, 1504 is a center of gravity comparison step, 1505 is a rectangle expansion step, 1506 is an arrangement side determination step, 1507 is a uniform arrangement step, and 1508 is an inter-block area. A virtual wiring step 1509 is a conventional pin arrangement step.

Steps from block arrangement step 1501 to arrangement side determination step 1506 are the same as those described in the first embodiment. Hereinafter, the equal arrangement step 1507 and subsequent steps will be described. After determining the block pin arrangement side in the arrangement side determination step 1506, the process returns to the rectangle generation step 1502 to determine the block pin arrangement sides of all other nets. After the block pin arrangement sides of all nets are determined, the process proceeds to the equal arrangement step 1507.

In the equal arrangement step 1507, the block pins allocated to the block pin arrangement sides of each block determined in the arrangement side determining step 1506 are arranged at equal intervals on the block pin arrangement sides.

The uniform arrangement step 1507 will be described with reference to FIG. FIG. 16 shows a block in which block pins are arranged at equal intervals. Reference numeral 1601 denotes a block frame.
Reference numeral 1602 denotes a block pin.

Although the block pins 1602 are arranged at equal intervals, the arrangement positions of the block pins are calculated using the following example method.

On the basis of information on the block side length L of the target block side and the number n of the allocated block pins, the interval between the block pins can be obtained by the following equation.

L / (n + 1) “1” of (n + 1) in the above equation is obtained by dividing the block side length by the number of block pins without adding this “1”. For example, if a block pin is placed in a lower left corner for calculation, the wiring process may not operate properly due to restrictions of the CAD tool. Therefore, in order to execute the wiring processing normally, the calculation is performed by adding “1” to the number n of the block pins. In other words, when n block pins are arranged at equal intervals, the division number of the block side is (n + 1)
Because it becomes. In the example of FIG. 16, on the left side, n = 1, so that it is bisected, on the right side, it is n = 2, so it is divided into three, on the upper side, it is n = 3, and it is divided into four, and on the lower side, n =
Since it is 4, it is divided into 5 equal parts.

First, based on the pin intervals determined for each block side from the above equation, the first block pins are arranged at the pin intervals determined from the block edge. After that, the block pins are arranged on the block frame 1601 at the pin intervals determined above from the already arranged block pins. If the rule of the distance between the pins arranged in the conventional pin arrangement step 1509 cannot be satisfied, the arrangement is performed while adjusting the arrangement position so as to satisfy the rule.

Using the above method, block pins are arranged at equal intervals on all block pin arrangement sides of all blocks. After that, the inter-block virtual wiring step 1508 (floor plan step) is completed, and the semiconductor integrated circuit is designed as in the related art.

According to the semiconductor integrated circuit design method (block pin arrangement position determining method) of the second embodiment thus configured, the distance between adjacent block pins on the same block pin arrangement side is equalized. In addition, it is possible to avoid wiring congestion caused by intensive arrangement of block pins beyond the limit. Therefore, it is possible to avoid a situation in which wiring processing cannot be performed due to wiring congestion. As a result, it is possible to prevent the design from returning due to the change in the arrangement of the block pins, and to efficiently design the semiconductor integrated circuit. Further, it is possible to prevent an increase in the wiring length and an increase in the chip size due to the fact that the wiring does not pass through the congested portion due to the route.

[0171] Of course, as in the first embodiment, since long-distance inter-block wiring does not occur around the block, timing violations caused by long-distance wiring, virtual inter-block wiring and inter-block It is possible to prevent a timing violation from occurring due to a wiring error of the wiring.

(Embodiment 3) Embodiment 3 of the present invention will be described with reference to the drawings.

FIG. 17 is a flowchart showing the processing performed in the floor plan process of the method for designing a semiconductor integrated circuit according to the third embodiment of the present invention. In FIG.
Reference numeral 1701 denotes a block arrangement step, 1702 denotes a rectangle generation step, 1703 denotes an obstacle confirmation step, 1704 denotes a center of gravity comparison step, 1705 denotes a rectangle expansion step, 1706 denotes an arrangement side determination step, 1707 denotes an arrangement position designation step, and 1708 denotes designation. An arrangement step, 1709 is a virtual wiring step between blocks, 171
0 is a conventional pin arrangement step.

The contents from the block arrangement step 1701 to the arrangement side determination step 1706 are the same as those described in the first embodiment. Hereinafter, the arrangement position designation step 1707 and subsequent steps will be described. After determining the block pin arrangement side in the arrangement side determination step 1706, the process returns to the rectangle generation step 1702 to determine the block pin arrangement side of all other nets. After the block pin arrangement sides of all nets are determined, the process proceeds to an arrangement position designation step 1707.

In the arrangement position designation step 1707, the arrangement position of the block pin assigned to the block pin arrangement side of each block determined in the arrangement side determination step 1706 is specified at an arbitrary position on the block pin arrangement side. An example of the designation method will be described below.

Designation is performed using the constraint condition of the block pin specified when performing the block layout with the CAD tool. When performing a block layout, it is general to set a constraint condition of a block pin for each block. The constraint conditions of the block pins control the movement of the block pins during the block layout, and there are four main conditions.

Restriction condition 1: The position of the pin arrangement is not specified at all.

Restriction condition 2: Designate a block side on which pins are to be arranged.

Restriction condition 3: Designate the block side where pins are to be arranged and the arrangement order.

Restriction condition 4: Designate a block side on which a pin is arranged and coordinates on the block side.

The constraint conditions as described above are created and read into the CAD tool to designate the block pin arrangement position at an arbitrarily designated position. Also, when generating the constraint condition, consideration is given not to change the block pin arrangement side determined in the arrangement side determination step 1706. Also, consideration is given to satisfy the rule of the interval between the pins arranged in the conventional pin arrangement step 1710. After designating the block pin arrangement position using the constraint condition, the process proceeds to the designated arrangement step 1708.

The designated arrangement step 1708 will be described with reference to FIG. FIG. 18 shows a block in which block pins are arranged at arbitrarily designated positions. Reference numeral 1801 denotes a block frame, and reference numeral 1802 denotes a block pin.

Each block pin 1802 changes the block pin arrangement position according to the arrangement position designated in the arrangement position designation step 1707. The CAD tool has a function of arranging according to the constraint conditions, and it is easy to automatically arrange by using the function.

By using the above method, the arrangement positions of the block pins are arbitrarily specified on all the block pin arrangement sides of all the blocks. After that, the inter-block virtual wiring step (floor plan step) is completed, and the semiconductor integrated circuit is designed as before.

According to the semiconductor integrated circuit design method (block pin arrangement position determination method) of the third embodiment configured as described above, block pins can be arranged at arbitrary positions. Wiring in a state where the wiring lengths are equalized becomes possible, and it becomes easy to realize a desired wiring in a state in which a difference in wiring length and an error are suppressed.

It is needless to say that, as in the case of the first embodiment, since long-distance inter-block wiring does not occur around the block, timing violations caused by long-distance wiring, virtual inter-block wiring and inter-block It is possible to prevent a timing violation from occurring due to a wiring error of the wiring.

Embodiment 4 Embodiment 4 of the present invention will be described with reference to the drawings.

FIG. 19 is a diagram showing a flowchart of the processing performed in the floor plan step of the method for designing a semiconductor integrated circuit according to the fourth embodiment of the present invention. In FIG.
Reference numeral 1901 denotes a block arrangement step, 1902 denotes a timing constraint list generation step, 1903 denotes a rectangle generation step, 1
904 is an obstacle confirmation step, 1905 is a center of gravity comparison step, 1
Reference numeral 906 denotes a rectangle extension step, 1907 denotes an arrangement side determination step,
908 is a timing constraint order placement step, 1909 is an inter-block virtual wiring step, and 1910 is a conventional pin placement step.

The block arrangement step 1901 is the same as the contents described in the first embodiment. After determining the shapes and arrangement positions of all the blocks, the process proceeds to a timing constraint list generation step 1902.

In the timing constraint list generating step 1902, the timing constraints between blocks are read, and a timing constraint list in the order of strict timing constraints is generated.
The inter-block timing constraint is a wiring constraint, such as a wiring length and a wiring capacitance, determined for each inter-block wiring manually determined.If the inter-block wiring is not generated to satisfy the specified timing constraint, This is a timing violation in the timing verification process.

After generating a timing constraint list in which block pins are arranged in order of strict timing constraints based on the constraint values of the timing constraints, the net names of the inter-block wires, and the names of the block pins connected by the nets. ,
It moves to the rectangle generation step 1903.

Steps from the rectangle generation step 1903 to the arrangement side determination step 1907 are the same as those described in the first embodiment. Hereinafter, the timing constraint order placement step 1908
The following will be described. After the placement side determination step 1907 determines the block pin placement side of the target net, the process proceeds to the timing constraint order placement step 1908.

In the timing constraint order placement step 1908,
The block pins assigned to the block pin arrangement side determined in the arrangement side determination step 1907 are arranged based on the timing constraint list in order from the position closest to the center of gravity of the rectangular frame within the block pin arrangement side.

At this time, when there is a block pin already arranged at a position closest to the center of gravity of the rectangular frame within the block pin arrangement side, a timing constraint list generation step 190
The block pins to which the stricter timing constraints are added are preferentially arranged based on a comparison based on the timing constraint list generated in step 2.

An example will be described with reference to FIG. FIG.
0 indicates the block pin arrangement arranged in the order of the strictest timing constraint from the position closest to the center of gravity of the rectangular frame. Reference numeral 2001 indicates a block arrangement area,
2006 represents blocks A to E, and 2007 represents block B20.
03, the center of gravity of the block E2006, 2008, a rectangular frame, 2009, a rectangular frame center of gravity (before expansion), 2010, an obstacle center of gravity, and 2011, a block pin.

Hereinafter, block B2003 and block E2
A net having a connection relationship with 006 and a block E2
An example of a method of determining the block pin arrangement position of the block pin 2011 allocated to the lower side of 006 will be described.

First, a position closest to the rectangular frame center of gravity 2009 within the lower side of the block E2006 is obtained. As a method for obtaining the coordinates, the coordinates of the rectangular frame center of gravity 2009 and the block E20
06 Both ends of the lower side or the center of the lower side, 1 /
By comparing the coordinates of a plurality of points such as the position 4, the position closest to the rectangular frame center of gravity 2009 is specified. Here, the position of the left end of the lower side of the block E2006 is
This is the position closest to No. 9.

Next, it is checked whether the block pin 2011 has already been arranged at the left end position of the lower side of the block E2006. As a result of the confirmation, when the block pin 2011 is not arranged at the left end position of the lower side of the block E2006, the block pin 2011
It is arranged at the left end position of the lower side of 2006. Here, it should be noted that it is the left end. That is, as described in the case of the uniform spacing, it is assumed that the block is not arranged at the lower left corner, and the space is slightly spaced from the left side of the block. For example, an interval corresponding to the minimum interval rule of the block pin is set.

On the other hand, when the block pin 2011 is already arranged at the left end position of the lower side of the block E2006, a stricter timing constraint is given based on the timing constraint list generated in the timing constraint list generation step 1902. The block pin 2011 is preferentially arranged at the lower left position of the lower side of the block E2006.

With the above arrangement, the block pin 201 which could not be arranged at the left end position of the lower side of the block E2006
1 specifies a position near the rectangular frame center of gravity 2009 next to the left end position, and checks whether the block pin 2011 is arranged at the specified position. If the block pin is not arranged at the specified position, it is arranged at the specified position as it is. If the block pin has been arranged at the specified position, the block pin 2011 to which a stricter timing constraint is given is preferentially arranged based on the information in the timing constraint list described above.

After the block pin arrangement position of the target net is determined by using the above method, the process returns to the rectangle generation step 1903, and is repeated until the block pin arrangement positions of all other nets are determined. After the block pin arrangement positions of all the nets are determined, the inter-block virtual wiring step 1908 (floor planning step) is completed, and the semiconductor integrated circuit is designed in the conventional manner.

According to the semiconductor integrated circuit design method (block pin arrangement position determination method) of the fourth embodiment thus configured, the block pin having more severe timing constraints is prioritized and is closer to the center of gravity of the rectangular frame. Since the pins are arranged on the side, that is, on the side closer to the partner block having a connection relationship, the arrangement position of the block pins can be determined so that the wiring length becomes shorter in the order of strict timing constraints. Therefore, since a timing violation that greatly deviates from the timing constraint does not occur, the processing for improving the timing violation is reduced.

The timing constraint list generation step 19
For the timing constraint between blocks used in 02,
Similar effects can be obtained by using a tool that outputs a wiring constraint such as a wiring length and a wiring capacity determined for each inter-block wiring, in addition to the manual creation.

The timing constraint order placement step 1908
When arranging the block pins, the length obtained by adding the vertical and horizontal sizes of the rectangular frame of the target net is obtained, and the constraint value per 1 μm is obtained and held based on the timing constraint value, and the constraint value per 1 μm is held. Is used for the comparison of the placement priority, it is possible to more accurately compare the strictness of the timing constraint, so that a better effect can be obtained.

It is needless to say that, as in the case of the first embodiment, since long-distance inter-block wiring does not occur around the block, timing violations caused by long-distance wiring, virtual inter-block wiring and inter-block It is possible to prevent a timing violation from occurring due to a wiring error of the wiring.

(Embodiment 5) Embodiment 5 of the present invention will be described with reference to the drawings.

FIG. 21 is a diagram showing a flowchart of the processing performed in the floor plan step of the method of designing a semiconductor integrated circuit according to the fifth embodiment of the present invention. In FIG.
Reference numeral 2101 denotes a block arrangement step, reference numeral 2102 denotes a temporary wiring length calculation step, reference numeral 2103 denotes a virtual timing verification step, 21
04 is a verification result list generation step, 2105 is a rectangle generation step, 2106 is an obstacle confirmation step, 2107 is a center of gravity comparison step, 2108 is a rectangle expansion step, 2109 is an arrangement side determination step, 2110 is a timing order arrangement step, and 2111 is a block. The inter-virtual wiring step 2112 is a conventional pin arrangement step.

The block arranging step 2101 is the same as the contents described in the first embodiment. After determining the shapes and arrangement positions of all the blocks, a temporary wiring length calculating step 210
Move to 2. In the provisional wiring length calculation step 2102, the wiring length between blocks for each net is obtained. An example of obtaining the inter-block wiring length will be described below.

First, the center of gravity of a block is obtained based on the vertical size and horizontal size of each block. Next, assuming that the block pins are arranged at the block center of gravity of each block, the inter-block temporary wiring length is obtained.

The method for obtaining the temporary wiring length is as follows. Focusing on the centers of gravity of two blocks having a connection relationship, a distance between two points along a Manhattan path (a path connecting two points without a detour in a combination of the X and Y directions) is obtained. That is, the distance obtained by adding the difference between the X coordinates and the difference between the Y coordinates of the two centers of gravity is defined as the inter-block temporary wiring length.

After calculating the inter-block tentative wiring length in this way, the process proceeds to a virtual timing verification step 2103.

In the virtual timing verification step 2103, virtual timing verification is performed based on the net list, the inter-block temporary wiring length obtained in the temporary wiring length calculation step 2102, and the inter-block timing constraint described in the fourth embodiment. Do. Delay calculation is performed based on the netlist and the inter-block temporary wire length obtained in the temporary wire length calculation step 2102, and it is verified whether or not the timing can be satisfied with respect to the timing constraint. After verification, a verification result list generation step 210
Move to 4.

In the verification result list generation step 2104, based on the verification result of the virtual timing verification step 2103, the net name of the inter-block wiring, and the name of the block pin connected by the net, the order in which the violation values with respect to the timing constraints are large is That is, a verification result list in which block pins are arranged in the order of strictness of satisfying the timing constraint based on the result of the timing verification is generated. After generating the verification result list, the process proceeds to the rectangle generation step 2105.

[0214] The steps from the rectangle generation step 2105 to the arrangement side determination step 2109 are the same as those described in the first embodiment. Hereinafter, the timing order arrangement step 2110 and subsequent steps will be described. After determining the block pin placement side of the target net in the placement side determination step 2109, the process proceeds to the timing order placement step 2110.

In the timing order arranging step 2110, the block pins assigned to the block pin arranging sides determined in the arranging side deciding step 2109 are arranged in order from the position closest to the rectangular frame center of gravity in the block pin arranging sides based on the verification result list. To place.

At this time, if there is a block pin already arranged at a position closest to the center of gravity of the rectangular frame in the block pin arrangement side, a comparison is made based on the verification result list generated in the verification result list generation step 2104, and Block pins that are more difficult to satisfy timing constraints are preferentially placed.

An example of the method will be described with reference to FIG. FIG. 22 shows block pin arrangements arranged in an order that strictly satisfies the timing constraint. Reference numeral 2201 denotes a block arrangement area, reference numerals 2202 to 2207 denote blocks A to E, 2207 denotes a center of gravity of the block B 2203 and the block E 2206. , 2208 is a rectangular frame, 220
9 is the center of gravity of the rectangular frame (before expansion), 2210 is the center of gravity of the obstacle, 2
211 denotes a block pin.

Hereinafter, block B2203 and block E2
A net having a connection relationship with the block 206 and a block E2
An example of a method for determining the block pin arrangement position of the block pin 2211 allocated to the lower side of the 206 will be described.

First, a position closest to the rectangular frame center of gravity 2209 within the lower side of the block E2206 is determined. As a method of obtaining, it is specified by the method described in the fourth embodiment. Here, the position of the left end of the lower side of the block E2206 is the position closest to the rectangular frame center of gravity 2209.

Next, it is confirmed whether or not the block pin 2211 is already arranged at the left end position of the lower side of the block E2206. As a result of the confirmation, if the block pin 2211 is not arranged at the left end position of the lower side of the block E2206, the block pin 2211 is directly replaced with the block E2206.
206 is arranged at the left end position of the lower side. Here, it should be noted that it is the left end. That is, as described in the case of the uniform spacing, it is assumed that the block is not arranged at the lower left corner, and the space is slightly spaced from the left side of the block. For example, an interval corresponding to the minimum interval rule of the block pin is set.

On the other hand, if the block pin 2211 is already arranged at the left end position on the lower side of the block E2206, the timing constraint must be satisfied based on the information in the verification result list generated in the verification result list generation step 2104. Uses the stricter block pin 2211 to block E22
06 is preferentially arranged at the left end position of the lower side.

The block pin 221 which could not be arranged at the left end position of the lower side of the block E2206 due to the above arrangement
1 specifies a position near the rectangular frame center of gravity 2209 next to the left end position, and checks whether the block pin 2211 is already arranged at the specified position. If the block pin is not arranged at the specified position, it is arranged at the specified position as it is. If the block pin has been arranged at the specified position, the block pin 2211 which is more strict to satisfy the timing constraint is preferentially arranged based on the information in the verification result list described above.

After the block pin arrangement position of the target net is determined by using the above-described method, the process returns to the rectangle generation step 2105, and the process is repeated because the block pin arrangement positions of all other nets are determined. After the block pin arrangement positions of all the nets are determined, the inter-block virtual wiring step 2111 (floor plan step) is completed, and the semiconductor integrated circuit is designed as before.

According to the semiconductor integrated circuit designing method (block pin arrangement position determining method) of the fifth embodiment thus configured, the order of the strictness of satisfying the timing constraint (timing verification result) is stricter. Since the block pins are preferentially arranged on the side closer to the rectangular frame center of gravity, that is, on the side closer to the block on the other side of the connection relationship, the order in which the strictness of satisfying the timing constraint (timing verification result) is stricter is set. Since the arrangement position of the block pins can be determined so that the wiring length is shortened, and a timing violation that greatly deviates from the timing constraint does not occur, the processing for improving the timing violation is reduced.

The virtual timing verification step 2103,
The inter-block timing constraint used in the verification result list generation step 2104 may be created manually or by using a tool that outputs a wiring constraint such as a wiring length and a wiring capacity determined for each inter-block wiring. Similar effects can be obtained.

Note that, instead of the inter-block temporary wiring length used in the virtual timing verification step 2103, wiring capacitance data or wiring delay data generally calculated from wiring statistical information called a wire load model can be used. It is.

When arranging the block pins in the timing order arranging step 2110, the length obtained by adding the vertical and horizontal sizes of the rectangular frame of the target net is determined, and the violation per 1 μm is determined based on the violation value that cannot satisfy the timing constraint. By obtaining and holding the value, and using the violation value per 1 μm for the comparison of the arrangement priority, it is possible to more accurately compare the violation values, so that a better effect can be obtained.

It is needless to say that, as in the case of the first embodiment, since long-distance inter-block wiring does not occur around a block, timing violations caused by long-distance wiring, virtual inter-block wiring and inter-block It is possible to prevent a timing violation from occurring due to a wiring error of the wiring.

Here, with regard to the timing constraints in the fourth and fifth embodiments, a supplementary explanation will be given on the method of determining the wiring length. Consider first and second two blocks that are connected to a common block of interest. A rectangular frame having a minimum size surrounding the center of gravity of the first block and the center of gravity of the common block is formed, and the length of the vertical side and the length of the horizontal side are added to form a first temporary wiring length. For example, the first temporary wiring length = 10 μm + 90 μm = 100 μm. Similarly, a rectangular frame having a minimum size surrounding the center of gravity of the second block and the center of gravity of the common block is formed, and the length of the vertical side and the length of the horizontal side are added to form a second temporary wiring length. For example, the second temporary wiring length = 60 μm + 90 μm = 150 μ
m. The timing constraint between the first block and the common block is R ₁ , and the timing constraint between the second block and the common block is R ₂ . Here, it is assumed that R ₁ = R ₂ = R ₀ for easy understanding. 1μ
When a constraint value per m is obtained, R _0/100 is obtained for the wiring between the first block and the common block.
For wiring between the second block and common block is R ₀ / 0.99. In comparison, since the latter is smaller, the latter wiring has priority. That is,
In the wiring from the common block to the first block and the wiring from the common block to the second block, the longer one of the provisional wiring lengths is the length of the block pin for wiring to the second block. With priority given to the arrangement, the blocks are arranged from the side closer to the center of gravity of the obstacle block on the block pin arrangement side of the common block.

(Embodiment 6) Embodiment 6 of the present invention will be described with reference to the drawings.

FIG. 23 is a diagram showing a flowchart of a process performed in the floor plan process of the method for designing a semiconductor integrated circuit according to the sixth embodiment of the present invention. In FIG.
Reference numeral 2301 denotes a block arrangement step, 2302 denotes a rectangle generation step, 2303 denotes an obstacle confirmation step, 2304 denotes a center of gravity comparison step, 2305 denotes a rectangle extension step, 2306 denotes an arrangement side determination step, 2307 denotes an arrangement confirmation step, and 2308 denotes an arrangement adjustment. Step 2309 is a block pin arrangement step, 2310 is an inter-block virtual wiring step, and 2311 is a conventional pin arrangement step.

The contents from the block arrangement step 2301 to the arrangement side determination step 2306 are the same as those described in the first embodiment. Hereinafter, the arrangement confirmation step 2307 and subsequent steps will be described. After determining the block pin arrangement side in the arrangement side determination step 2306, the process returns to the rectangle generation step 2302 to determine the block pin arrangement sides of all other nets. After the block pin arrangement sides of all nets are determined, the process proceeds to the arrangement confirmation step 2307.

The arrangement confirmation step 2307 and subsequent steps will be described with reference to FIG. FIG. 24 shows a result in which, when the number of block pins allocated to one block pin arrangement side overflows, the excess block pin is arranged on a block side adjacent to the block pin arrangement side. It is. In FIG. 24, reference numeral 2401 denotes a block arrangement area, and 2402 to 2406 denote blocks A to
E and 2407 indicate the center of gravity of the chip, and 2408 indicates a block pin.

Hereinafter, a method for confirming whether the number of block pins allocated to the block pin arrangement side overflows the permissible block pin arrangement amount, a method for adjusting the number of block pins in the case of overflow, and a method for adjusting the block pin arrangement Will be described. Here, block E2
A description will be given focusing on 406.

In the arrangement confirmation step 2307, it is confirmed whether the number of the plurality of block pins allocated to the block pin arrangement side does not exceed the allowable block pin arrangement amount of the block pin arrangement side. If the number of allocated block pins exceeds the permissible block pin arrangement amount of the block pin arrangement side, the block pins protrude from the block pin arrangement side and cannot be arranged on the block pin arrangement side. If they are forcibly arranged on the side where the block pins are arranged, there is a possibility that the arrangement of the block pins may not be able to satisfy the rule of the predetermined pin interval. Therefore, it is necessary to confirm the arrangement.

As an example of a checking method, in the arrangement checking step 2307, the chip center of gravity 240
Ask for 7. Next, the block pin arrangement allowable amount S for each block side is calculated from the block side length L and the minimum pin interval P of each block using the following equation.

S = (L / P) -1 When L is divided by P, the number of equally dividing the side L is obtained. The number of arranged block pins is one less than the equal number.
Therefore, the above equation is an equation for calculating the allowable block pin arrangement amount S.

By comparing the block pin arrangement allowable amount S obtained above with the allocated block pin number N, it is confirmed whether or not a block pin exceeding the block pin arrangement allowable amount S is allocated. The number of block pins N is compared with that of the conventional pin arrangement step 2311 including the pins arranged.

If the comparison result indicates that the number N of block pins is smaller, it can be seen that the number N of allocated block pins does not exceed the permissible amount S of block pins on the side where the block pins are arranged. It moves to the pin arrangement step 2309.

Conversely, if the block pin arrangement allowable amount S is smaller than the comparison result, it can be seen that the number N of allocated block pins exceeds the block pin arrangement allowable amount S of the block pin arrangement side. Move to step 2308.

In the lower side of the block E2406, description will be made assuming that the allowable block pin arrangement amount is S = 7 and the number of allocated block pins is N = 9. Since the number N of block pins exceeds the block pin arrangement allowable amount S, the arrangement adjustment process 2
Move to 308.

In the arrangement adjusting step 2308, the number of block pins corresponding to the excess block pins is calculated, and the excess of the block pins is assigned to the side closer to the chip center of gravity 2407 of the two sides connected to the block pin arrangement side. Change the block pin placement side for. In specifying the block pin whose arrangement side is to be changed, the pin assigned in the arrangement side determination step 2306 is specified in preference to the pin arranged in the conventional pin arrangement step 2311.

On the lower side of the block E2406, the number of excess block pins is “2” (= 9−7), and the two block pins are located at the chip centroid 2407 of the two sides connected to the lower side of the block E2406. The block pin arrangement side is changed to the closer side, that is, the left side of the block E2406.

Using the above method, the number of block pins is adjusted on the block sides of all the blocks, and the process proceeds to the block pin arranging step 2309.

In the block pin arranging step 2309, the arrangement is performed in the assigned block side based on the adjustment result of the block pin allocated in the arrangement adjusting step 2308. At this time, both the block pins originally allocated and the block pins additionally allocated in the layout adjustment step 2308 are arranged, but the block pins whose block pin layout sides have been changed are located close to the block pin layout sides before the change. Consider to place in.

As shown in FIG. 24, the arrangement adjusting step 230
On the left side of block E2406, which is the block pin arrangement side changed by step 8, two of the block pins whose block pin arrangement sides have been changed are arranged at positions near the lower side of block E2406 before the change. , And place the originally allocated block pin on the left side.

Using the above method, block pins are arranged on all the block pin arrangement sides of all blocks. Thereafter, the inter-block virtual wiring step 2310 (floor plan step) is completed, and the steps subsequent to the timing constraint generation step are performed as before, to design a semiconductor integrated circuit.

According to the semiconductor integrated circuit design method (block pin arrangement position determination method) of the sixth embodiment configured as described above, the number of block pins allocated to the block pin arrangement side is equal to the block pin arrangement. Even if the block pin arrangement tolerance of the side is exceeded, block pin arrangement is performed to prevent block pins from being placed in places other than the block pin arrangement side or block pin arrangement that can not meet the minimum spacing rule It is possible to prevent the regression of the design caused by the problem described above.

It is needless to say that, as in the case of the first embodiment, no long-distance inter-block wiring is generated around the block, so that a timing violation due to the long-distance wiring, a virtual inter-block wiring and an inter-block It is possible to prevent a timing violation from occurring due to a wiring error of the wiring.

(Embodiment 7) Embodiment 7 of the present invention will be described with reference to the drawings.

FIG. 25 is a view showing a flowchart of the processing performed in the floor plan step of the method of designing a semiconductor integrated circuit according to the seventh embodiment of the present invention. In FIG.
Reference numerals 2501 are a block arrangement step, 2502 is a rectangle generation step, 2503 is an obstacle confirmation step, 2504 is a center of gravity comparison step, 2505 is a rectangle expansion step, 2506 is an arrangement side determination step, 2507 is a block side center arrangement step, and 2508.
Denotes a virtual wiring step between blocks, and 2509 denotes a conventional pin arrangement step.

The contents from the block arrangement step 2501 to the arrangement side determination step 2506 are the same as those described in the first embodiment. Hereinafter, the block side center arranging step 250
7 will be described. After determining the block pin arrangement side in the arrangement side determination step 2506, the process returns to the rectangle generation step 2502 to determine the block pin arrangement sides of all other nets. After the block pin arrangement sides of all nets are determined, the process proceeds to a block side center arrangement step 2507.

In the block side center arranging step 2507, all the block pins allocated to the block pin arranging side of each block determined in the arrangement side deciding step 2506 are arranged in the center of the block side.

An example will be described with reference to FIG. FIG.
Reference numeral 6 denotes a block in which the block pins are arranged in the center of the block side, and reference numeral 2601 denotes a block arrangement area;
Reference numerals 2602 to 2606 denote blocks A to E, and reference numeral 2607 denotes a block pin.

The block pins 2607 on the lower side of the block E2606 are arranged at the center of the block side, but the block pins are arranged by the following example method.

First, ブ ロ ッ ク of the block side length is calculated, and its value is added to the start point of the block side end, thereby obtaining the block side center. With this method, the center of the block side is obtained on all the block sides of all the blocks.

Next, the block pin allocated in the arrangement side determining step 2506 is arranged at the center of the block side obtained above. After the block pins are arranged, the inter-block virtual wiring step 2508 (floor plan step) is completed, and logic synthesis is performed in the timing constraint generation step and the logic synthesis step.

Thereafter, in the block layout step, for the block pins arranged at the center of the block side, the block pin arrangement positions are re-determined by using, for example, the constraint condition information of the block pins specified in the block layout described above. . At this time, an arrangement side determination step 25
Consider that the block side determined in 06 is not changed. Thereafter, the semiconductor integrated circuit is designed as in the conventional case.

According to the semiconductor integrated circuit design method (block pin arrangement position determination method) of the seventh embodiment thus configured, the block pin arrangement position is strictly determined at the initial stage of design as in the floor plan process. When it is not possible, there are the following advantages. In order to generate timing constraints based on the block pins arranged at the center of the block pin arrangement side and the result of connecting the block pins with virtual interconnects between blocks, an average constraint between the inter-block interconnects in the logic synthesis process is set. Can be considered. afterwards,
Even if the block pin position determined in the layout process becomes a pessimistic pin position or an optimistic pin position with respect to the estimation, a timing violation that greatly deviates from the timing constraint occurs because the constraint is average. It becomes difficult to do. Further, even if a timing violation occurs, the timing constraint is not greatly deviated, so that the processing for improving the timing violation is reduced.

It is needless to say that, as in the case of the first embodiment, long-distance inter-block wiring does not occur around the block, so that timing violations caused by long-distance wiring and virtual inter-block wiring and inter-block It is possible to prevent a timing violation from occurring due to a wiring error of the wiring.

(Eighth Embodiment) An eighth embodiment of the present invention will be described with reference to the drawings.

FIG. 27 is a diagram showing a flowchart of the processing performed in the floor plan step of the method for designing a semiconductor integrated circuit according to the eighth embodiment of the present invention. In FIG.
Reference numeral 2701 denotes a block arrangement step, 2702 denotes a rectangle generation step, 2703 denotes an obstacle confirmation step, 2704 denotes a center of gravity comparison step, 2705 denotes a rectangle expansion step, 2706 denotes an arrangement side determination step, 2707 denotes a pessimistic position arrangement step, and 2708 denotes a block. The inter-virtual wiring step 2709 is a conventional pin arrangement step.

Steps from block arrangement step 2701 to arrangement side determination step 2706 are the same as those described in the first embodiment. Hereinafter, the pessimistic position arrangement step 2707 and subsequent steps will be described. After deciding the block pin placement side of the target net in the placement side determination step 2706, the pessimistic position placement step 27
Move to 07.

In the pessimistic position arranging step 2707, the block pins allocated to the block pin arranging side of each block determined in the arranging side deciding step 2706 are arranged at positions farthest from the center of gravity of the rectangular frame on the block pin arranging side.

An example will be described with reference to FIG. FIG.
Reference numeral 8 denotes a block pin in which the block pin is arranged at a position farthest from the center of gravity of the rectangular frame. In FIG. 28, reference numeral 2801 denotes a block arrangement area,
Reference numeral 806 denotes blocks A to E, 2807 denotes a center of gravity of blocks B and E, 2808 denotes a rectangular frame, 2809 denotes a rectangular frame center of gravity (before expansion), 2810 denotes an obstacle center of gravity, and 2811 denotes a block pin.

Hereinafter, block B2803 and block E2
A net having a connection relationship with the 806, and a block E2
An example of a method for determining an arrangement position of the block pin 2811 on the lower side of the block 806 will be described.

First, a position farthest from the rectangular frame center of gravity 2809 in the lower side of the block E2806 is determined. As a method for obtaining the coordinates, the coordinates of the rectangular frame center of gravity 2809 and the block E2
806: Both ends of the lower side or the center of the lower side, 1 from the lower side end
By comparing the coordinates of a plurality of points such as the position of / 4, the position farthest from the rectangular frame center of gravity 2809 is specified. Next, the block pin 2811 is arranged at a position farthest from the center of gravity 2809 of the rectangular frame specified within the lower side of the block E2806.

In FIG. 28, since the right end of the lower side of the block E2806 is the farthest position from the center of gravity 2809 of the rectangular frame, the block pin 2811 is arranged at the right end of the lower side.

After the block pin arrangement position of the target net is determined by using the above method, the process returns to the rectangle generation step 2702, and is repeated until the block pin arrangement positions of all other nets are determined. After the block pin arrangement positions of all nets are determined, the inter-block virtual wiring step 2708 (floor plan step) is completed, and logic synthesis is performed in the timing constraint generation step and the logic synthesis step.

Then, in the block layout step, for the block pin located farthest from the center of gravity of the rectangular frame, for example, by using the constraint condition information of the block pin specified at the time of the block layout described above, the block pin arrangement position is determined. Is determined again. At this time, consideration is made so that the block side determined in the arrangement side determination step 2706 is not changed. After that, the semiconductor circuit is designed as usual.

According to the semiconductor integrated circuit design method (block pin arrangement position determination method) of the eighth embodiment thus configured, the block pin arrangement position is strictly determined at the initial stage of design as in the floor plan process. When it is not possible, there are the following advantages. A block pin located farthest from the center of gravity of the rectangular frame within the block pin placement side,
In addition, since the timing constraint is generated based on the result of connecting the block pins with the virtual wiring between the blocks, the most pessimistic restriction on the wiring between the blocks can be considered in the logic synthesis process. Thereafter, the block pin arrangement position determined in the layout process does not become a more pessimistic pin position with respect to the estimation, and a situation in which the timing constraint cannot be satisfied does not occur. Therefore, no timing violation occurs.

It is needless to say that, as in the case of the first embodiment, no long-distance inter-block wiring is generated around the block, so that a timing violation caused by the long-distance wiring, a virtual inter-block wiring and an inter-block It is possible to prevent a timing violation from occurring due to a wiring error of the wiring.

Embodiment 9 Embodiment 9 of the present invention will be described with reference to the drawings.

FIG. 29 is a diagram showing a flowchart of the processing performed in the floor plan step of the method for designing a semiconductor integrated circuit according to the ninth embodiment of the present invention. In FIG. 29,
Reference numeral 2901 denotes a block arrangement step, 2902 denotes a rectangle generation step, 2903 denotes an obstacle confirmation step, 2904 denotes a center of gravity comparison step, 2905 denotes a rectangle expansion step, 2906 denotes a connection determination step, 2907 denotes an arrangement side determination step, and 2908 denotes a target net. Completion confirmation step 2909 is wiring area confirmation step, 291
0 is a wiring determination step, 2911 is a conventional pin arrangement step, 29
12 is a wiring prohibited area generation step, 2913 is a completion confirmation step, 2914 is a block pin arrangement position determination step, 291
Reference numeral 5 denotes a virtual wiring step between blocks.

The block arrangement step 2901 and the rectangle generation step 2902 are the same as those described in the first embodiment. Hereinafter, the obstacle confirmation step 2903 and subsequent steps will be described.

After a rectangular frame surrounding the block centroid of the connected block is generated in the rectangle generating step 2902, the flow proceeds to the obstacle confirming step 2903.

The obstacle confirming step 2903 will be described with reference to an example of a floor plan shown in FIG. FIG. 30 shows a rectangular frame surrounding the center of gravity of the block.
01 denotes a block arrangement area, 3002 to 3007 denote blocks A to F, 3008 denotes a center of gravity of the blocks A3002 and E3006, and 3009 denotes a rectangular frame.

Hereinafter, block A3002 and block E3
Assuming that there is a connection relationship with the block pin 006, a method of determining a block pin arrangement side will be described.

In the obstacle confirmation step 2903, the rectangular frame 300
Check if there are any obstacles that cross 9 vertically or horizontally
Confirm by the method described in the first embodiment. After confirming,
If there is an obstacle crossing the rectangular frame, the process moves to the next step of comparing the center of gravity 2904. On the other hand, when there is no obstacle crossing the rectangular frame, the process proceeds to the wiring area confirmation step 2909. In the floor plan of FIG. 30, since there is no block crossing the rectangular frame 3009, the process proceeds to the wiring area confirmation step 2909.

In the wiring area confirmation step 2909, as in the case of the conventional pin arrangement method, in each of the blocks having a connection relationship, the block side located closest to the connection destination block is searched to specify the wiring path. I do.

In the floor plan of FIG. 30, block A3
For connection information between 002 and block E3006,
A description will be given assuming that a wiring path passing through a wiring area between the lower side of the block C3004 and the upper side of the block D3005 is specified.

Next, the wiring area on the wiring route is specified, and the number A of routable lines is calculated for each wiring area. As a calculation method, for example, the following method is used to calculate based on information such as a wiring layer, a wiring width, and a wiring pitch.

If two blocks are arranged one above the other and the number A of wires that can be laid in the horizontal direction in the wiring area existing between them is calculated, the lower left Y-axis coordinate of the block arranged above , The vertical width H of the wiring area is calculated by subtracting the upper right Y-axis coordinate of the block arranged below.

Next, the number L of wiring layers that can be wired in the horizontal direction
And the wiring width W and the wiring interval P, the number A of routable wires is obtained by the following equation.

((HP) / (W + P)) * L In the floor plan shown in the example, the number A of wires that can be passed in the horizontal direction through the wiring area between the lower side of the block C3004 and the upper side of the block D3005 is expressed as Ask. After calculating the number A of routable wires, the process proceeds to a wiring determination step 2910.

In the wiring determination step 2910, the number A of routable lines for each wiring area obtained in the wiring area confirmation step 2909 is
It is checked whether the number B of wirings counted in the next conventional pin arrangement step 2911 does not exceed. If the number B of wires is smaller than the number A of routable wires (B <A), the process proceeds to the conventional pin arrangement step 2911. Conversely, when the number B of wires is equal to or more than the number A of routable wires (B ≧ A), the wiring prohibited area generation step 29
Move to 12.

In the floor plan of FIG. 30, block C3
The number B of wirings that passed through the wiring area between the lower side of 004 and the upper side of the block D3005 is determined by the wiring area confirmation step 290.
It is determined that the number A is equal to or larger than the number A that can be wired obtained in step 9, and the process proceeds to a wiring prohibited area generation step 2912.

On the other hand, if the number B of wires that have passed through the wiring area between the lower side of the block C3004 and the upper side of the block D3005 is smaller than the number A of routable lines obtained in the wiring area confirmation step 2909, the conventional pin placement step 2911 The processing in this case will be described later.

The wiring prohibited area generation step 2912 will be described with reference to FIG.

FIG. 31 shows a wiring prohibited area generated in the wiring prohibited area generating step 2912.
001 to 3009 are as described above. As new elements, reference numeral 3011 denotes a wiring prohibited area, 301
2 indicates the center of gravity of the rectangular frame 3009, and 3013 indicates the center of gravity of the obstacle.

In the wiring determination step 2910, a wiring prohibited area 3011 is generated in a wiring area in which it is determined that the allowable number of wirings and the number of passing wirings are the same. After the wiring prohibited area is generated, it is determined that it is impossible to pass through the wiring prohibited area, and both blocks facing up and down or left and right across the wiring prohibited area are connected, and the connected block is regarded as one obstacle. Treat as a block. After creating the routing prohibited area,
It moves on to the rectangle generation step 2902.

In FIG. 31, a wiring prohibited area 3011 is generated in a wiring area between the lower side of the block C3004 and the upper side of the block D3005. After the generation, the wiring prohibited area 301 is set until the block pin arrangement positions of all nets are determined.
1 and the upper and lower blocks C3004 and D3005 that are in contact with the area are connected and treated as one block as an obstacle. After the generation of the wiring prohibited area, the rectangle generation step 29
Move to 02.

The rectangle generation step 2902 is the same as that described above except that the connected block is treated as a block as one obstacle.

The obstacle confirmation step 2903 is the same as the contents described above except that the connected block is treated as one block. In FIG. 31, the connected block C300
Since block 4 and block D3005 are obstacles that cross the rectangular frame 3009 up and down, the process proceeds to the center of gravity comparison step 2904.

In the center of gravity comparing step 2904, the rectangular frame 300
The direction in which 9 is expanded is determined to one of four directions, up, down, left, and right. As a method of obtaining the extension direction, the method described in the first embodiment can be used.

In FIG. 31, the obstacle center of gravity 3013 is
Since the rectangular frame center of gravity 3012 exists in the upward direction, the extension direction is determined to be upward, and the process proceeds to the rectangular extension step 2905.

The rectangle expanding step 2905 will be described with reference to FIG. FIG. 32 shows an expansion result of the rectangular frame 3009. The reference numerals 3001 to 3013 are as described above, and the reference numeral 3014 indicates a block pin arrangement side as a new element.

The rectangular frame 3009 is expanded in the upward direction determined in the centroid comparison step 2904. When performing expansion, expansion is performed until a block edge that meets the following two conditions is touched.

The first condition is that, regardless of the presence / absence of a connection relationship, a block side that has not been in contact before expansion is set.

[0300] The second condition is that a block side exists in the direction in which an obstacle crosses the rectangular frame.

In FIG. 32, the rectangular frame 3009 is expanded until the rectangular frame 3009 contacts the upper side of the block A 3002, and the process proceeds to the connection determination step 2906.

In the connection judging step 2906, it is judged whether or not the block touched in the rectangle expanding step 2905 is a block having the target connection. If the blocks having a connection relationship have come into contact with each other, the process proceeds to an arrangement side determination step 2907. On the other hand, if blocks having no connection relationship are in contact, the process proceeds to the obstacle confirmation step 2903, and it is confirmed whether an obstacle still exists or an obstacle does not exist in the rectangular frame by rectangle extension.

In FIG. 32, since the rectangular frame 3009 is in contact with the upper side of the block A 3002, it is determined that the block A 3002 is in contact with a block having a connection relationship, and the flow advances to an arrangement side determination step 2907.

In the arrangement side determining step 2907, the block side which is in contact with the rectangular frame expansion in the rectangular expansion step 2905 is determined as the block pin arrangement side of the block. After the decision, the process moves to the target net completion confirmation step 2908.

As can be seen from FIG. 32, block A3
The upper side of 002 is the block pin arrangement side 3014. After the decision, the process moves to the target net completion confirmation step 2908.

In the target net completion confirmation step 2908, it is checked whether all the block pin arrangement positions or the block pin arrangement sides of the target net have been determined. If the arrangement side or the arrangement position has been determined for all the block pins of the target net, the process proceeds to the completion confirmation step 2913. On the other hand, if the arrangement side or the arrangement position is not determined for all the block pins of the target net, the process returns to the obstacle confirmation step 2903.

In FIG. 32, the block pin arrangement side of the block A 3002 has been determined, but the block pin arrangement side of the block E 3006 has not been determined, so the flow proceeds to the obstacle confirmation step 2903. The obstacle confirmation step 2903 is the same as the contents described above.

[0308] As shown in FIG.
Since the block 3004 and the block D3005 are obstacles crossing the rectangular frame 3009 up and down, the process proceeds to the center of gravity comparing step 2904. The center-of-gravity comparing step 2904 is the same as the content described above. The expansion direction is upward, as before.

[0309] The rectangle extension step 2905 will be described with reference to FIG. The rectangular frame 3009 is further expanded in the upward direction determined in the center of gravity comparison step 2904. Here, the rectangular frame 3009 is expanded until the rectangular frame 3009 contacts the upper side of the block E3006, and a connection determination step 2906 is performed.
Move on to The connection determination step 2906 is the same as the content described above.

In FIG. 33, since the rectangular frame 3009 is in contact with the upper side of the block E3006, it is determined that the block E3006 is in contact with a block having a connection relationship, and the flow advances to the arrangement side determination step 2907. The arrangement side determination step 2907 is the same as the content described above.

In FIG. 33, the upper side of the block E3006 is defined as a block pin arrangement side 3014. After the decision, the process moves to the target net completion confirmation step 2908. The target net completion confirmation step 2908 is the same as the content described above.

Here, since the block pin arrangement sides of the block A3002 and the block E3006 are determined,
Move to the completion confirmation step 2913.

[0313] In the completion confirmation step 2913, it is confirmed whether the arrangement side or arrangement position of the pin is determined in all nets. If the arrangement side of the block pin has been determined for all nets, the block pin arrangement position determination step 2914
Move on to If the arrangement side of the block pin has not been determined for all the nets, the process returns to the rectangle generation step 2902 to process the unprocessed nets.

Here, it is assumed that the block pin arrangement sides or arrangement positions of all nets have been determined, and the flow shifts to the block pin arrangement position determination step 2914.

In the block pin arrangement position determining step 2914, the block pin arrangement position is determined within the block side determined in the arrangement side determining step 2907. At this time, the pin position is determined so as to satisfy a predetermined rule of the pin interval. After all the block pin arrangement positions are determined, the inter-block virtual wiring step 2915 (floor plan step) is completed, and the steps subsequent to the timing constraint generation step are performed to design the semiconductor integrated circuit as in the related art.

Here, a conventional pin placement step 2911 which is the next step in the case where the number B of wirings in the wiring area is smaller than the number A of possible wirings in the wiring determination step 2910 will be described with reference to FIG. FIG. 34 shows the pin arrangement positions determined in the conventional pin arrangement step 2911.
09 is as described above. As a new element, reference numeral 3010 indicates a block pin arrangement position.

On the basis of the information on the wiring path specified in the wiring area confirmation step 2909, a block side on which the block pins are to be located is searched, and the block pin arrangement position 3010 is determined. That is, the right side of block A3002, block E
A block pin arrangement position 3010 is provided on the left side of 3006. After the block pin arrangement position 3010 is determined, the number of passages is counted for each of the passed wiring areas, and the process proceeds to the target net completion confirmation step 2908.

According to the semiconductor integrated circuit design method (block pin arrangement position determination method) of the ninth embodiment thus configured, the block pin arrangement side and the number A of routable lines are taken into consideration with respect to the position of the wiring area. Since the block pin arrangement position is determined, there is no need to allocate block pins that allow the wiring area to pass through more than the number A that can be wired in the wiring area. Therefore, wiring that goes around the block does not occur due to wiring congestion, so that it is possible to prevent occurrence of a timing violation due to a wiring error between the virtual wiring between blocks and the wiring between blocks.

When calculating the number A of routable wires in the wiring area, it is necessary to consider that the amount of loss in the contact arrangement area for wiring replacement and wiring replacement is subtracted from the obtained number A of routable wires, and that it is underestimated. It is also possible.

Note that, similarly to the first embodiment, since long-distance inter-block wiring does not occur around a block, timing violations caused by long-distance wiring, virtual inter-block wiring and inter-block It is possible to prevent a timing violation from occurring due to a wiring error of the wiring.

[0321]

As described above, according to the present invention, when determining an arrangement side of a block pin as a basis for connecting blocks having a connection relation, when an obstacle block exists, an opposite side is avoided. In order to determine the placement side of the block pins rationally, it is not necessary to place the block pins on the block side where long-distance wiring goes around the block, and therefore, a timing violation caused by long-distance wiring occurs Can be prevented. Further, it is possible to prevent a timing violation from occurring due to a wiring error between the virtual wiring between blocks and the wiring between blocks.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a process performed in a floor plan process according to a first embodiment of the present invention.

FIG. 2 is a diagram showing that a block centroid of a block having a connection relation in Embodiment 1 of the present invention is surrounded by a rectangle;

FIG. 3 is a diagram showing a flowchart for determining an extension direction in a center-of-gravity comparing step according to the first embodiment of the present invention;

FIG. 4 is a diagram showing a center of gravity of a rectangular frame and a center of gravity of an obstacle according to the first embodiment of the present invention;

FIG. 5 is a diagram showing a result of rectangle extension according to the first embodiment of the present invention;

FIG. 6 is a diagram illustrating a block side determined as a block pin arrangement side according to the first embodiment of the present invention;

FIG. 7 is a diagram illustrating an example of a second type of floor plan according to the first embodiment of the present invention, in which a block center of gravity of a block having connection relation is surrounded by a rectangular frame;

FIG. 8 is a diagram showing an example of a second type of floor plan according to the first embodiment of the present invention, showing a rectangular frame center of gravity and an obstacle center of gravity.

FIG. 9 is a diagram showing an example of a result of rectangle extension in an example of a second type of floor plan according to the first embodiment of the present invention.

FIG. 10 is a diagram showing an example of a second type of floor plan according to the first embodiment of the present invention, showing a block side determined to be a block pin arrangement side;

FIG. 11 is a diagram illustrating an example of a third type of floor plan according to the first embodiment of the present invention, in which a block centroid of a block having connection relation is surrounded by a rectangle;

FIG. 12 is a diagram illustrating an example of a third type of floor plan according to the first embodiment of the present invention, showing block pin arrangement positions determined using a conventional pin arrangement method.

FIG. 13 is a diagram illustrating an example of a fourth type of floor plan according to the first embodiment of the present invention, in which a block centroid of a block having connection relation is surrounded by a rectangle;

FIG. 14 is a diagram showing an example of a fourth type of floor plan according to the first embodiment of the present invention, showing a block pin arrangement position determined using a conventional pin arrangement method.

FIG. 15 is a diagram showing a flowchart of a process performed in a floor plan process according to the second embodiment of the present invention.

FIG. 16 is a diagram showing a block pin arrangement result of arrangement at equal intervals according to the second embodiment of the present invention;

FIG. 17 is a diagram showing a flowchart of a process performed in a floor plan process according to the third embodiment of the present invention.

FIG. 18 is a diagram showing a block pin arrangement result obtained by performing an arbitrary designated arrangement according to the third embodiment of the present invention;

FIG. 19 is a view illustrating a flowchart of processing performed in a floor plan process according to the fourth embodiment of the present invention.

FIG. 20 is a diagram showing a block pin arrangement arranged in an order of strict timing constraints according to the fourth embodiment of the present invention;

FIG. 21 is a diagram showing a flowchart of a process performed in a floor plan process according to the fifth embodiment of the present invention.

FIG. 22 is a diagram illustrating a block pin arrangement arranged in an order that strictly satisfies a timing constraint determined based on a virtual timing verification result according to the fifth embodiment of the present invention;

FIG. 23 is a diagram showing a flowchart of a process performed in a floor plan process according to the sixth embodiment of the present invention.

FIG. 24 is a diagram showing the result of changing the block pin arrangement side to the side where the excess number of block pins is in contact with the block pin arrangement side and performing pin arrangement according to the sixth embodiment of the present invention;

FIG. 25 is a view showing a flowchart of a process performed in a floor plan process according to the seventh embodiment of the present invention.

FIG. 26 is a diagram showing a block in which a block pin is arranged in the center of a block side according to a seventh embodiment of the present invention.

FIG. 27 is a view illustrating a flowchart of processing performed in a floor plan step according to Embodiment 8 of the present invention.

FIG. 28 is a diagram showing a block pin according to an eighth embodiment of the present invention in which the block pin is arranged at a position farthest from the center of gravity of the chip.

FIG. 29 is a view illustrating a flowchart of processing performed in a floor plan step according to Embodiment 9 of the present invention.

FIG. 30 is a diagram showing that a block center of gravity of a block having a connection relation in Embodiment 9 of the present invention is surrounded by a rectangular frame.

FIG. 31 is a diagram showing a wiring prohibited area, a rectangular frame center of gravity, and an obstacle center of gravity in the ninth embodiment of the present invention.

FIG. 32 is a diagram showing a rectangle expansion result and a block side determined as a block pin arrangement side according to the ninth embodiment of the present invention.

FIG. 33 is a diagram showing a rectangle expansion result and a block side determined as a block pin arrangement side according to the ninth embodiment of the present invention;

FIG. 34 is a diagram showing block pin arrangement positions determined using a conventional pin arrangement method according to the ninth embodiment of the present invention.

FIG. 35 is a view showing a flowchart of a process in a conventional method of designing a semiconductor integrated circuit.

FIG. 36 is a view showing a flowchart of processing of a conventional block pin arrangement method.

FIG. 37 is a diagram showing a block pin arrangement position determined using a conventional block pin arrangement method and virtual wiring between blocks.

FIG. 38 is a diagram showing a block pin arrangement position determined using a conventional block pin arrangement method, and a wiring length error between a virtual wiring between blocks and a wiring between blocks.

[Explanation of symbols]

101, 1501, 1701, 1901, 2101,
301, 2501, 2701, 2901 ... Block arranging process 102, 1502, 1702, 1903, 2105, 2
302, 2502, 2702, 2902... Rectangle generation step 103, 1503, 1703, 1904, 2106, 2
303, 2503, 2703, 2903: Obstacle confirmation step 104, 1504, 1704, 1905, 2107, 2
304, 2504, 2704, 2904... Gravity center comparison step 105, 1505, 1705, 1906, 2108, 2
305, 2505, 2705, 2905... Rectangle extension process 106, 1506, 1706, 1907, 2109, 2
306, 2506, 2706, 2907... Arrangement side determining step 107, 2914... Block pin position determining step 108, 1508, 1709, 1909, 2111, 11
310, 2508, 2708, 2915 ... virtual wiring steps between blocks 109, 1509, 1710, 1910, 2112, 2
311, 2509, 2709, 2911 ··· Conventional pin placement step 301 ··· Rectangular rectangle / obstacle center of gravity calculation step 302 ··· Direction determination step 303 ··· Up / down determination step 304 ··· Left and right determination step 1507 ··· ... Arrangement position designation step 1708... Designation arrangement step 1902... Timing constraint list generation step 1908... Timing constraint order arrangement step 2102... Temporary wiring length calculation step 2103... Virtual timing verification step 2104. 2110: Arrangement step in timing order 2307: Arrangement confirmation step 2308: Arrangement adjustment step 2309: Block pin arrangement step 2407: Chip center of gravity 2507: Block side center arrangement step 2707: Graceful position arrangement step 2906: Connection Judgment process 2908 ... Completed target net Confirmation step 2909 wiring area confirmation step 2910 wiring determination step 2912 wiring prohibited area generation step 2913 completion confirmation step 3501 floor plan step 3502 timing constraint generation step 3503 logic synthesis step 3504 ... Block layout step 3505... Timing verification step in block 3506... Top layout step 3507... Hierarchical timing verification step 3508... Driving capacity optimization step 3509.
01, 2401, 601, 2801, 3001... Block arrangement areas 202 to 206, 702 to 707, 1102 to 110
7, 1302-1307, 2002-2006, 220
2-2206, 2402-2400, 2602-260
6, 2802 to 2806, 3002 to 3007 ... Blocks 207, 708, 1108, 1308, 2007, 22
07, 2807, 3008 ... Block centroids 208, 709, 1109, 1309, 2008, 22
08, 2808, 3009 ... rectangular frame 209, 710, 2009, 2209, 2809, 30
12: rectangular frame center of gravity 210, 711, 2010, 2210, 2810, 30
13: Obstacle center of gravity 211, 712, 3014 ... Block pin arrangement side 1110, 1310, 3010 ... Block pin arrangement position 1601, 1801 ... Block frame 1602, 1802, 2011, 211, 2408,
2607, 2811: Block pin 3011: Wiring prohibited area

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/822 F-term (Reference) 5B046 AA08 BA06 DA05 5F038 CA03 CA10 CA17 CD05 CD09 CD13 EZ09 EZ20 5F064 DD02 DD03 DD07 DD10 DD14 DD18 DD25 EE02 EE03 EE08 EE15 EE16 EE19 EE43 EE47 EE57 HH06

Claims (11)

[Claims] 1. A method for designing a semiconductor integrated circuit, in which a plurality of functional blocks are arranged on a chip and a desired function is realized by connecting the functional blocks, the method comprising the steps of connecting a plurality of blocks. A rectangle generation step of obtaining a center of gravity and creating a rectangular frame surrounding the block centroids; an obstacle checking step of checking whether an obstacle crossing the rectangular frame exists; a center of gravity of the obstacle and a center of gravity of the rectangular frame A center-of-gravity comparing step of determining the extension direction of the rectangular frame, a rectangular extension step of extending the rectangular frame in the extension direction until it contacts a block side of a block having a connection relationship, and a block side in contact with the rectangular frame. A step of determining an arrangement side to be an arrangement side of a block pin. 2. The method according to claim 1, further comprising, after the arrangement side determining step, an equal arrangement step of arranging the block pins assigned to the same block pin arrangement side at equal intervals within the block pin arrangement side. The method for designing a semiconductor integrated circuit according to claim 1. 3. An arrangement position designating step for designating an arrangement position of the block pins allocated to the same block pin arrangement side after the arrangement side determining step, and a pin arrangement designated in the arrangement position designating step. 2. A design method for a semiconductor integrated circuit according to claim 1, further comprising a step of designating a block pin according to a position. 4. The method according to claim 1, further comprising the step of generating a timing constraint list for reading a timing constraint, and, after the step of determining an arrangement side, giving priority to a block pin having a strict timing constraint read in the timing constraint list generation step. 2. The method according to claim 1, further comprising the step of arranging block pins having stricter timing constraints in order from a side closer to the center of gravity of the rectangular frame within the block pin arrangement side determined in the determination step. Semiconductor integrated circuit design method. 5. A tentative wiring length calculating step of temporarily arranging a block pin at the center of a block to calculate a tentative wiring length between blocks, and performing a delay calculation based on the inter-block wiring length to determine whether a timing constraint is satisfied. A virtual timing verification step of performing such timing verification, and a verification result list generation step of generating a verification result list in which the order of strictness of satisfying the timing constraint based on the result of the timing verification is generated. After the determination step, the block pin arrangement side determined in the arrangement side determination step with priority given to the stricter block pins in the order of the strictness of satisfying the timing constraint indicated by the verification result list generated in the verification result list generation step Within which the stricter block pins of the order are arranged in order from the side closer to the center of gravity of the rectangular frame. 2. The method for designing a semiconductor integrated circuit according to claim 1, further comprising a sequential arrangement step. 6. An arrangement confirming step for confirming whether all of the block pins arranged on the same block pin arrangement side can be arranged after the arrangement side determining step, and an arrangement complete on the block pin arrangement side. 2. The method for designing a semiconductor integrated circuit according to claim 1, further comprising: an arrangement adjusting step of adjusting an arrangement of no excess block pins on a block side adjacent to the block pin arrangement side. 7. A block side center arranging step of arranging the block pins arranged on the same block pin arranging side at the center of the block pin arranging side after the arrangement side deciding step. The method for designing a semiconductor integrated circuit according to claim 1. 8. A pessimistic position arranging step of arranging the block pins arranged on the block pin arranging side at a position farthest from a rectangular frame center of gravity on the block pin arranging side after the arrangement side deciding step. 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein: 9. A connection judging step of judging whether a block side contacted by the rectangular frame is a connected block, and, when it is judged that the block side is connected, the block side contacting the rectangular frame is determined by the connection. The method includes a placement side determining step as a placement side of a block pin, a wiring area confirmation step of calculating the number of possible wires that can pass through the wiring area, and a wiring prohibited area generation step of providing a wiring prohibited area in a wiring area that cannot pass. The method for designing a semiconductor integrated circuit according to claim 1. 10. The semiconductor integrated circuit according to claim 1, wherein the description is made in such a manner that the description is replaced with “measures frame” instead of “rectangular frame”. Design method. 11. The design of a semiconductor integrated circuit according to claim 1, wherein the description is made in such a manner that “center of gravity” is replaced with “near the center of gravity”. Method.