CN112685991A - Wiring method meeting constraint - Google Patents
Wiring method meeting constraint Download PDFInfo
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- CN112685991A CN112685991A CN202011528148.4A CN202011528148A CN112685991A CN 112685991 A CN112685991 A CN 112685991A CN 202011528148 A CN202011528148 A CN 202011528148A CN 112685991 A CN112685991 A CN 112685991A
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Abstract
A routing method that satisfies a constraint, comprising the steps of: reading the wiring parameters, acquiring grid data and constraint of the wiring layer, and constructing a wiring grid; setting a wiring starting node, and adding the starting node into a priority queue; searching a wiring path, expanding nodes of a priority queue according to a low-cost sequence to a high-cost sequence, and pressing the expanded nodes into the priority queue; and inquiring the expansion area to generate a wiring path which accords with the design rule. The wiring method meeting the constraint can connect the pins in the multi-terminal wire network, and ensures that the wiring result meets the minStepEdgeLength constraint.
Description
Technical Field
The invention relates to the technical field of VLSI (very large scale integration) design, in particular to a wiring method which meets the minStepEdgeLength (minimum length of a graphic frame) constraint in the detailed wiring of a very large scale integration.
Background
With the progress of the process, the ultra-deep submicron process is continuously perfected, the number of devices is rapidly increased under the condition of reducing the area of a chip, the density of the chip is more and more dense, and the difficulty of physical design is continuously increased. The wiring as the back-end node of the physical design in the very large scale integrated circuit is the key stage of the failure of the chip design, which makes the application of EDA (electronic design automation) tools an indispensable auxiliary means.
The wiring refers to distributing metal wires among units, pins or other electronic devices to be connected in a physical design stage, so that the connectivity of the pins of the wire network is ensured, the distributed metal wires are not short-circuited, and physical design constraints (design rules) are also met.
With the maturity of the photolithography process, the improvement of the chip performance often means the increase of the chip density, the routing space is further reduced, the number of the critical net constraints is continuously increased, and finally the routing difficulty and complexity are greatly increased, which brings new challenges to the EDA tool.
In the FinFET high-end process of 14nm and below, the wiring density is increased, and the physical design of the wiring is considered to be better while the space is considered to be minimum. The wiring results of the nets such as the power line (PG Net), the Signal line (Signal Net), and the Clock line (Clock Net) play a key role in the performance of the chip, for example, the power line has a larger width than a normal Net, and even if the power line is turned on, the voltage does not meet the requirement of the driving voltage, and the devices in the region still cannot work. The wire mesh length of the signal wire is too large, the signal is attenuated, and the device cannot obtain the signal. The clock line is used in the synchronous circuit and is the key of synchronous operation of the devices. These nets are therefore referred to as critical nets, the routing results of which often determine chip performance.
The minStepEdgeLength constraint is one of many design rules. The minstepedength constraint is a requirement that the side length of the manufactured graph is not less than a constraint value. The key wire mesh often involves communication among pins, and the first section of metal wire connected with the pins uses the width of the pins until through holes are drilled on the metal wire, so that the wire width is increased for wiring, and in the high-end process manufacturing with more tense wiring space, the constraint requirements are met, and new challenges are brought to wiring tools.
In a high-end process, EDA manufacturers are required to develop a wiring tool aiming at a critical wire network, meeting the design rule of minstepedlength.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a wiring method meeting the constraint, which can connect pins in a multi-terminal wire network and ensure that a wiring result meets minStepEdgeLength constraint.
In order to achieve the above object, the present invention provides a wiring method satisfying constraints, including the steps of:
reading the wiring parameters, acquiring grid data and constraint of the wiring layer, and constructing a wiring grid;
setting a wiring starting node, and adding the starting node into a priority queue;
searching a wiring path, expanding nodes of a priority queue according to a low-cost sequence to a high-cost sequence, and pressing the expanded nodes into the priority queue;
and inquiring the expansion area to generate a wiring path which accords with the design rule.
And further, the step of reading the wiring parameters, acquiring grid data and constraint of the wiring layer and constructing a wiring grid further comprises the step of adding grid data parallel to the preset direction to the grid according to the information of the pins.
Further, the step of setting a routing start node further comprises,
taking nodes on the same layer and nodes inside the pins as initial nodes of the pins;
the node on the same layer is the middle point of the pin frame;
the nodes in the pins are the intersection points of the horizontal central line and the vertical central line of the rectangle and the grids, and do not contain points on the frame.
Further, the step of searching for a routing path to expand nodes in the priority queue in order of cost further comprises,
and performing same-layer expansion on the nodes of the pin frame, and performing layer-skipping expansion on the nodes in the pin.
Further, the step of querying the expansion area to generate the routing path that meets the design rule further includes querying whether the metal wire generated at the current position violates the design rule or not when the start node of the frame expands along the specified direction, and if so, increasing the cost value of the expansion node.
Furthermore, the step of querying the expansion region to generate a wiring path meeting the design rule further includes generating rectangles of top metal, bottom metal and a via layer according to the via parameters when nodes inside the pins are subjected to layer-skipping expansion, querying whether the design rule is violated in the rectangular regions of the top metal, the bottom metal and the via layer, and if so, increasing the cost value of the expansion node.
Further, the step of inquiring the expansion area and generating a wiring path according with the design rule further comprises the steps that a metal wire in a wiring result is directly connected with the pin, a starting node of the metal wire is positioned on the middle point of a pin frame, and when the metal wire is vertical, the wiring width is the width of a pin graph; when the metal lines are horizontal, the wiring width is the height of the pin pattern.
Further, the step of querying the expansion area and generating a wiring path according with the design rule further comprises the steps that the through hole in the wiring result is connected with the pin, the first section of metal wire connected with the through hole meets the design rule constraint between the graph of the through hole on the layer where the metal wire is located and the first section of metal wire, and when the first section of metal wire is vertical, the wiring width is the width of the graph of the through hole; when the metal lines are horizontal, the width of the wiring is the height of the via pattern.
To achieve the above object, the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to execute the steps of the wiring method satisfying the constraints as described above.
To achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed, performs the steps of the wiring method satisfying the constraints as described above.
The wiring method, the electronic device and the computer readable storage medium which satisfy the constraints of the present invention have the following advantageous effects:
1) the wiring method meeting the minStepEdgeLength constraint automatically adjusts the grid correspondence of the pins, sets the corresponding starting point and achieves the expected wiring result.
2) The process is broken down into multiple queries, and DRC can be effectively reduced.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow diagram of a routing method that satisfies constraints in accordance with the present invention;
FIG. 2 is a schematic diagram of a lead corresponding to an added centerline and a boundary line according to an embodiment of the invention;
FIG. 3 is a diagram illustrating a starting point of a pin according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a pin expansion node according to an embodiment of the invention;
FIG. 5 is a schematic diagram illustrating a set routing parameter according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a first segment of metal lines with a top level lead out having a width equal to a height of the lead according to an embodiment of the invention;
fig. 7 is a schematic diagram illustrating that the width of a first metal line segment of a same-layer vertical lead-out pin is equal to the width of the pin according to an embodiment of the invention;
FIG. 8 is a schematic diagram of a wiring according to an embodiment of the present invention;
fig. 9 is a diagram illustrating the result of a via out lead and a same layer out lead according to an embodiment of the invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of a routing method satisfying constraints according to the present invention, and the routing method satisfying constraints of the present invention will be described in detail with reference to fig. 1.
First, in step 101, before wiring, the wiring grid is preprocessed, and grids of the lead frame and the center are added.
Preferably, the routing parameters are read, grid data and constraints for each routing layer are obtained, and a preliminary routing 3-D grid is constructed.
Preferably, a new routing grid is added according to the pin information and constraint information.
In this embodiment, the grid graph is an important component of the routing because the path search algorithm works directly on the grid. In the grid map, various costs and attributes can be assigned to the attributes of the corresponding point and the edge. Based on a classical horizontal-vertical model, one layer is horizontal, two adjacent layers are vertical certainly, and horizontal grids are added necessarily on the horizontal layer; the addition of vertical grids must be added on the vertical layer. The corresponding adding of the central line and the boundary line of the pin is shown in fig. 2, the pin adds grid data parallel to the preset direction to the grid, and the grid data and the horizontal and vertical 3D structure are displayed in a plane in an overlapping manner.
In step 102, a starting point for the routing is defined and added to the priority queue.
Preferably, the starting points of the pins are of two types: 1) the nodes on the same layer are the middle points of the pin frames; 2) the nodes inside the pins are the intersection points of the horizontal central line and the vertical central line of the rectangle and the grid, and do not contain points on the frame.
In this embodiment, all the intersections on the pins and the grid may be used as nodes in the extended queue, but in order to satisfy minstepedength (minimum length of the graph frame), a start point must be defined, as shown in fig. 3.
At step 103, the least costly node in the queue is preferentially expanded using the a-search routing path.
Preferably, the nodes in the lead frame can be expanded in the same layer, and the nodes in the lead frame can be expanded only in a layer jump manner.
Preferably, the node can perform 6 directional extensions, which are the same layer north, east, south and west, and the jump layer extension direction is up and down, respectively. Among them, north, east, south, west are extensions of the same layer, and upward and downward are extensions of the skip layer, and extra through holes are needed to ensure connectivity.
In step 104, the expanded area is queried in real time during the routing process to generate a routing path.
Preferably, when a specific start point node is expanded in a specified direction, it is queried whether DRC (Design Rule Check) is generated when a metal line is generated at the current position.
Preferably, a larger cost value is added to the cost of the expanded nodes if DRC are generated.
Fig. 4 is a schematic diagram of a pin extension node according to an embodiment of the invention.
In this embodiment, the extension of the starting point of the lead frame, for example, the starting point of the right frame of the lead, is only to extend to the east, and the height of the lead is used as the line width of the metal line to construct the outer frame of the metal line, and then the minimum spacing distance is added to construct the query rectangle. As shown in fig. 4, the pin expands the node, determines whether there is a DRC range, and if there is an obstacle in the query rectangle, the cost of this expansion is assigned a larger value.
In this embodiment, the jump layer of the starting point inside the pin is expanded, and the rectangles of the top metal layer, the bottom metal layer, and the via layer are generated according to other parameters of the via. And querying whether barriers exist in the rectangular areas of the top layer, the bottom layer and the through hole layer through the data structure, and judging whether DRC can be generated. After layer jump expansion, expansion in any direction can be performed except for the direction opposite to the previous expansion direction.
In this embodiment, the method further includes generating rectangles of the top metal layer, the bottom metal layer, and the via layer according to the via parameters when the nodes inside the pins perform layer jump expansion, and querying whether the rectangular areas of the top metal layer, the bottom metal layer, and the via layer exceed the pin frame.
Exceeding the lead frame is realized by preprocessing, the lead is retracted inwards to half the width of the outer frame (enclosing wall) of the through hole and half the width of the cut (cut), and if the width is not in the range, the cost is increased.
FIG. 5 is a diagram illustrating a layout parameter setting process according to an embodiment of the present invention.
In this embodiment, as shown in fig. 5, two pages are set metal layer and Via data, respectively.
In step 105, in the stage of converting the found path into a layout, an optimal line width wiring is selected at a position satisfying the constraint, and no DRC is generated.
Preferably, the wiring result is that the metal wire is led out of the pin, the minStepEdgeLength constraint is met, when the starting point of the metal wire is on the middle point of the pin frame, the first section of the metal wire is vertical and is on the same layer with the pin, and the width is the width of the pin graph; the first section of metal wire is horizontal and in the same layer with the pin, and the width is the height of the pin pattern.
Preferably, the wiring result is that the through hole leads out of the pin, the minStepEdgeLength constraint is satisfied, the graph of the through hole on the pin layer does not exceed the range of the pin, and the center of the through hole is positioned on the horizontal or vertical central line of the pin and cannot be positioned on the frame of the pin.
Preferably, the first segment of metal line connected to the via hole, in order to satisfy minstephedgelength constraint of the via hole between the pattern of the layer where the metal line is located and the first segment of metal line, includes that the metal line is vertical, and the width is the width of the via hole pattern; the metal lines are horizontal and the width is the height of the via pattern.
FIG. 8 is a schematic diagram of a layout according to an embodiment of the present invention.
In this embodiment, as shown in fig. 8, the width of the first metal line segment of the skip-level lead is aligned with the via. The width of the metal line from the upper left corner to the lower left corner is equal to the width of the via. The width of the metal line from the lower right corner to the lower left corner is equal to the height of the through hole.
The routing method satisfying the constraints of the present invention is further described below in conjunction with a specific embodiment.
Fig. 9 is a diagram illustrating the result of a via out lead and a same layer out lead according to an embodiment of the invention.
(1) The wiring command is initiated and the wiring parameters are set in fig. 9.
(2) Clicking the mouse selects the starting object or the relay point to be connected for wiring operation, as shown in fig. 9, and clicking the mouse selects the wiring pin in order to meet the design requirement.
(3) Right clicking generates a routing result as in fig. 9.
In an embodiment of the present invention, there is also provided an electronic device, including a memory and a processor, the memory having stored thereon a computer program running on the processor, the processor executing the computer program to perform the steps of the wiring method satisfying the constraints as described above.
In an embodiment of the present invention, there is also provided a computer readable storage medium having stored thereon a computer program which when run performs the steps of the wiring method satisfying the constraints as described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A routing method satisfying a constraint, comprising the steps of:
reading the wiring parameters, acquiring grid data and constraint of the wiring layer, and constructing a wiring grid;
setting a wiring starting node, and adding the starting node into a priority queue;
searching a wiring path, expanding nodes of a priority queue according to a low-cost sequence to a high-cost sequence, and pressing the expanded nodes into the priority queue;
and inquiring the expansion area to generate a wiring path which accords with the design rule.
2. The routing method satisfying the constraints as claimed in claim 1, wherein the step of reading routing parameters, obtaining grid data and constraints of the routing layer, and constructing the routing grid further comprises adding grid data parallel to the preset direction to the grid according to the information of the pins.
3. The routing method satisfying the constraint of claim 1, wherein the step of setting a routing start node further comprises,
taking nodes on the same layer and nodes inside the pins as initial nodes of the pins;
the node on the same layer is the middle point of the pin frame;
the nodes in the pins are the intersection points of the horizontal central line and the vertical central line of the rectangle and the grids, and do not contain points on the frame.
4. The method of satisfying a constraint according to claim 1 wherein the step of searching for a routing path to expand nodes in a priority queue in cost order further comprises,
and performing same-layer expansion on the nodes of the pin frame, and performing layer-skipping expansion on the nodes in the pin.
5. The routing method according to claim 4, wherein the step of querying the expansion region and generating the routing path that meets the design rule further comprises querying whether the generation metal line at the current position violates the design rule when the start node of the frame expands in the specified direction, and if so, increasing the cost value of the expansion node.
6. The routing method according to claim 4, wherein the step of querying the expansion region to generate a routing path that meets the design rule further comprises generating rectangles of top metal, bottom metal and via layer according to the via parameters when the nodes inside the pins perform layer-skipping expansion, querying whether the design rule is violated in the rectangular regions of the top metal, bottom metal and via layer, and if so, increasing the cost value of the expansion nodes.
7. The routing method according to claim 1, wherein the step of querying the expansion area to generate a routing path that meets the design rule further comprises the steps of directly connecting a metal line to a pin in the routing result, wherein a start node of the metal line is located at a midpoint of a frame of the pin, and when the metal line is vertical, the routing width is a width of a pin pattern; when the metal lines are horizontal, the wiring width is the height of the pin pattern.
8. The wiring method satisfying the constraints as claimed in claim 1, wherein the step of querying the expansion area to generate the wiring path that meets the design rule further includes that the via in the wiring result is connected to the pin, the first segment of metal line connected to the via satisfies the design rule constraint between the pattern of the via on the layer where the metal line is located and the first segment of metal line, and when the first segment of metal line is vertical, the wiring width is the width of the via pattern; when the metal lines are horizontal, the width of the wiring is the height of the via pattern.
9. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to perform the steps of the wiring method satisfying the constraints according to any one of claims 1 to 8.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program executes the steps of the method of wiring satisfying the constraints of any one of claims 1 to 8 when running.
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Cited By (1)
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