CN111027275A

CN111027275A - Pin connection preprocessing method meeting minimum groove constraint

Info

Publication number: CN111027275A
Application number: CN201911317655.0A
Authority: CN
Inventors: 柏晞琼; 张亚东; 陈建利; 李起宏; 陆涛涛; 刘伟平
Original assignee: Huada Empyrean Software Co Ltd
Current assignee: Huada Empyrean Software Co Ltd
Priority date: 2019-12-19
Filing date: 2019-12-19
Publication date: 2020-04-17

Abstract

A pin connection preprocessing method satisfying minimum recess constraints includes the following steps: 1) obtaining all pin graphs in a wire net; 2) creating obstacles at the convex and/or concave corners of the pin pattern; 3) and selecting the pin connection position and direction which accord with the design rule for wiring. The pin connection preprocessing method meeting the minimum groove constraint can quickly analyze the special pin structure needing to be processed before wiring begins, solve the problem that the pin connection in the layout wiring violates the design rule constraint of min notch, save later correction design rule violation time, provide a corresponding solution and improve the wiring quality.

Description

Pin connection preprocessing method meeting minimum groove constraint

Technical Field

The invention relates to the technical field of EDA (electronic design automation) design, in particular to a pin connection preprocessing method meeting the minimum groove constraint.

Background

With the increasing demand of ultra-deep submicron technology, the back-end physical design in the integrated circuit design flow becomes more and more complex, so that applying EDA (electronic design automation) tools becomes an indispensable auxiliary means for the back-end physical design. As the wiring stage of the physical design of the very large scale integrated circuit needs to meet a plurality of design rule constraints while connecting the geometric figures of the circuit netlist, and the increasing process requirements lead to more and more new design constraints to be required to be met, thereby increasing the complexity of the wiring stage. One of the basic goals of the mainstream layout wiring tool of today is to automatically and rapidly generate the wire mesh pattern connection meeting the requirements of the design rule, and the violation of the design rule on the layout during the connection process can make the chip unable to be delivered to the manufacturing. Therefore, no design rule violation is a fundamental requirement of layout wiring design.

A typical router automatically performs physical connections (connections of geometric figures) to a netlist (net set) of circuits on a layout. Since the geometry in a circuit netlist is usually composed of pin patterns, the generated physical connections include metal lines in the same layer, and different metal layers are connected through vias. While physical connections are being generated, the metal wiring layers and via layers that pass through the layout need to meet the requirements of numerous design rules. Such as minimum spacing constraints between different nets or between a net and an obstacle, minimum spacing constraints between adjacent vias of the same net or different nets in the same via level, minimum footprint constraints for the nets to meet a metal block, etc. When routing a single net, the metal lines or vias connecting the pins often encounter problems that violate minimum pitch constraints and minimum footprint constraints.

Due to the increasing demands of the wiring stage of the vlsi design, the size of the nets is becoming larger and larger, the number of pins in the nets is increasing, and the shapes of the pins in the nets are also changing from a single geometric figure to a complex geometric figure. It becomes important how to quickly obtain an effective (meeting design rule requirements) connection point from the pin for routing or via-punching. If the design rules are not considered at first and the connection points of the pins are randomly obtained, a large number of unnecessary design rule violations are generated near the generated physically connected pin connection points, and then the actual effect of the wiring of the whole layout is greatly influenced by amending the design rule violations in an interim.

Disclosure of Invention

In order to solve the defects of the prior art, the invention aims to provide a pin connection preprocessing method meeting the minimum groove constraint, and in the layout wiring process, rectangular obstacles with the width and height of min notch (minimum groove) can be created at the convex or concave corners of all pins before wiring. So that the routing of the connection pins meets the design min notch geometric constraints.

In order to achieve the above object, the present invention provides a pin connection preprocessing method satisfying minimum recess constraint, comprising the steps of:

1) obtaining all pin graphs in a wire net;

2) creating obstacles at the convex and/or concave corners of the pin pattern;

3) and selecting the pin connection position and direction which accord with the design rule for wiring.

Further, the step 1) further comprises analyzing and acquiring the pin pattern needing to be preprocessed.

Further, the step 3) further includes wiring to avoid the position of the obstacle.

Further, the width and height of the obstacles are the minimum spacing.

Further, the nets may comprise a single net or a multiple net.

To achieve the above object, the present invention also provides a computer readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the pin connection pre-processing method satisfying the minimum recess constraint as described above.

In order to achieve the above object, the present invention further provides a wiring device satisfying the constraints, including a memory and a processor, where the memory stores computer instructions running on the processor, and the processor executes the computer instructions to execute the steps of the pin connection preprocessing method satisfying the minimum recess constraints as described above.

The pin connection preprocessing method meeting the minimum groove constraint has the following beneficial effects:

1) all special pin structures that need to be processed can be quickly analyzed before starting the wiring and a corresponding solution is provided.

2) The problem that the pin connection in layout wiring violates the design rule constraint of min notch can be successfully preprocessed, and later-period correction design rule violation time is saved.

3) The pin connection min notch design rule constraint is met, and the wiring quality is improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a flow chart of a pin connection pre-processing method that satisfies minimum recess constraints in accordance with the present invention;

FIG. 2 is a pin diagram according to the present invention;

FIG. 3 is a schematic diagram of creating obstacles at corners of a pin pattern according to the present invention;

FIG. 4 is a schematic view of a wiring process layer setup interface according to an embodiment of the invention;

FIG. 5 is a diagram illustrating a final routing result generated according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating a layout result after changing the position and shape of a pin pattern according to an embodiment of the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

In the embodiment of the invention, the complex pin graphs of a single net are used for processing and analyzing, and the following pin connection point processing method for a multi-net is similar.

Fig. 1 is a flowchart of a pin connection preprocessing method satisfying the minimum recess constraint according to the present invention, and the pin connection preprocessing method satisfying the minimum recess constraint of the present invention will be described in detail with reference to fig. 1.

First, in step 101, all pin patterns in the net are obtained, and the pin structures to be processed are found.

In step 102, a wiring process layer is provided.

In the embodiment of the invention, the values of the line width and the minimum distance of the wiring process layer are set.

At step 103, rectangular obstacles are created at the corners of the pin pattern that are at a minimum pitch in width and height. In this step, rectangular obstacles with minimum spacing in width and height are created at all its convex or concave corners for these pin patterns.

At step 104, the pin connection locations and directions that meet the minimum pitch design rules are selected for routing.

In this step, after the preprocessing is completed, the pin connection position and direction which do not generate the min notch DRC (minimum pitch design rule check) are automatically selected during wiring.

A pin connection preconditioning method that satisfies minimum recess constraints in accordance with the present invention is further described below in conjunction with an exemplary embodiment.

(1) A wiring command is initiated and wiring parameters are set. Fig. 4 is a schematic diagram of a layout process layer layout interface according to the present invention, and values of line width and minimum pitch associated with the layout of the corresponding metal layer are set as shown in fig. 4. In this embodiment, a Multi-layer Point to Point Router (Multi-layer Point to Point Router) command is started in the Aether tool, and a routing parameter is set in a corresponding page.

(2) Two pins that need to be routed are selected, creating an obstacle.

In the embodiment of the invention, two selected pins needing to be subjected to wiring operation are shown in FIG. 2; the obstacles created at the corners of the pin pattern are shown in fig. 3.

(2) Routing is performed among the pins, and as the routing result is shown in fig. 5, since the first pin pattern has a concave corner, and the starting pin connection point transversely and directly leads out the routing result to violate the min notch constraint, after an obstacle is created at the corner, the routing avoids the directly leading out connection line, thereby ensuring that the generated routing result meets the constraint of the min notch.

FIG. 6 is a schematic diagram of the routing result after changing the position and shape of the pin pattern according to the present invention, as shown in FIG. 6, when both pin patterns have reentrant corners, the routing result indicates that our method meets the design requirement and generates the routing result without violating the min notch constraint.

The invention provides a pin connection preprocessing method meeting min notch constraint. The method defines the illegal region of the pin connection violating the min notch constraint as an obstacle, can quickly analyze all special pin structures needing to be processed before starting wiring, and provides a corresponding solution, thereby ensuring the satisfaction of the pin connection min notch design rule constraint and improving the wiring quality.

To achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed, performs the steps of the pin connection pre-processing method satisfying the minimum recess constraint as described above.

In order to achieve the above object, the present invention further provides a wiring device satisfying the constraints, comprising a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the computer program to execute the steps of the pin connection preprocessing method satisfying the minimum recess constraints as described above.

Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A pin connection preprocessing method meeting minimum groove constraints is characterized by comprising the following steps of:

1) obtaining all pin graphs in a wire net;

2) creating an obstacle at a convex or concave pin corner of the pin pattern;

2. The method of pin connection pre-processing satisfying minimum recess constraints as set forth in claim 1, wherein the step 1) further comprises analyzing and obtaining the pin pattern to be pre-processed.

3. The pin connection preconditioning method that satisfies the minimum recess constraint of claim 1, wherein the step 3) further comprises routing away from the location of the obstacle.

4. The pin connection preconditioning method of satisfying minimum recess constraints of claim 1, wherein the width and height of the obstacles are a minimum pitch.

5. The method of pin connection preconditioning of claim 1, wherein the wire meshes comprise a single wire mesh or a multiple wire mesh.

6. A computer readable storage medium having computer instructions stored thereon, wherein the computer instructions when executed perform the pin connection pre-processing method steps of any of claims 1 to 5 that satisfy minimum recess constraints.

7. A wiring device satisfying constraints, comprising a memory and a processor, the memory having stored thereon computer instructions for execution on the processor, the processor executing the computer instructions to perform the steps of the pin connection pre-processing method satisfying minimum recess constraints as recited in any one of claims 1 to 5.