JPH0467243A - Data processor - Google Patents

Abstract

PURPOSE:To obtain a high-speed data processor by providing an illicit address bit on an address conversion buffer. CONSTITUTION:A logical address LMA generated by an address generating part 3 serves as an entry address of an address conversion buffer 4. A tag part 8 read out by the entry address is compared with the address LMA by a comparison part 10. When the coincidence is secured in the comparison, a coincidence signal HIT becomes significant. Then the output of a real address part 9 of the entry address is outputted as it is to a main storage 2 as a physical address PMA. Meanwhile the reference is applied to an address conversion table if no coincidence is obtained between the contents of the part 8 and the address LMA. When the converted physical address is larger than the capacity of the storage 2, an illicit address bit 11 is set. Thus the address limit error processing is started by a control part 5 when the bit 11 is set, that is, a limit address is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to speeding up detection of address limits in memory access of a data processing device.

(Prior Art) FIG. 3 is a block diagram of a conventional data processing device.
1) is the basic processing unit, (2) is the main memory, (3) is the address generator, (4) is the address translation buffer, (5)
is a control unit, and (6) is an address comparator.

Next, the operation will be explained. The main memory (2) holds the instructions and data that the basic processing unit (1) needs, and the basic processing unit (1) needs the instructions and data that the main memory (2) holds. Then, address generation part (3)
The address of the instruction word or data is generated. Since the address generated by the address generator (3) is a logical address, it is converted into a physical address by the address translation buffer (4). The physical address is the main memory (2)
This is the memory address to be sent to and referenced. At this time,
The physical address is compared with the maximum address value MAX of the memory array of the main storage device (2) itself by the comparison unit (6). As a result of the comparison, if MAX is larger than the physical address, the memory access ends normally. On the other hand, as a result of the above comparison, if the physical address is large, the invalid address bit part of the address over detection signal is made significant to inform the control unit (5) that an impossible physical address has been pressed into the address translation buffer (4). When the invalid address bit part of the address over detection signal becomes significant, the control unit (5) performs thorough error processing.

Further, FIG. 4 is a more detailed block diagram of the address translation buffer (4) in the configuration example of the conventional data processing device. In the figure, (7) is a passing section that randomizes all or some bits of a logical address using an appropriate hashing function, (8) is a tag section that holds a logical address that is the target of address translation, and (9) is a The real address section (10) that holds the physical address after address conversion is a comparator that compares the logical address LMA with the contents of the tag section (8).The tag section (8) and the real address section (9) are It is composed of a memory array, and the output of the hashing section (7) becomes the entry address of the memory array.

The address translation buffer (4) is configured to hold a copy of a part of the address translation table used in the data processing device as a combination of a tag and a real address, and when given a logical address LMA from the address generation unit (3), Specify the entry address of the hashing section (7), tag section (8), and real address section (9). The content of the tag part (8) of the entry address is the logical address LM.
If they match, the match signal 1 (IT) becomes significant, and the pressure in the real address part (9) of the entry address is output as is as the physical address PMA.

On the other hand, when the logical address LMA and the contents of the tag part (8) do not match, the contents of the real address part (9) are not used.
After referring to the address conversion table anew and updating the contents of the tag section (8) and real address section (9), the above address conversion process is performed again.

(Problem to be Solved by the Invention) Since the conventional data processing device is configured as described above, the address limit cannot be detected until after the address translation by the address translation buffer (4) is completed. As a result, the detection of the address limit is delayed, which ultimately becomes a factor that hinders the performance improvement of the data processing device as a whole.

Furthermore, Japanese Patent Laid-Open No. 59-87566 discloses a process of recording a program event by attaching information to each element of an address translation buffer to identify whether or not the memory area includes an access detection target area. Publication No. 63-247852 has various flags in the address translation buffer,
Although each document describes how to improve the efficiency of error detection, it does not mention flags related to address limit checking and detection. Furthermore, JP-A-1-1978
Publication No. 44 states that the address translation buffer has a flag indicating that the address limit has been changed, and if the flag is set when referring to the address translation buffer, the address limit is checked again.
There is nothing written about holding the address limit check result as a flag in the address translation buffer.

This invention has been made in view of the above points, and provides a data processing device in which the address limit check result is stored in the address conversion buffer as a flag, and the address limit can be detected at the same time as the address conversion process by the address conversion buffer. The purpose is to

[Means for Solving the Problems] A data processing device according to the present invention includes an address translation buffer that holds a copy of a part of the contents of an address translation table and converts a logical address generated by an address generation unit into a physical address. In the data processing device that sends the physical address to the main storage device as the address of the memory to be referenced, the logical address information, the physical address information corresponding to the logical address information, and the physical address are stored in the address translation buffer. The apparatus is provided with means for holding illegal address information indicating whether or not the address is larger than the capacity of the main storage device, and also includes a control section that starts illegal address processing based on the illegal address information.

(Operation) In this invention, when the registered physical address is larger than the capacity of the main storage device when updating the address translation buffer, that information is registered in the invalid address information holding section in the address translation buffer together with the registered physical address, and The specified physical address is read simultaneously when it is used, triggering address limit error handling.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

The same parts as in Figures 3 and 4 are designated by the same reference numerals.
In Figure tS1 and Figure 2, (1) to (5) (7) to (
10) is the same as the conventional one, and (11) is provided in the address translation buffer (4) together with the tag part (8) and the real address part (9), and the physical address is stored in the main memory (2).
), and when this invalid address bit (11) is set, appropriate limit address error processing is activated by the control unit (5). It is designed so that

Next, the operation will be explained. The logical address LMA generated by the address generation unit (3) is processed by the hashing unit (7).
) and becomes the entry address of the address translation buffer (4). The tag part (8) read by the entry address is compared with the logical address LMA by the comparison part (10), and if they match, a match signal is sent) II
T becomes significant, and the output of the real address part (9) of the entry address is output as is to the main storage device (2) as the physical address PMA. At this time, the invalid address bit (11) is also read out at the same time. The output signal of the invalid address bit (11) The invalid address bit part is controlled by the control unit (
5), and if the invalid address bit section signal is significant, the control section (5) activates appropriate limit address error handling.

On the other hand, if the content of the tag part (8) read by the entry address does not match the logical address LMA, the address translation table is referred to, and the logical address is stored in the tag part (8) as the translated physical address. is stored in the real address field (9), and when the converted physical address is larger than the capacity of the main storage device (2), the invalid address bit (
11) is set.

In this manner, when the invalid address bit (11) is set, that is, when a limit address is detected, address limit error processing is activated by the control unit (5).

[Effects of the Invention] As described above, according to the present invention, since an invalid address bit is added to the address translation buffer, a limit address can be detected directly from a logical address without using the physical address after address translation, and the A high-speed data processing device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data processing device according to an embodiment of the present invention, FIG. FS2 is a more detailed block diagram of the address translation buffer in the embodiment of FIG. Block Diagram FIG. 4 is a more detailed block diagram of an address translation buffer in a conventional data processing device. In the figure, (1) is a basic processing unit, (2) is a main memory, (3) is an address generation unit, (4) is an address translation buffer, (5) is a control unit, (6) is an address comparator, (
7) is a hashing section, (8) is a tag section, (9) is a real address section, (10) is a comparison section, and (11) is an invalid address bit section.

Claims (1)

[Claims] An address translation buffer is provided that holds a copy of a part of the contents of the address translation table and converts the logical address generated by the address generation unit into a physical address, and sends the physical address to the main storage device to address the memory to be referenced. In the data processing device, the address translation buffer holds logical address information, physical address information corresponding to the logical address information, and invalid address information indicating whether the physical address is larger than the capacity of the main storage device. What is claimed is: 1. A data processing device comprising: a control section for activating fraudulent address processing based on the fraudulent address information;