JPH02250173A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate a need of the invalidation processing of block data and to reduce the amount of hardware by limiting requests of access to a buffer storage part on non-arranged data requests. CONSTITUTION:A scalar request 101 outputted from a scalar request generating circuit 4 is inputted to an arrangement area check circuit 10. The access address is compared with addresses A and B set to an arrangement storage area address register 7 by a comparator 8 to discriminate whether the scalar request 101 requests the access to arranged data or non-arranged data by an arrangement and non-arrangement discriminating circuit 9. The scalar request is outputted as an arranged data request 103 to a main storage part 3 when requesting arranged data, and the scalar request is outputted as a non-arranged data request 102 to a buffer storage part 2 when requesting the access to non- arranged data. A vector request is generated by a vector request generating circuit 5 and is outputted to the main storage part 3. Thus, the invalidation processing of block data is unnecessary to reduce the amount of hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly, to a main memory section, a buffer memory section for storing a copy of data stored in the main memory section, and a system for generating scalar requests and vector requests. The present invention relates to an information processing device including a data processing unit.

A conventional method of storing data in the main memory and accessing data to the buffer memory will be described with reference to FIG. The data processing unit 1 outputs a scalar request (referred to as a scalar load request or a scalar store request) created by the scalar request creation circuit 4 to the storage unit 2 . In addition, a vector request 205 created by the vector request creation circuit 5
(referred to as a vector request or a vector store request) is output to the main storage unit 3.

However, when the data processing unit 1 outputs a vector store request to the main storage unit 3, a copy of the block data in the main storage unit 3 including the data to be updated by the vector store request is stored in the buffer memory hidden unit 2. If it is registered, it is necessary to invalidate the block data in the buffer storage unit 2. Therefore, the vector request generation circuit 5 also outputs the vector request 202 to the vector area check circuit 6, the vector area check circuit 6 analyzes the vector store request, and outputs a block data invalidation request 204 to the buffer storage unit 2. be done. When the block data invalidation request 204 is input, the buffer storage unit 2 performs invalidation processing on the corresponding block data.

When a scalar request 201 is output from the scalar request generation circuit 4 without waiting for the end of this block data invalidation process, the vector area check circuit 6 determines whether or not the access is to block data that should be invalidated, and the request is not invalidated. If block data is accessed, a scalar request 203 is output to the buffer storage unit 2. When accessing block data to be invalidated, the output of the scalar request 203 to the buffer storage unit 2 is as follows:
It is suppressed until the end of block data invalidation processing.

Therefore, all scalar requests 1 through are outputted to the g-plane storage unit 2 via the vector area check circuit 6.

In the conventional information processing device described above, when a vector store request is output from the data processing unit to the main storage unit, the block data in the main storage unit containing the data to be updated by the request is If a copy of the block data is registered in the buffer memory, the corresponding block data in the buffer memory is invalidated, and if a scalar request is created while block data is being invalidated, it is determined whether the block data to be invalidated is accessed or not. Since it is necessary to make a judgment, it has the disadvantage that a large amount of hardware is required for this purpose.

Purpose of the Invention Therefore, the present invention has been made to solve the drawbacks of the conventional ones, and its purpose is to eliminate the invalidation processing of block data in the buffer storage section and improve the hardware. An object of the present invention is to provide an information processing device with a reduced amount of hardware.

Structure of the Invention According to the present invention, there is provided an information processing device including a main memory, a buffer memory that stores a copy of data stored in the main memory, and a data processing unit that generates a scalar request and a vector request. an area holding means for storing array data in a predetermined area of the main memory section, and holding an array data storage area without indicating the predetermined area; determination means for determining whether or not the request is within the array data storage area, and when the determination result indicates that the request is within the array data storage area, the scalar request is supplied to the main storage unit. However, when this is not the case, there is obtained an information processing apparatus characterized in that the information is supplied to the buffer storage section.

Example Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram without showing a solid line example of the present invention;
Parts that are equivalent to those in the figure are indicated by the same reference numerals.6 In the present invention, the array data requested by the vector request generation circuit 5 is not stored in the buffer storage unit 2 but is entirely stored in the main storage unit 3. It is.

Therefore, when compiling the program, the main memory storage area for data declared as array data in the program is determined in advance from addresses A to B.

When executing a program, first the array area check circuit 10
Address A and address B are set in the array storage area address register 7 of . The scalar request 101 output from the scalar request creation circuit 4 is input to the array area check circuit 11810, and the access address is compared with the addresses A and B set in the array storage area address register 7 in the comparator 8. As a result, the array/non-array determination circuit 9 determines whether the scalar request 101 is an access to array data or non-array data.

If the access is to array data, it is output to the main storage unit 3 as an array data request 103, and if it is an access to non-array data, it is output to the M-plane storage unit 2 as a non-array data request 102. The vector request is only created by the vector request creation circuit 5 and output to the main storage unit 3. This is because the array data required by the vector request is not stored in the buffer storage unit 2 in the same amount, so an invalidation request for the data is not required.

As explained above, according to the present invention, by limiting requests to access the buffer memory to non-array data requests, vector store requests are output from the data processing unit to the main memory. At this time, a process is performed to determine whether the block data registered in the buffer memory is a copy of the block data in the main memory that includes the data updated by the vector store request, and to invalidate the block data. Since this is no longer necessary, the effect is that the amount of hardware required for this purpose can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram not showing the prior art. Explanation of symbols of main parts 1... Data processing unit 2... Buffer storage unit 3... Main storage unit 4... Scalar request creation circuit 5... ...
・Vector request creation circuit 7... Array data storage area register 8... Comparator 9... Array/non-array determination circuit

Claims (1)

[Claims] (1) An information processing device that includes a main memory section, a buffer memory section that stores a copy of data stored in the main memory section, and a data processing section that generates a scalar request and a vector request. an area holding means for storing array data in a predetermined area of a storage unit, and holding an array data storage area indicating the predetermined area; determination means for determining whether the request is within the array data storage area, and when the determination result indicates that the request is within the array data storage area, the scalar request is supplied to the main storage unit; otherwise, the scalar request is supplied to the buffer. An information processing device characterized by supplying information to a storage section.