JPH0283750A - Information processor - Google Patents

Abstract

PURPOSE:To easily obtain the executing information necessary for debugging jobs by providing a register which designates a program area to be recorded, an address comparator, an information memory, a word length memory for executed instructions, and an adder which produces the addresses of both memories. CONSTITUTION:The upper and lower limit registers 5 and 6 designate the instruction address areas of a program which records the history information. A comparator 7 decides the address areas designated by the registers 5 and 6. An adder 8 adds 1 every time an information processor 1 carries out an instruction. An information memory 3 has a recording area of a flag which identifies whether the relevant instruction is equal to a branch instruction or not and whether a program instruction is produced or not. Then the processor 1 compares and decides the addresses with each other in an instruction address area for each execution of an instruction and designates an address with the output of an adder 8 within a designated area. Then the history information and the instruction word length are recorded to the memories 3 and 4 respectively for each execution of an instruction. In such a constitution, the generation of an interruption and the failure of branch can be identified. Thus the availability of the memory part is improved and a program can be extended. Furthermore the instruction word length is easily decided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing apparatus that efficiently records history information of programs processed within the information processing apparatus.

[Conventional technology]

Conventionally, as a function for recording program history information, as described in Japanese Patent Laid-Open No. 59-161751, upper and lower limit address registers are used to specify the recording target area of the program, the actual execution instruction address and the upper and lower limit addresses. It is equipped with a register comparison circuit and a memory section that records the history information of the corresponding instruction corresponding to the instruction address.When an instruction in the recording target area is executed, the memory section records whether the corresponding instruction was executed, not executed, branched successfully, or failed. There is a method of recording and executing a flag that identifies success.

[Problem to be solved by the invention]

When a program interrupt occurs while executing an instruction in a program for which history information is to be recorded, the instruction execution information of the program interrupt generating instruction is divided into cases where it is recorded and cases where it is not recorded, depending on the cause of the program interrupt. In such a case, in the conventional technology, when a program interrupt occurs and instruction execution information is recorded, it is necessary to check whether the executed instruction terminated normally or whether a program interrupt occurred but was recorded as an instruction execution. It is not possible to determine whether or not. In the case where a program interrupt occurred and instruction execution information was not recorded, the previous instruction was a branch instruction and the branch was successful and the corresponding instruction was recorded as unexecuted. It is not possible to determine whether execution information was not recorded or not. In addition, in the prior art, when a branch instruction is executed, a case of branch failure is recorded as an instruction execution, so it is necessary to check whether an instruction other than the branch instruction was executed and recorded as an instruction execution. It is not possible to identify whether this is a branch failure case or not. In addition, in the conventional technology, since each instruction has flags of 2 bits 1 to 1 for identifying executed/unexecuted instructions and successful/unsuccessful branching as history information, the lower limit of the program area to be recorded is ~If the answer is L, the address in the memory section where the flag is recorded is L10, L-1-2, L+4...
・L+1 in the next memory section. , T-7+37-7+5
The area indicated by the address . . . becomes unused. Also, if the instruction at the lower limit address L is a 4-high l- instruction, when this instruction is executed, the 2-hi I flag is recorded in the memory section for the first 2 hides, and nothing is written for the latter 2 hides. Not recorded. In other words, L+O in the memory section
A flag of 2 pips 1- is recorded in the area, and the area at address L+2 becomes unused. Similarly, if the instruction at the lower limit address L is a 6-high I instruction, 2 bits' for the first 2 bytes 1~
The flag of TS1- is recorded. In other words, 1. A flag of 2 pits 1~ is recorded in the area of address 10,
The area at address L+2 and 1. The area at address +4 becomes unused. As described above, the prior art has a drawback in that the memory section for recording history information cannot be used efficiently. Furthermore, in the prior art, the instruction word length of the executed instruction is 4.
There is a drawback in that when the instruction word length is determined, the identification flag recorded in the memory section must be stored and the length of the instruction word must be determined based on the identification flag recorded in the memory section. An object of the present invention is to eliminate the above-mentioned conventional drawbacks, efficiently use the memory section for recording history information, enable confirmation of events I~ that occur during program execution, and enable program execution necessary for program depacking. The objective is to realize a function that allows information to be easily collected.

[Means to solve the problem]

When a program interrupt occurs during the execution of an instruction in a program to be recorded, depending on the cause of the program interrupt, there are cases in which the execution information of the relevant instruction is recorded and cases in which it is not recorded. In other words, they are distinguished by the instruction execution state until the program interrupt factor occurs. Therefore, a block diagram interrupt generation instruction identification flag is provided to identify whether an instruction has a possibility of generating a program interrupt or not.
We believe that this problem can be solved by providing a program interrupt occurrence identification flag that identifies whether a program interrupt has occurred when the instruction is executed.

If a branch fails when executing a branch instruction, the same information as when an instruction other than a branch instruction is executed is recorded, so whether the branch instruction was executed and the branch failed or not is recorded.
It is not possible to determine whether an instruction other than a branch instruction has been executed.

I believe that this problem can be solved by providing a branch instruction identification flag that identifies whether or not the executed instruction is a branch instruction. In order to efficiently use the memory section for recording history information, it is considered that it is sufficient to use the memory area that is an unused section in the conventional technology. In other words, instead of recording history information in units of instructions 2 by 1 as in the conventional technology, the start address of the program area where history information is to be recorded is set as the start address. By preparing an adder that adds 1- to 1-by-1, generating continuous addresses, and recording history information in the continuous recording area in the memory section indicated by these addresses, memory areas that were previously unused can be used. I think it can be solved. Further, a memory section is provided for recording the instruction word length of the executed instruction, and the above-mentioned adder is used in combination,
By recording the instruction word length, the instruction word length of the executed instruction can be easily known.

[Effect]

When an instruction in a program area where history information is to be recorded is executed, it is determined based on the instruction code whether or not the executed instruction has a possibility of generating a program interrupt, and if there is a possibility that a program interrupt will occur, a program interrupt generation instruction identification flag is set. is set to 1 and written to the memory section. If a program interrupt occurs when this instruction is executed, the program interrupt occurrence identification flag is set to 1 and written into the memory section. As a result, a program interrupt occurs during instruction execution, and regardless of whether the instruction execution/non-execution identification flag is recorded due to the cause of the occurrence, the instruction can be detected by checking the 2-bit identification flag recorded in the memory section. It becomes possible to identify whether a program interrupt occurred during execution and instruction execution information was not recorded, whether the instruction ended normally, or whether the instruction remained unexecuted. When a branch instruction is executed, the branch operation instruction identification flag is set to 1 and recorded in the memory section. This makes it possible to identify whether or not a branch has failed after executing an instruction by checking the branch operation instruction identification flag in the memory section. Also, using the start address of the program area where history information is to be recorded as the first address, add one by one using an adder to generate continuous addresses, and record an identification flag in the memory section that records the history information indicated by this address. By doing so, it is possible to improve the usage efficiency of the memory section. In other words, if the start address of the program area where history information is to be recorded is L, then in the prior art, in order to record the identification flag in units of instruction 2 high I, L+O,L
+2. It was recorded in the memory area indicated by the address L+4... However, with L as the first address, this is 1
By using an adder that adds up L+O, L+1
．． By generating a continuous address such as L+2 and recording an identification flag in the memory area indicated by this address, previously unused areas can be used, increasing the efficiency of memory use and reducing the program area to be recorded. Can be expanded. In addition, by using this adder in combination with a memory section for recording the instruction word length, and recording the instruction word length, the instruction word length can be determined by checking the identification flag recorded in the memory section in the conventional technology. The length of the instruction word can be easily determined by checking the information recorded in the memory section dedicated to recording the length of the instruction word, and the length of the instruction word is stored in consecutive areas of the memory section indicated by consecutive addresses by the adder. By recording, it is possible to increase the usage efficiency of the memory unit and expand the program area to be recorded.

[Example] An example of the present invention will be described below with reference to the drawings. 1st
The figure shows a history information recording unit 100 according to the present invention connected to an information processing device 1.

The history information recording unit 100 has an upper limit address register 5. Lower limit address register 6 that specifies the lower limit address
, an address comparison circuit 7, and an information recording memory section 3 for recording history information. An instruction word length recording memory unit 4 for recording the instruction word length of an instruction executed by the information processing device 1. It is comprised of an adder 8 that generates recording addresses for the information recording memory section 3 and the instruction word length recording memory section 4.

The operation shown in FIG. 1 will be explained below. The information recording device 100 receives 4 bytes of the next instruction address of the instruction being executed by the information processing device 1 via path a. The next instruction address X is manually input to the address comparison circuit 7 in the path. The instruction address X input to the address comparison circuit 7 is compared with the upper limit address U and lower limit address L, which are set in the upper limit address register 6 and lower limit address register 5 as the program area to be recorded in advance, and L≦X≦U. When the conditions are met, a write permission signal is sent to the information recording memory section 3. The command word length recording memory unit 4 and write signal generation circuit 9 are inputted. The data recorded in the information recording memory section 3 is a branch success/failure identification flag for identifying branch success/failure at the time of a branch instruction from the information processing device 1 on the path Q.

An instruction execution/non-execution identification flag is used to identify whether an instruction has been executed or not executed on path m, a branch operation instruction identification flag is used on path 1 to identify whether an executed instruction is a branch operation instruction, and a protaram interrupt is generated on path σ. Program interrupt occurrence instruction identification flag for identifying whether a program interrupt has occurred during execution of an instruction on path f. Among the identification flags from 5 hino 1 to 5, the branch success/failure identification flag sent out on path Q and the instruction execution/non-execution discrimination flag sent out on path m are written in path/
The write signal generation circuit 9 uses the branch operation sentinel identification flag sent out at step 1 and the write permission signal sent out at path no. In other words, if the next instruction address of the actual execution instruction is X'h'XL≦X≦U, and the instruction is not an actual execution instruction or a branch operation instruction, a write signal is sent on the path r, and the instruction is sent out on the path In. An execution/non-execution identification flag is recorded in the information recording memory section 3. If the next instruction address of the actual execution instruction is X or 1-1≦X≦U, and the actual execution instruction is a branch operation instruction, a write signal is sent on path l,
The branch success/failure identification flag sent on route a is recorded in the information recording memory section 3. 5 Branch operation instruction identification flag/path sent out on path l among the identification flags to hit I. The program interrupt generation instruction identification flag sent out in path 7. The pronoram interrupt generation identification flag sent out in path 7. When the write permission signal sent in is issued, it is recorded in the information recording memory section 3.

The recording address in the information recording memory section 3 is determined by the adder 8. A signal instructing the start of information recording operation is issued from the information processing device through path P, and when this signal is issued, the second half of the next instruction address X input to the selector 11- is 0 manually entered in the selector 12 is selected. The next instruction address X when the signal instructing the start of the information recording operation is issued on the path 49 is the same as the lower limit address designated by the lower limit address register 5. In other words, the Y selected by the SEL node 1,000 is the latter half 2 high i- of the do limit address L. Selector 11
Y selected by - and O selected by selector 1-2
are manually inputted to the adder 8 at the path center and path S to perform the addition operation. The addition result Y is sent to the information recording device 3 via the path f.
The second half 2 bytes 1-Y of the next instruction address If the signal instructing the start of the information recording operation is not issued on the path 9, the Y input to the selector 1-1- on the path f and the 1 input to the selector 12 are
are selected and input to the adder 8 through the respective routes and routes A, and an addition operation is performed.

The addition result Y + 1- is transferred to the information recording memory section 3 via path f.
This becomes the recording address of the identification flag in the information recording memory section 3. In this way, the second half 2 bytes Y of the next instruction address By recording - in a continuous memory area, the information recording memory section 3 can be used efficiently.

The instruction word length recording memory unit 4 receives 3-bit information representing the instruction word length of an execution instruction from the information processing device 1 via a path, and stores the instruction word only when a write permission signal is issued via the path. The information of 3 pins 1- sent out via path 9 is recorded in the long recording memory section 4.

The instruction word length recording memory section 4 is recorded at the same address as the address at which the identification flag is recorded, as shown by the path f, by using the adder 8 as well. The information of 3hi which represents the instruction word length recorded in the meirei word length recording memory section 4 is shown in FIG.
Each byte instruction and 6-byte instruction are recorded in patterns. The contents of the information recording memory section 3 and the instruction word length recording memory section 4 are stored in the path Z7. It can be read out to the main storage device via the information processing device via path r.

Second. Third. Instruction execution can be identified by providing a branch operation instruction identification flag 3, a program interrupt generation instruction identification flag, and a program interrupt generation identification flag shown in FIG. Furthermore, by providing the 3-bit information representing the instruction word length of the executed instruction shown in FIG. 5 and the instruction word length recording memory section 4 shown in FIG. 1 for recording this information,
You can know the instruction word length of the executed instruction.

The first identification flag according to the present invention is shown in FIGS. 6 and 7.
- This is an example recorded in the information recording memory section 3 shown in the figure. L'
The contents of address 10 are identified as a case in which an instruction other than a program interrupt generation instruction was executed, and the contents of address L'+1 are identified as either an instruction that may cause a program interrupt was executed or a program interrupt did not occur. The contents of address L'+2 execute an instruction that may cause a program interrupt, and it is determined that whether a program interrupt has occurred or whether instruction execution information has been recorded. The contents of address L'+4 can be identified as a previous instruction or a branch instruction that resulted in a successful branch and the instruction was not executed. It can be determined that the contents of address L'+5 were not recorded because an instruction that could cause a program interrupt was executed and a program interrupt occurred. By providing the program interrupt occurrence instruction identification flag and the program interrupt occurrence identification flag in this way, it is possible to identify cases where a program interrupt occurs during instruction execution. Furthermore, the contents of address U'-4 and the contents of address U'-3 in Fig. 6 are conventionally recorded as instruction execution, but by using the branch operation instruction identification flag, the contents of address U'-4 can be changed. An instruction other than a branch action instruction is identified as being executed, and the contents of address U'-3 can be identified as a branch action instruction being executed and an unsuccessful branch.

In order to efficiently use the information recording memory section 4 for recording identification flags, the adder 8 shown in FIG. 1 is provided to generate continuous addresses by adding 1 to the first address, as shown in FIG. Record the identification flag in a continuous recording area.

FIG. 7 shows an actual recording example of the instruction word length recording memory section 4 shown in FIG. By using the adder 8 of FIG. 1 in combination with this memory section, information of 3 pips 1- representing the instruction word length shown in FIG. 5 is recorded in a continuous memory area.

〔Effect of the invention〕

According to the present invention, the following effects can be achieved.

1) Cases in which a program interrupt occurs during instruction execution and cases in which a branch fails during execution of a branch instruction, which could not be identified using conventional techniques, can be identified.

2) Record history information that was unused in conventional technology.
6. By using the area of the memory section, it is possible to improve the usage efficiency of the memory section and expand the program area to be recorded.

3) In the conventional technology, the instruction word length of the executed instruction could not be determined without checking the history information recorded in the memory section.
This can be easily determined by using a memory unit that records the instruction word length.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of identification flags used conventionally, FIG. 3 is a diagram illustrating an actual recording example of the prior art, and FIG. Fifth. FIG. 6 is a diagram illustrating the expression of the identification flag according to the present invention, and FIG. 7 is a diagram illustrating the expression of the three bits 1 to 1 representing the instruction word length recorded as BFfl information according to the present invention. 1. Information processing device, 2. Main storage device, 3. Information recording memory section, 4. Instruction word length recording memory section, 5. Lower limit address register, 6.. 2 limit address register, 7. Address comparison circuit, 8. Adder, 9. Write signal generation circuit, 10. Inverter, 11. Selector, 12.
- Selector, 100... History information recording section. Successful/unsuccessful Miyaya to L or L 7 Rakupa Figure 7-363=

Claims (1)

[Claims] 1. In a device that records history information of a program running in an information processing device, there are upper and lower limit address registers that specify the instruction address area of the program in which history information is to be recorded, and an address register that specifies the instruction address area of the program currently being executed.・A comparison circuit that determines whether or not it is within the area specified by the lower limit address register, an adder that adds 1 each time an instruction is executed, and a circuit that determines whether the corresponding instruction is a branch instruction or a program interrupt occurs each time an instruction is executed. Using an information recording memory section having an area for recording identification flags, each time the information processing device executes one instruction, the comparison circuit determines whether the instruction address is within the specified area, and whether or not the instruction address is within the specified area. An information processing apparatus characterized by having a function of using the value indicated by the output of the adder as an address and recording history information in the information recording memory specified by this address every time an instruction is executed.