JPS58225457A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPS58225457A JPS58225457A JP10906482A JP10906482A JPS58225457A JP S58225457 A JPS58225457 A JP S58225457A JP 10906482 A JP10906482 A JP 10906482A JP 10906482 A JP10906482 A JP 10906482A JP S58225457 A JPS58225457 A JP S58225457A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- address
- operating state
- working state
- storage circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Executing Machine-Instructions (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は情報処理装置、特に、記憶回路へのアクセスア
ドレスのエリアを動作状態に応答して設定できるような
情報処理装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to an information processing device that can set an access address area for a storage circuit in response to an operating state.
このような情報処理装置に、たとえば、指紋照合を行な
う情報処理装置がある。指紋照合は、ディスク装置にフ
ァイルされている過去の指紋データ(ファイル指紋)を
次々にメモリに書き込んで、メモリの他のエリアに書き
込まれた現在の指紋データ(サーチ指紋)と照合して行
なうが、ファイル指紋の書込みかサーチ指紋の書込みか
に応答して、メモリの書込みエリアを違えている。An example of such an information processing apparatus is an information processing apparatus that performs fingerprint verification. Fingerprint verification is performed by sequentially writing past fingerprint data (file fingerprints) stored in the disk device into memory and comparing them with current fingerprint data (search fingerprints) written in other areas of the memory. , the write area of the memory is changed depending on whether the file fingerprint or search fingerprint is written.
従来のこの種の情報処理装置は、動作状態を記憶する動
作状態記憶回路と、記憶回路へのアクセスアドレス保持
するアドレスレジスタとを備えている。A conventional information processing device of this type includes an operating state storage circuit that stores an operating state and an address register that holds an access address to the storage circuit.
このような従来構成においては、ファームウェアが動作
状態記憶回路の記憶内容を調べて、その結果に応答して
アドレスレジスタにセラトスべきアクセスアドレスを違
えているため、ファームウェアが繁雑であるという欠点
がある。Such a conventional configuration has the disadvantage that the firmware is complicated because the firmware checks the storage contents of the operating state storage circuit and changes the access address to be accessed in the address register in response to the result.
本発明の目的はファームウェアを簡略化した情報処理装
置を提供することにある。An object of the present invention is to provide an information processing device with simplified firmware.
本発明の装置は動作状態を記憶す不動作状態記憶手段と
、
記憶回路アクセスのためのアドレスを保持するアドレス
保持手段と、
前記記憶回路へのアクセス要求があると前記動作状態記
憶手段の記憶内容に応答して前記アドレス保持手段の保
持内容を修飾するアドレス修飾手段
とを設けたことを特徴とする。The device of the present invention includes: inactive state storage means for storing an operating state; address holding means for holding an address for accessing a memory circuit; and storage contents of the operating state storage means when an access request to the memory circuit is received. The present invention is characterized in that an address modification means is provided for modifying the contents held by the address holding means in response to the above.
次に本発明について図面を参照して詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.
第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
本実施例は動作状態記憶回路1と、アドレスレジスタ2
と、加算回路3と、記憶回路4とで構成されている。This embodiment includes an operating state storage circuit 1 and an address register 2.
, an adder circuit 3, and a memory circuit 4.
ファームウェアは情報処理装置の動作状態10を動作状
態記憶回路に記憶しておく。記憶回路4へのアクセス要
求があると、ファームウェアはアクセス用アドレス11
をアドレスレジスタ2にセラトスるが、このアクセスア
ドレス11は動作状態記憶回路1の記憶内容に拘らず同
じである。The firmware stores the operating state 10 of the information processing device in an operating state storage circuit. When there is a request to access the memory circuit 4, the firmware uses the access address 11.
is stored in the address register 2, but this access address 11 is the same regardless of the contents stored in the operating state storage circuit 1.
加算回路3は動作状態記憶回路1から修飾指示信号12
を受けないときは、アドレスレジスタ2の保持内容をそ
のま\記憶回路4に出力する。加算回路3が修飾指示信
号12を受けると、アクセス用アドレス11の上位2ビ
ツト13に、予め定められ九一定数を加算したうえで、
アクセス用アドレス11の下位ピット14とともにアク
セスアドレス15を形成して、記憶回路4に出力する。The addition circuit 3 receives the modification instruction signal 12 from the operating state storage circuit 1.
When not received, the contents held in the address register 2 are outputted as they are to the storage circuit 4. When the adder circuit 3 receives the modification instruction signal 12, it adds a predetermined nine constant number to the upper two bits 13 of the access address 11, and then
An access address 15 is formed together with the lower pit 14 of the access address 11 and output to the storage circuit 4.
本発明によれば、以上のような構成により、ファームウ
ェアは動作状態記憶手段の記憶内容に拘らず同じアクセ
ス用アドレスをアドレス保持手段にセットするだけでよ
くなるため、ファームウェアを簡略化できる。According to the present invention, with the above-described configuration, the firmware can be simplified because the firmware only needs to set the same access address in the address holding means regardless of the contents stored in the operating state storage means.
第1図は本発明の一実施例である。
1・・・・・・動作状態記憶回路、2・・・・・・アド
レスレジスタ、3・・・・・・加算回路、4・・・・・
・記憶回路、10・・・・・・動作状態、11・・・・
・・アクセス用アドレス、12・・・・・・修飾指示信
号、13・・・・・・上位ビット、14・・・第1図FIG. 1 shows an embodiment of the present invention. 1...Operating state storage circuit, 2...Address register, 3...Addition circuit, 4...
・Memory circuit, 10...Operating status, 11...
...Access address, 12...Modification instruction signal, 13...Higher bit, 14...Figure 1
Claims (1)
セスのためのアドレスを保持するアドレス保持手段と、 前記記憶回路へのアドレス要求があると前記動作状態記
憶手段の記憶内容に応答して前記アドレス保持手段の保
持内容を修飾するアドレス修飾手段 とを設けたことを特徴とする情報処理装置。[Scope of Claims] Operating state storage means for storing an operating state; address holding means for holding an address for accessing a memory circuit; and when an address request to the memory circuit is made, the storage contents of the operating state storage means are stored. An information processing apparatus comprising: address modification means for modifying the content held by the address holding means in response to the address modification means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10906482A JPS58225457A (en) | 1982-06-24 | 1982-06-24 | Information processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10906482A JPS58225457A (en) | 1982-06-24 | 1982-06-24 | Information processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58225457A true JPS58225457A (en) | 1983-12-27 |
Family
ID=14500676
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10906482A Pending JPS58225457A (en) | 1982-06-24 | 1982-06-24 | Information processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58225457A (en) |
-
1982
- 1982-06-24 JP JP10906482A patent/JPS58225457A/en active Pending
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