JPH0467192B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a driving device for a liquid crystal matrix display device, and particularly to a driving method suitable for active driving using active elements.

The basic principle of the active matrix drive method, in which individual liquid crystal pixels are driven in a matrix using active elements, has been filed by RCA.

(Japanese Patent Publication No. 1973-28117) On the other hand, many applications have been filed for specific applications, and one of the representative patent applications is
Explain 159493.

FIG. 1 shows an overall configuration diagram of the drive circuit. Each display element includes a MOS transistor 7, a storage capacitor 8, and a liquid crystal pixel 9.
It is composed of. Further, MOS transistor 7 and MOS transistor 6 are connected through a source line 14.

Horizontal shift register 4 and vertical shift register 5
generates a signal that turns MOS transistor 6 and MOS transistor 7 ON or OFF. These signals are then transmitted to the gate signal lines 12 and 1.
3 to each MOS transistor.

On the other hand, the timing signal generation circuit 3 outputs CKH, STH, CKV, and
STV and an M signal to be applied to the polarity selection circuit 2 are generated. The polarity selection circuit 2 described above has a liquid crystal pixel 9
The polarity of the video signal is switched for each field in order to drive the video signal with alternating current. A signal whose polarity has been inverted by the polarity inversion circuit 1 and the original signal are added to this circuit. Note that 10 is a common electrode terminal to which a constant potential is applied.

Next, the operation of these circuits will be explained using the timing diagram shown in FIG.

The STV signal and the CKV signal are timing signals for sequentially turning on the MOS transistors 7 line by line. Therefore, the number of pulses of the CKV signal during one field (1/60s) is
Equal to the number of 3 (m).

On the other hand, the CKV signal and the STH signal are timing signals that sequentially turn on the MOS transistor 6. Therefore, the number of pulses of the CKH signal within one horizontal scanning period is equal to the number (n) of gate lines 12.

For example, if the first line of the gate lines 13 is selected, all the MOS transistors 7 of the first line connected to it will be in the ON state,
On the other hand, the MOS transistors 6 are sequentially turned on at the timing of the CKH signal, and the video signal is written to the storage capacitor 8 and the liquid crystal pixel 9 in a time-division manner.

The above series of operations is performed in 1 field (1/60s)
Repeat each time.

Therefore, if we show the voltage applied to the liquid crystal pixel 9, the third
It will look like the figure. The voltage applied to one liquid crystal pixel has a waveform whose polarity is inverted every field. At this time, when not selected, the voltage attenuates with a time constant determined mainly by the storage capacitor 8, the capacitor _CLC of the liquid crystal layer, and the resistance _RLC of the liquid crystal layer.

By the way, in the conventional method, in order to increase the effective value of the voltage applied to the liquid crystal pixels and increase the contrast of the display, it is necessary to either increase the capacity of the storage capacitor 8 or reduce the leakage current of the liquid crystal.
Alternatively, there is a method of increasing the write voltage. Of these, storage capacitor 8
Increasing the write voltage causes problems in the IC process and is also disadvantageous in terms of yield. Furthermore, in order to reduce the leakage current of the liquid crystal, it is necessary to reduce the amount of impurities contained in the liquid crystal, which poses a problem during mass production.

An object of the present invention is to provide a drive method that achieves high contrast by increasing the effective value of the voltage applied to the liquid crystal pixels of a display device that drives a display signal input at a predetermined period, such as a video signal, in an active matrix manner. There is something to do. The feature of the present invention is to focus on the fact that the voltage applied to the liquid crystal pixels attenuates with almost the same time constant regardless of the voltage conditions, and to
A source signal output circuit that divides the screen into three or more screens and outputs the display signal as it is, and a storage/output circuit that temporarily stores and outputs the display signal, and outputs the output of the source signal output circuit to the divided screen. By providing a selection circuit that outputs the stored display signal to one of the screens and outputs the stored display signal to the remaining LCD screens, the effective voltage of the voltage applied to the liquid crystal element is increased and the display contrast is increased. This is due to the fact that the Examples of the present invention will be described below. FIG. 4 shows an example of the configuration of the present invention. Each display element is composed of a storage capacitor 23, a liquid crystal pixel 22, and a MOS transistor 21. Among these, one terminal 24 of the liquid crystal pixel 22 is set to a common potential. The source of each MOS transistor 21 is connected to the MOS transistor 1 by a source line 19.
It is connected to the drain terminal of 8. The source of the MOS transistor 18 is connected to a video signal line 25, and a gray-scale signal is applied thereto.

On the other hand, the vertical shift register 16 generates scanning signals L ₁ to L _{j that} sequentially turn on the MOS transistors 21 line by line, and passes them through the gate line 20.
Controls each MOS transistor. Further, the horizontal shift register 15 generates sampling signals C ₁ to _{C i} that sequentially turn on the MOS transistors 18 and controls each MOS transistor 18 through the gate line 17 .

In addition, the source video signal (source display signal) is
In the output circuit, the analog-to-digital conversion circuit (hereinafter referred to as A/D circuit) 30 converts it into a digital signal, and then inputs it to the buffer register 29, and the contents are input to the digital-to-analog conversion circuit (hereinafter referred to as D). /A circuit.) At step 28, the signal is again converted into an analog signal.

The source video signal and the output signal of the storage/output circuit are appropriately selected by the selection switch circuit 27a, and then sent to the polarity inversion circuit 26 and the selection switch 27b.
added to. This selection switch 27b is
a signal applied to the source of the MOS transistor 18;
That is, the polarity of the video signal sent to the signal line 25 is switched for each field.

Further, the timing circuit 31 generates a timing signal to each circuit section.

Here, the operation of the circuit shown in FIG. 4 is shown in FIG.
This will be explained using FIG. 6 as an example. Of these, in Fig. 6, the liquid crystal screen is divided into two blocks, A and B.
In the block, the liquid crystal pixels are numbered 1 to i in the horizontal direction and 1 to j/2 in the vertical direction, and the B block is numbered as follows:
Similarly, 1 to i in the horizontal direction and j/2+1 to j in the vertical direction
It is numbered.

On the other hand, FIG. 5 shows a buffer register 29 that stores information for one block of pixels shown in FIG.
Then, the addresses of the register are set as 1 to O in the horizontal direction and 1 to P in the vertical direction, and display information for one liquid crystal pixel is stored in each address. For example, when converting a video signal into a 4-bit digital quantity using the A/D circuit 30 shown in FIG. 4, a 4-bit quantized video signal is stored in each address of the buffer register 29. .

Next, the writing operation to the A and B screens will be explained. Assume that display information for screen B is now stored in the buffer register 29. In this case, the buffer register 29 stores the latter half of one field (=1/2 field) of the video signal.

First, the selection switch circuit 27a selects the source video signal and writes it directly to pixels 1, 1 (hereinafter displayed as e ₁ , ₁ ) on the A screen. When the above operation is completed, the selection switch circuit 27 selects the A/D circuit 2.
8 is selected, and the digital video signal stored in m _1,1 of the buffer register 29 is converted into an analog quantity and written to eb _j/2+1,1 on the B screen. When this is completed, write the information of e _1,1 to m _1,1 .

Next, after writing the source video signal to e _1,2 of screen A, the contents of m _1,2 are D/A converted and written to e _j/2+1,2 . After this, e _1,2 information is written to m _1,2 . These series of operations are performed up to e _j/2+1,i and e _j,i . As a result, the display information of the A screen is stored in the contents of the buffer register. This corresponds to the video signal of the first half of one field (1/2 field).

Next, the source video signal is directly written to e _j/2+1,1 of the B screen. When this is completed, the contents of the buffer register _m1,1 are written to _e1,1 on the A screen. After this,
Write the display information of e _j/2+1,1 to m _1,1 .

Then, write the source video signal directly to e _j/2+1,2 , and write the contents of m _1,2 to e _1,2 . And m _1,2
Write the display information of e _j/2+1,2 to.

These series of operations are performed up to e _j/2,i and e _j,i . As a result, e _j/2+1,1 ~e _j,i of screen B is displayed in the buffer register.
display information is stored. This corresponds to the video signal of the latter half of one field (1/2 field).

The operations described above are performed for each field. Figure 7 shows the situation at that time.

For example, when directly writing the first half of one field signal of the source video signal to the A screen, the contents of the buffer register are written to the B screen. Furthermore, when directly writing the second half of one field signal of the source video to the B screen, the contents of the buffer register are written to the A screen.

At this time, the selection switch circuit 27b switches the polarity of the video signal for each field.

FIG. 8 shows only the writing state of the source video signal of FIG. t _S time is one
This is the time when the MOS transistor 18 is selected. For example, in the first half of time t _S , e _1,1 appears on screen A,
Furthermore, in the second half, the source video signals are written to e _j/2+1,1 of the B screen, respectively.

FIG. 9 shows the timing of the signals shown in FIG. 4. to vertical shift register 16
Generates scanning signals L ₁ to L _j by adding STV and CKV signals, and turns on MOS transistor 21 for each line.
state. In this example, since the liquid crystal pixel is divided into two, L _o and L _j/2+o (where n=1, 2
...j/2) have the same timing, so the gate lines 20 of each block can be commonly connected.

The M signal is a switching timing signal for the switch 27b which inverts the polarity of the video signal for each field.

In addition, STH and CKV are added to the horizontal shift register 15.
generate sampling signals C ₁ to C _i by adding signals,
The MOS transistor 18 is turned on.
At this time, the video signal is switched by switching the switch 27a using the SL signal. Also, A/D
The video signal converted into digital by the circuit 30
It is written to the buffer register 29 at the rising timing of the SL signal.

As a result of the above, the voltage waveform applied to the liquid crystal pixel 22 becomes as shown in FIG. At t _a , t _d , and t _e the source video signal is applied directly to the liquid crystal pixels. Also, t _b ,
At _ts , the video signal stored in buffer register 29 is applied to the liquid crystal pixels. Note that even if the voltage level of the source video signal input to the circuit of this embodiment is constant, the voltage level at each time is not strictly constant, but this does not pose a problem in practice.

FIGS. 11 and 12 show other embodiments. Here, the screen is divided into 4 screens A, B, C, and D.
Divide the screen into screens and set the buffer register 29 to 1, 2,
It was divided into 3 blocks of 3.

The buffer register 29 stores 3/4 screen display information. Therefore, O=i, P3/4j.

FIG. 13 shows the timing of writing to the A, B, C, and D screens. First, if the source video signal is directly written to the A screen, the video signal stored in the buffer register 29 is written to the B, C, and D screens. In this case, each screen is written in a time-division manner within the time t _S shown in FIG. Also, the video signal of the A screen is written into the buffer register 29.

As a result, the video signals of screens A, C, and D are stored in the buffer register 29 at time _t1 .
Repeat this operation sequentially.

The video signals stored in each block of the buffer register are shown in FIG. 14. t ₁ , t _{2 .} . . are the same as t ₁ , t _{2 .} . . in FIG. 13. In other words, during the 1/4 field time of the video signal, the video signal is written directly to the liquid crystal pixel,
During the remaining 3/4 field time, the video signal stored in the buffer register is written.

FIG. 15 shows a voltage waveform applied to a liquid crystal pixel. At t _a , t _e , t _i the source video signal is written directly, and at t _b , t _c , t _d , t _f , t _g , t _h the video signal stored in the buffer register is written.

In this way, by writing multiple times within one field time of the video signal, the effective value of the voltage applied to the liquid crystal pixel can be increased.

Furthermore, in order to achieve the same effect as this embodiment, it is possible to divide the display screen into N parts and provide a buffer register for storing the display information of the N-1 screen. Furthermore, in this embodiment, it is assumed that the video signal is inputted in an analog quantity, but if the video signal is inputted in a digital quantity, a similar result can be obtained by using two D/A circuits 28 as shown in FIG. Effects can be obtained.

According to the present invention, since the effective voltage applied to the liquid crystal pixels can be increased, the display contrast can be increased.

Furthermore, since the storage capacitor connected in parallel with the liquid crystal pixels can be made smaller, the area required for this can be made smaller, making it possible to create a small display with a limited display screen.

Furthermore, since the voltage written to the liquid crystal pixels can be lowered, the withstand voltage of the semiconductor can be lowered, making it easier to integrate into LSI.

[Brief explanation of the drawing]

Figure 1 is a conventional circuit block diagram, Figure 2 is a conventional circuit block diagram.
3 is a voltage waveform diagram applied to the liquid crystal pixel in FIG. 1, FIG. 4 is a block diagram of the circuit of the present invention, FIG. 5 is an example of buffer register addressing, and FIG. Examples of display screen divisions, Figures 7 and 8
9 is a timing diagram of writing to the display screen, FIG. 9 is a timing diagram of FIG. 4, FIG. 10 is a voltage waveform diagram applied to a liquid crystal pixel, and FIG. 11 is an example diagram of addressing of buffer registers according to another embodiment. , Fig. 12 is an example of how the display screen is divided, Fig. 13 is a timing diagram for writing to the display screen, Fig. 14 is a diagram of the contents of the buffer register, Fig. 15 is a voltage waveform diagram applied to the liquid crystal pixels, and Fig. 16 is a diagram of the contents of the buffer register. is a circuit configuration diagram according to another embodiment. 15...Horizontal shift register, 16...Vertical shift register, 18, 21...MOS transistor, 22...Liquid crystal pixel, 23...Storage capacitor, 27...Selection switch circuit, 28...
D/A circuit, 29... Buffer register, 30...
...A/D circuit.

Claims (1)

[Claims] 1 Display elements consisting of active elements that switch input voltage and liquid crystal pixels whose voltage is controlled by these active elements are arranged in a matrix in the X-Y direction, and the entire display is divided into multiple areas. a divided liquid crystal screen; a scanning circuit section that applies a drive signal to turn on and off the active element; a signal circuit section that sequentially applies a display signal to the liquid crystal pixels via the active element; and the scanning circuit section and the signal circuit section. In a liquid crystal matrix display device, the signal circuit section includes a storage/output circuit that temporarily stores and outputs a source display signal, and the signal circuit section includes a storage/output circuit that temporarily stores and outputs a source display signal, and according to a signal from the control circuit, one field is displayed. A liquid crystal matrix display device, characterized in that the source display signal and the output signal from the storage/output circuit are output to the display element in a predetermined order within a time period. 2. The liquid crystal matrix display device according to claim 1, wherein the predetermined order is such that at least immediately after the source display signal, the output signal from the storage/output circuit is output. 3. In claim 1, while the signal circuit is outputting the source display signal to one of the divided liquid crystal screens, the signal circuit outputs the output signal of the storage/output circuit to the remaining screens. A liquid crystal matrix display device characterized in that it is configured to output.