JPH0466094B2 - - Google Patents
Info
- Publication number
- JPH0466094B2 JPH0466094B2 JP10531085A JP10531085A JPH0466094B2 JP H0466094 B2 JPH0466094 B2 JP H0466094B2 JP 10531085 A JP10531085 A JP 10531085A JP 10531085 A JP10531085 A JP 10531085A JP H0466094 B2 JPH0466094 B2 JP H0466094B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- pattern
- mask
- section
- mask plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
この発明は、半導体装置製造用のマスク板、特
にフアセツトカツト部形成に有効なマスク板に関
する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a mask plate for manufacturing semiconductor devices, and particularly to a mask plate effective for forming facet cut portions.
(ロ) 従来の技術
一般に、半導体ウエハにおいて、各層や電極を
形成する工程、あるいは搬送過程で、取扱い上、
ピンセツトでつまむ場合がある。この場合、箇所
をかまわずつまむと、ウエハ表面を傷つけるおそ
れがある。そこで、第３図に示すように、ウエハ
１のオリエンテーシヨンフラツト２から内側に予
めフアセツトカツト部（カツトゾーン）３を形成
し、テストではアウトとなるようにする。ウエハ
１を取扱う時は、フアセツトカツト部３をピンセ
ツトでつまむことになる。このフアセツトカツト
部３を形成するのに、従来は第２図に示すよう
に、正常なパターン形成用のパターン部４を有す
るガラス板５の下方にパターン形成すべきウエハ
１を配設し、オリエンテーシヨンフラツト２を含
むウエハ１の端部にプラスチツク板６を被せ、露
光時にこの部分に光が当たらないようにしてい
た。(b) Prior art Generally, in the process of forming each layer and electrode on a semiconductor wafer, or during the transportation process, there are
It may be pinched with tweezers. In this case, there is a risk of damaging the wafer surface if the parts are pinched too tightly. Therefore, as shown in FIG. 3, a facet cut portion (cut zone) 3 is formed in advance on the inside of the orientation flat 2 of the wafer 1 so that it will be cut out in the test. When handling the wafer 1, the facet cut portion 3 is pinched with tweezers. To form this facet cut portion 3, conventionally, as shown in FIG. 2, the wafer 1 to be patterned is placed below the glass plate 5 having the pattern portion 4 for normal pattern formation, A plastic plate 6 was placed over the edge of the wafer 1, including the shock flat 2, to prevent light from hitting this area during exposure.
(ハ) 発明が解決しようとする問題点
上記した従来技術によるフアセツトカツト部の
形成では、オリエンテーシヨンフラツト近傍にプ
ラスチツク板を被せるのみであるから、非露光
幅、つまりカツト幅が一定せず、必要以上にフア
セツトカツト部の幅を大きくしたり、逆にその幅
が狭く、時にはチツプの一部をカツトすることに
なり、本来不合格であるべきものが、テストして
も合格となるものがあつた。(c) Problems to be Solved by the Invention In the formation of the facet cut portion according to the above-mentioned prior art, since the plastic plate is only placed in the vicinity of the orientation flat, the unexposed width, that is, the cut width is not constant. If the width of the facet cut part is made larger than necessary, or conversely, the width is made narrower, sometimes a part of the chip is cut off, which may result in some parts passing the test even though they should have failed. Ta.
この発明は、上記に鑑み、ウエハのフアセツト
カツト部の幅を一定となし得る半導体装置製造用
のマスク板を提供することを目的としている。 SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a mask plate for manufacturing semiconductor devices that allows the width of a facet cut portion of a wafer to be constant.
(ニ) 問題点を解決するための手段及び作用
この発明のマスク板は、半導体ウエハに所要の
パターンを形成するためのパターン部と、このパ
ターン部に隣接して設けられる帯状の透明部と、
この透明部の前記パターン部とは反対側に隣接し
て設けられるマスク部とから構成されている。(d) Means and effects for solving the problems The mask plate of the present invention includes a pattern section for forming a desired pattern on a semiconductor wafer, a band-shaped transparent section provided adjacent to the pattern section,
The mask part is provided adjacently on the opposite side of the transparent part to the pattern part.
このマスク板を用いて半導体ウエハにパターン
を形成する場合に、透明部よりウエハ表面が目視
でき、マスク部にウエハのオリエンテーシヨンフ
ラツトを合わせると、常に一定幅のフアセツトカ
ツト部を持つウエハが得られる。 When forming a pattern on a semiconductor wafer using this mask plate, the wafer surface can be seen through the transparent part, and by aligning the orientation flat of the wafer with the mask part, a wafer with a facet cut part of a constant width can be obtained. It will be done.
(ホ) 実施例
以下、実施例により、この発明をさらに詳細に
説明する。(E) Examples The present invention will be explained in more detail below with reference to Examples.
第１図は、この発明の一実施例を示すマスク板
の平面図である。同図において、マスク板１０
は、ガラス板１１上に、ウエハに通常の層を形成
するためのパターンが描かれたパターン部１２
と、このパターン部１２に隣接したて設けられる
帯状の透明（白抜き）部１３、さらにこの透明部
１３の外側（パターン部１２とは反対側）に隣接
して、帯状のマスク（黒ベタ）部１４が形成され
て構成されている。 FIG. 1 is a plan view of a mask plate showing an embodiment of the present invention. In the figure, a mask plate 10
is a pattern section 12 on which a pattern for forming a normal layer on a wafer is drawn on a glass plate 11;
A strip-shaped transparent (white) section 13 is provided adjacent to the pattern section 12, and a strip-shaped mask (solid black) is provided adjacent to the outside of the transparent section 13 (on the opposite side to the pattern section 12). A portion 14 is formed and configured.
次に、このマスク板１０を用いてウエハ製造の
フアースト工程処理をなす場合を説明する。 Next, a case will be described in which this mask plate 10 is used to perform a first process process for manufacturing a wafer.
ウエハ１をマスク板１０の下方で移動させ、透
明部１３の上方から目視により、ウエハ１のオリ
エンテーシヨンフラツト２をマスク部１４の端縁
１４ａに合わせる。そして、マスク板１０の上方
より光を投射する。これにより、ウエハ１はオリ
エンテーシヨンフラツト２より透明部１３の幅ｔ
だけカツトされ、常に一定幅のフアセツトカツト
部（アウトゾーン）３が形成される。 The wafer 1 is moved below the mask plate 10, and the orientation flat 2 of the wafer 1 is aligned with the edge 14a of the mask part 14 by visual observation from above the transparent part 13. Then, light is projected from above the mask plate 10. As a result, the wafer 1 is moved by the width t of the transparent portion 13 from the orientation flat 2.
A facet cut portion (out zone) 3 having a constant width is always formed.
フアースト工程以後のウエハ１の位置決めは、
フアスート工程でパターン部１２によつてウエハ
１中に形成される位置決めチツプを用いることに
より、精度良くなすことができ、従つて以後の工
程では、フアセツトカツト部３の幅が変化するこ
とはない。 Positioning of wafer 1 after the first process is as follows:
By using the positioning chip formed in the wafer 1 by the pattern part 12 in the fastet process, this can be done with high precision, and therefore the width of the facet cut part 3 does not change in the subsequent steps.
(ヘ) 発明の効果
この発明によれば、マスク板のパターン部とマ
スク部の間に帯状の透明部を設けているので、こ
の透明部よりウエハを目視しながら、ウエハの位
置決めが出来るので、ウエハのフアセツトカツト
部を常に一定幅とすることができ、得られたチツ
プに不良を出したり、不必要にアウトとするのを
防止できる。特に、マスクでカツトするので、チ
ツプを分断する態様でカツトされることはなく、
歩溜りが向上する。(F) Effects of the Invention According to the present invention, since a band-shaped transparent part is provided between the pattern part of the mask plate and the mask part, the wafer can be positioned while visually observing the wafer from this transparent part. The facet cut portion of the wafer can always have a constant width, and it is possible to prevent the resulting chips from being defective or being unnecessarily rejected. In particular, since it is cut with a mask, the chip is not cut in a manner that divides it.
Yield improves.
第１図は、この発明の一実施例を示すマスク板
の平面図、第２図は、従来のウエハのフアセツト
カツト部の形成を説明するための平面図、第３図
は、ウエハの平面図である。
１……ウエハ、２……オリエンテーシヨンフラ
ツト、３……フアセツトカツト部、１０……マス
ク板、１１……ガラス板、１２……パターン部、
１３……透明部、１４……マスク部。
FIG. 1 is a plan view of a mask plate showing an embodiment of the present invention, FIG. 2 is a plan view for explaining the formation of a conventional facet cut portion of a wafer, and FIG. 3 is a plan view of a wafer. be. DESCRIPTION OF SYMBOLS 1...Wafer, 2...Orientation flat, 3...Facet cut part, 10...Mask plate, 11...Glass plate, 12...Pattern part,
13...Transparent part, 14...Mask part.
Claims (1)
ためのパターン部と、このパターン部に隣接して
設けられる帯状の透明部と、この透明部の前記パ
ターン部とは反対側に隣接して設けられるマスク
部とからなる半導体装置製造用のマスク板。1. A pattern section for forming a desired pattern on a semiconductor wafer, a band-shaped transparent section provided adjacent to the pattern section, and a mask section provided adjacent to the transparent section on the opposite side of the pattern section. A mask plate for semiconductor device manufacturing consisting of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60105310A JPS61263124A (en) | 1985-05-16 | 1985-05-16 | Mask plate for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60105310A JPS61263124A (en) | 1985-05-16 | 1985-05-16 | Mask plate for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61263124A JPS61263124A (en) | 1986-11-21 |
| JPH0466094B2 true JPH0466094B2 (en) | 1992-10-22 |
Family
ID=14404129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60105310A Granted JPS61263124A (en) | 1985-05-16 | 1985-05-16 | Mask plate for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61263124A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003022987A (en) * | 2001-07-09 | 2003-01-24 | Sanyo Electric Co Ltd | Production method for compound semiconductor device |
-
1985
- 1985-05-16 JP JP60105310A patent/JPS61263124A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61263124A (en) | 1986-11-21 |
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