JPH0464822U - - Google Patents
Info
- Publication number
- JPH0464822U JPH0464822U JP10715590U JP10715590U JPH0464822U JP H0464822 U JPH0464822 U JP H0464822U JP 10715590 U JP10715590 U JP 10715590U JP 10715590 U JP10715590 U JP 10715590U JP H0464822 U JPH0464822 U JP H0464822U
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- effect transistor
- control voltage
- amplifier
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 6
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案回路の一実施例の構成を示す接
続図、第２図は従来回路の一例の構成を示す接続
図、第３図は第２図の回路において電界効果トラ
ンジスタのゲート・ソース間電圧に対する利得変
化の一例を示す説明図である。
１……電界効果トランジスタ、Ｇ……ゲート、
Ｓ……ソース、Ｄ……ドレイン、Ｅ１……第１制
御電圧、７……反転増幅器、Ｅ２……第２制御電
圧。
Figure 1 is a connection diagram showing the configuration of an embodiment of the circuit of the present invention, Figure 2 is a connection diagram showing the configuration of an example of a conventional circuit, and Figure 3 shows the gate and source of the field effect transistor in the circuit of Figure 2. FIG. 3 is an explanatory diagram showing an example of a gain change with respect to an inter voltage. 1... Field effect transistor, G... Gate,
S...source, D...drain, E1 ...first control voltage, 7...inverting amplifier, E2 ...second control voltage.
Claims (1)
して利得を可変する増幅器において電界効果トラ
ンジスタ１のゲートＧに第１制御電圧Ｅ１を印加
すると共に電界効果トランジスタ１のソースＳに
第１制御電圧Ｅ１を反転増幅器７により反転増幅
して得られる第２制御電圧Ｅ２を印加せしめてな
る電界効果トランジスタ増幅器の利得制御回路。 In an amplifier that varies the gain by controlling the bias voltage of the field effect transistor 1, a first control voltage E1 is applied to the gate G of the field effect transistor 1 , and a first control voltage E1 is applied to the source S of the field effect transistor 1 . A gain control circuit for a field effect transistor amplifier to which a second control voltage E2 obtained by inversion amplification by an inverting amplifier 7 is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10715590U JPH0464822U (en) | 1990-10-12 | 1990-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10715590U JPH0464822U (en) | 1990-10-12 | 1990-10-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0464822U true JPH0464822U (en) | 1992-06-04 |
Family
ID=31853542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10715590U Pending JPH0464822U (en) | 1990-10-12 | 1990-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0464822U (en) |
-
1990
- 1990-10-12 JP JP10715590U patent/JPH0464822U/ja active Pending
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