JPH0463465A - Cutting method for lead of semiconductor package - Google Patents
Cutting method for lead of semiconductor packageInfo
- Publication number
- JPH0463465A JPH0463465A JP17801190A JP17801190A JPH0463465A JP H0463465 A JPH0463465 A JP H0463465A JP 17801190 A JP17801190 A JP 17801190A JP 17801190 A JP17801190 A JP 17801190A JP H0463465 A JPH0463465 A JP H0463465A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- cut
- plating
- semiconductor package
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 16
- 238000007747 plating Methods 0.000 claims abstract description 20
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 101100008048 Caenorhabditis elegans cut-4 gene Proteins 0.000 abstract 2
- 238000005452 bending Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 101100008044 Caenorhabditis elegans cut-1 gene Proteins 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体パッケージのリードカット方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead cutting method for a semiconductor package.
近年の薄型パッケージには、第３図に示すようなノーマ
ルタイプと、第４図に示すようなリバースタイプ（リー
ド逆曲げ型）とがある、第３図。Recent thin packages include a normal type as shown in FIG. 3 and a reverse type (lead reverse bend type) as shown in FIG. 4.
第４図のリードカットは、第５図、第６図のように行わ
れていた。The lead cut shown in FIG. 4 was performed as shown in FIGS. 5 and 6.
すなわち、第５図（ａ）〜（ｃ）はノーマルタイプの従
来のリードカット方法を示すものである。That is, FIGS. 5(a) to 5(c) show a conventional lead cutting method of a normal type.
この図において、１は半導体パッケージから外部に突設
されたリードであり、２はこのり一ド１に外装されたメ
ツキ、３はこのリードカッ１−後のメッキダレである。In this figure, 1 is a lead protruding from the semiconductor package, 2 is plating externally mounted on the lead 1, and 3 is plating sag after the lead cut 1.
また、４は前記リード１のカット方向を示している。Further, 4 indicates the direction in which the lead 1 is cut.
第５図のリードカットは、まず、第５図（ａ）の状態に
あるリード１をカット方向４よりリードカットすると、
第５図（ｂ）のようになり、リード１を曲げ加工すると
、第５図（Ｃ）のように成形される。In the lead cutting shown in FIG. 5, first, lead 1 in the state shown in FIG. 5(a) is cut from cutting direction 4.
The result is as shown in FIG. 5(b), and when the lead 1 is bent, it is formed as shown in FIG. 5(C).
また、第６図は、第４図のリバースタイプのリードカッ
ト方法を示すもので、第６図（ａ）（ｂ）のように、第
５図（ａ）、（ｂ）と同様にリードカットした後、リー
ド１を逆方向に曲げたものである。すなわち、第６図（
ｅ）に示すように、第５図（Ｃ１と逆方向となる。従っ
て、第５図（Ｃ）および第６図（Ｃ）の状態で基板に半
田付けを行うとそれぞれ第７図および第８図のようにな
る。In addition, Fig. 6 shows the reverse type lead cutting method shown in Fig. 4, and as shown in Fig. 6 (a) and (b), the lead is cut in the same way as Fig. 5 (a) and (b). After that, lead 1 was bent in the opposite direction. In other words, Fig. 6 (
As shown in e), the direction is opposite to that shown in Fig. 5 (C1). Therefore, if the board is soldered in the states shown in Figs. It will look like the figure.
つまり、第５図のノーマルタイプのリード１の場合には
、第７図に示すように、基板面５側のリドカッ１−面に
はメッキダレ３が付着していないので、半田は付かず、
メツキ２のある片側にのみ半田６が接着している。In other words, in the case of the normal type lead 1 shown in FIG. 5, as shown in FIG. 7, the plating sag 3 is not attached to the surface of the lid cutter 1 on the board surface 5 side, so no solder is attached.
Solder 6 is bonded only to one side with plating 2.
また、第６図のリバースタイプの場合では、メッキダレ
３が第８図に示すように、基板面５側にあるため、リー
ド１の先端部分でも半田７が付着することになる。Further, in the case of the reverse type shown in FIG. 6, since the plating sag 3 is on the substrate surface 5 side as shown in FIG. 8, the solder 7 also adheres to the tip portion of the lead 1.
従来のリードカットは以上のような方法で行われている
ので、リード１の先端部分にはり一ド１の曲げ方向によ
っては、半田が付着せず、接合強度が低下する等の問題
点があった。Conventional lead cutting is carried out using the method described above, but depending on the bending direction of the lead 1, there are problems such as solder not adhering to the tip of the lead 1 and the bonding strength decreasing. Ta.
この発明は、上記のような問題点を解消するためになさ
れたもので、全面半田付けが可能な半導体パッケージの
リードカット方法を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a lead cutting method for a semiconductor package that allows soldering on the entire surface.
この発明に係る半導体パッケージのリードカッＩ・方法
は、各タイプの半導体パッケージがプリント基板に実装
されたとき、各タイプの半導体パッケージのリードのカ
ット面のプリン）・基板との接着面側にメッキダレが形
成される方向からり一ドカットを行うものである。The semiconductor package lead cutting method I according to the present invention is such that when each type of semiconductor package is mounted on a printed circuit board, plating sag is removed on the cut side of the lead of each type of semiconductor package and on the adhesive side with the board. A straight cut is made from the direction in which it is formed.
この発明におけるリードカット方法は、ノーマルタイプ
のリードカット方向と、リバースタイプのリードカット
方向を逆にすることにより、リドカット面のメッキダレ
は、基板面側に形成され、全面に半田が付着する。In the lead cutting method of the present invention, by reversing the normal type lead cutting direction and the reverse type lead cutting direction, plating sag on the lead cut surface is formed on the substrate surface side, and solder adheres to the entire surface.
以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図（ａ）〜（Ｃ）はノーマルタイプのり一ドカット
方法を示し、第２図（−）〜（Ｃ）はリバースタイプの
リードカット方法を示す図である。FIGS. 1(a) to 1(C) show a normal type lead cutting method, and FIGS. 2(-) to 2(C) show a reverse type lead cutting method.
第１図と第２図のリードカッ１一方法の違いは、それぞ
れリード１のリードカット方向を逆にすることによって
、リード曲げ後のメツキ２のメッキダレ３の方向をノー
マルタイプとリバースタイプともに同一になるようにリ
ードカットし、しかもメツキ２が半田接着面側（プリン
１−基板側）に残るようにリードカッ）・を行うもので
ある。The difference between the lead cutting methods in Figures 1 and 2 is that by reversing the lead cutting direction of lead 1, the direction of plating sag 3 on plating 2 after lead bending is the same for both the normal type and reverse type. Lead cutting is performed so that the plating 2 remains on the solder bonding surface side (print 1 - board side).
以上説明したように、この発明は、各タイプの半導体パ
ッケージがプリント基板に実装されたとき、各タイプの
半導体パッケージのリードのカット面のプリント基板と
の接着面側にメッキダレが形成される方向からリードカ
ットを行うので、リドカッ１−後の曲げ加工の曲げ方向
にかかわらず、基板面側にメッキダレが形成され、全面
に半田が付着し、高信頼性の半導体パッケージが得られ
る。As explained above, the present invention is directed to the direction in which plating sag is formed on the adhesive side of the cut surface of the lead of each type of semiconductor package to the printed circuit board when each type of semiconductor package is mounted on a printed circuit board. Since lead cutting is performed, plating sag is formed on the substrate surface side, and solder adheres to the entire surface, regardless of the bending direction of the bending process after re-cutting, resulting in a highly reliable semiconductor package.
第１図、第２図はこの発明の一実施例によるりドカット
方法を示す図、第３図はノーマルタイプのパッケージの
上面図、第４図はリバースタイプのパッケージの上面図
、第５図２第６図は従来のリードカット方法を示す図、
第７図、第８図は従来のリードカッ１−後の半田付は状
態を示す図である。
図において、１はリード、２はメツキ、３はメッキダレ
、４ばリードカッ１一方向、５は基板面、６．７は半田
である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第
図
第
図
第
図
第
図
第
図
第
図
第
図
第
図
拳旧FIGS. 1 and 2 are diagrams showing a vertical cut method according to an embodiment of the present invention, FIG. 3 is a top view of a normal type package, FIG. 4 is a top view of a reverse type package, and FIG. 5 is a top view of a reverse type package. Figure 6 is a diagram showing the conventional lead cutting method.
FIGS. 7 and 8 are diagrams showing the state of soldering after the conventional lead cutter 1. In the figure, 1 is a lead, 2 is plating, 3 is a plating sag, 4 is a lead cut 1 in one direction, 5 is a substrate surface, and 6.7 is solder. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others)
Claims (1)
ージのリードを、そのリードカット面にメッキダレが形
成されるようにリードカットする方法において、前記各
タイプの半導体パッケージがプリント基板に実装された
とき、前記各タイプの半導体パッケージのリードのカッ
ト面の前記プリント基板との接着面側にメッキダレが形
成される方向からリードカットを行うことを特徴とする
半導体パッケージのリードカット方法。In a method for cutting the leads of normal type and reverse type semiconductor packages so that plating sag is formed on the lead cut surface, when each type of semiconductor package is mounted on a printed circuit board, each type of semiconductor package is mounted on a printed circuit board. A method for cutting leads of a semiconductor package, characterized in that the leads are cut in a direction in which plating sag is formed on the cut surface of the lead of the package on the side that is bonded to the printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2178011A JP2522094B2 (en) | 1990-07-03 | 1990-07-03 | Lead-cut method for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2178011A JP2522094B2 (en) | 1990-07-03 | 1990-07-03 | Lead-cut method for semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0463465A true JPH0463465A (en) | 1992-02-28 |
| JP2522094B2 JP2522094B2 (en) | 1996-08-07 |
Family
ID=16041001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2178011A Expired - Lifetime JP2522094B2 (en) | 1990-07-03 | 1990-07-03 | Lead-cut method for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2522094B2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS632358A (en) * | 1986-06-16 | 1988-01-07 | テキサス インスツルメンツ インコ−ポレイテツド | Lead frame and plating of the same |
| JPS639957A (en) * | 1986-07-01 | 1988-01-16 | Furukawa Electric Co Ltd:The | Semiconductor lead frame |
| JPS6318853A (en) * | 1986-07-11 | 1988-01-26 | Hitachi Ltd | Contents variable talky sending system |
| JPS6428852A (en) * | 1987-07-24 | 1989-01-31 | Hitachi Ltd | Semiconductor device |
-
1990
- 1990-07-03 JP JP2178011A patent/JP2522094B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS632358A (en) * | 1986-06-16 | 1988-01-07 | テキサス インスツルメンツ インコ−ポレイテツド | Lead frame and plating of the same |
| JPS639957A (en) * | 1986-07-01 | 1988-01-16 | Furukawa Electric Co Ltd:The | Semiconductor lead frame |
| JPS6318853A (en) * | 1986-07-11 | 1988-01-26 | Hitachi Ltd | Contents variable talky sending system |
| JPS6428852A (en) * | 1987-07-24 | 1989-01-31 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2522094B2 (en) | 1996-08-07 |
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