JPH0463437A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make the channels of mixed field effect transistors the same length and suppress fluctuation thereof by arranging parallel dummy patterns of the same material as distantly as specified from gate electrodes. CONSTITUTION:Dummy patterns 15 of the same material, such as polysilicon, as gate electrodes 4 are arranged at the outside of, parallel with, and at specified distances S from the gate electrodes 4 and on element separation insulating films 2. Therefore, whether a single gate electrode type or a multiple gate electrode type, the gate electrodes 4 of mixed field effect transistors on a semiconductor integrated circuit device are arranged between the parallel dummy patterns 15 at the specified distances S and the exposure conditions in making the gate electrodes 4 are the same. Thereby the channels of the mixed field effect transistors are made the same length and fluctuation thereof is suppressed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device in which a plurality of field effect transistors such as MO3-FETs are mixedly formed. This invention relates to a technique for aligning the channel lengths of field effect transistors.

[Conventional technology]

Conventionally, as this type of semiconductor integrated circuit device, M
O3 integrated circuit devices are the best known. Therefore, in the description of the present invention, it is assumed that the semiconductor integrated circuit device is an MO3 integrated circuit device, and that this MO3 integrated circuit device is constituted by a plurality of n-channel MO3-FETs.

In addition, as MO3-FET, Fig. 6 (a), (b)
8(a) and 8(b), which is called a single gate electrode type with a single gate electrode and a small channel length, as shown in FIG. 8(a) and 8(b). There is a type called a multiple gate electrode type which has a large channel length by having multiple gate electrodes. In MO3 integrated circuit devices, MOS-F, which is called single gate electrode type and multiple gate/electrode type,
Normally, both ETs are formed in a mixed manner on the same chip.

Therefore, in the following explanation, first, the single gate electrode type M
After describing the O3-FET, we will discuss the multiple gate electrode type.

FIG. 6(a) is a plan view showing the schematic structure of an n-channel type MOS-FET, which is said to be a single gate electrode type, during the manufacturing process, and FIG.
It is a sectional view showing a cut structure along line -B. The reference numeral 1 in these figures indicates a p-type silicon substrate,
2 is an insulating film for element isolation, 3 is a gate insulating film that covers the channel of the MOS-FET, 4 is its gate electrode, and 5 is an interlayer insulating film that covers the insulating film 2 for element isolation and the gate electrode 4. Also, the code 6.7 is an n4 type MOSFE.
These source and drain regions 6 and 7 are electrically connected through contact holes 8.9 formed in the interlayer insulating film 5. Further, reference numeral 10 is a contact hole for electrically connecting the gate electrode 4, 11 is a field pattern indicating the boundary of the element isolation insulating film 2, and Ll is a MOS-FE
The pattern width of the gate electrode 4, which determines the channel length of T, is shown.

The manufacturing procedure of this MOS-FET is shown in Figures 7(a) to (e).
) will be explained based on the process cross-sectional diagrams shown.

First, an insulating film 12 that will become an element isolation insulating film 2 and a gate insulating film 3 is formed on the surface of a silicon substrate 1, and then a polysilicon film 13 that completely covers the surface is formed (7th [D (see (a)). Next, apply a positive (or negative) photoresist to the polysilicon film 1.
3, the non-exposure area 14 of the photoresist film 14, which is necessary for forming the gate electrode 4, is removed.
A is masked, and exposure is performed by irradiating light onto the exposure area 14b of the photoresist film 14 that is not masked by using a reduction projection exposure device or the like (7th step).
(See Figure (b)) Therefore, if the photoresist film 14 is positive type, only the unexposed region 14a remains on the polysilicon M13 without being removed if development is performed after the exposure is completed. (See Figure 7(c)). Then, the pattern width Ll of the non-exposure area 14a at this time
(R) is a major factor in determining the channel length of the MOS-FET.

Subsequently, when unnecessary portions of the polysilicon film 13 are removed by performing anisotropic etching, for example, reactive ion etching, using the remaining non-exposure region 14a as a mask, the area covered with the non-exposure region 14a is removed. The removed polysilicon film 13 partially remains, and the gate electrode 4 is formed (see FIG. 7(d)).

Then, the pattern width L1 of the gate electrode 4 at this time is
The channel length of the MOS-FET will be determined. Next, an n'' type impurity is implanted using the non-exposure region 14a as a mask, and then unnecessary portions of the non-exposure region 14a and the insulating film 12 are removed and the n4 type impurity is thermally diffused. Silicon substrate 1 located on both sides of 4
N° type source and drain regions 6 and 7 are formed therein (see FIG. 7(e)).Furthermore, after forming an interlayer insulating film 5, contact holes 8 to 7 are formed in this glabellar insulating film 5.
10, an n-channel type MO3, which is said to be a single gate electrode type, with the configuration shown in FIGS. 6(a) and 6(b) is formed.
-FET will be completed.

Next, based on FIGS. 8(a) and 8(b), an n-channel type MO3-FET, which is called a multiple gate electrode type and is used when a long channel length is desired, will be explained.

FIG. 8(a) is a plan view showing the schematic structure of an n-channel MOS-FET, which is said to be a multiple gate electrode type, during the manufacturing process, and FIG. 8(b) is a plan view showing the structure shown in FIG.
It is a sectional view showing a cut structure along line -B. The difference between the so-called multi-gate electrode type MOS-FET and the single-gate electrode type MOS-FET is that, as is clear from the figure, the single gate electrode 4 is divided into multiple pieces ( In the figure, it is located at the point where it is divided into three parts), so it is located at the point where it is divided into three parts (in the figure).
In a) and (b), the same or corresponding parts as in FIGS. 6(a) and (b) are designated by the same reference numerals, and detailed explanation thereof will be omitted.

That is, the reference numeral 4a in FIGS. 8(a) and (b)
~4c are gate electrodes formed at a predetermined distance S, L is the pattern width of the gate electrodes 4a and 4c located at both ends of the MOS-FET, and L is the gate electrode located at the center. 4b shows the pattern width.

Note that the spacing S between these gate electrodes 4a to 4C is M
This is set when designing the O3-FET, for example, the diameter of the contact hole 8.9 is set to 0.5 μm,
When the distance between these ends and each end of the gate electrodes 43 to 4C is 0.3 μm, the spacing S is 1.1 μm.

Next, the manufacturing procedure of this n-channel type MO8-FET, which is said to be a multiple gate electrode type, will be explained. Since the manufacturing procedure is the same as that of the electrode mold, here, we will explain the steps that require explanation based on the process cross-sectional views shown in FIGS. 9(a) to 9(c), which correspond to FIGS. 7(b) to (d). I will only talk about this.

First, a photoresist film 14 is formed on the polysilicon film 13 covering the element isolation insulating film 2 and the insulating film 12 by the same procedure as explained based on FIG. 7(a). After that, the non-exposure regions 14C and 14d of the photoresist film 14, which are necessary for forming the gate electrodes 42 to 4c spaced apart from each other by a predetermined distance S, are masked, and the masking is performed by using a reduction projection exposure device or the like. Exposure is performed by irradiating light onto the exposed areas 14e and 14f of the photoresist film 14 that are not exposed (see FIG. 9(a)).
)reference).

Therefore, if development is performed after exposure is completed, if the photoresist film 14 is positive type, the polysilicon film 13
Above, non-exposure areas 14C and 14d remain without being removed (see FIG. 9(b)). The pattern width Lm (R) L3 (R) of each of the non-exposure areas 14C and 14d at this time becomes a major factor in determining the channel length of the MO3-FET.

Thereafter, the polysilicon film 1 is etched by anisotropic etching using the remaining unexposed region 14C14d as a mask.
When unnecessary portions 3 are removed, gate electrodes 4a to 4C are formed which are spaced apart from each other by a predetermined distance S (see FIG. 9(c)).

The pattern widths Lt and Ls of the gate electrodes 43 to 4C at this time determine the channel length of the MO3-FET. Furthermore, when the same operation as explained based on FIG. 7(e) is performed, n4 type source and drain regions 6.7 are formed in the silicon substrate 1, and as shown in FIG. 8(a), An n-channel type MO3-FET, which is said to be a multiple gate electrode type, having the configuration shown in (b) is completed.

[Problem to be solved by the invention]

By the way, in the MO3 integrated circuit device used on a boat, the single gate electrode type and multiple gate electrode type M
Both OS-FETs are formed in a mixed manner on the same chip. However, these MOS
-For example, the patterning when manufacturing FET is
When miniaturized to 0.3 to 0.5 μm,
Even if the pattern widths L1 to L of the gate electrodes 4.43 to 4c of each MO3-FET are set to be equal, and the photoresist film 14 is exposed by using light of the same wavelength, Obtained MOSFET
This resulted in the inconvenience that the respective channel lengths were not equal to each other and varied.

Such inconveniences are thought to occur based on the following factors. That is, first, in a single gate electrode type MO3-FET, as shown in FIG. 7(b)
, As shown in (c), the photoresist film 1 is different from the wavelength of the light irradiated to expose the photoresist film 14 (for example, 0.248 μm for yuximer laser light).
Since the exposure area 14b of No. 4 has a sufficient length, the exposure area 14b is sufficiently exposed, and as a result, the pattern width Ll(R
) tends to become thinner. However, in a multiple gate electrode type MOS-FET, as shown in FIGS. 9(a) and (b).
As shown in , although the length of the exposed area 14f is sufficient for the wavelength of light,
The length of the exposure area 14e between 4d is several times the wavelength of light to 1
approximately 0 times (the above-mentioned separation interval S, that is, exposure area 1
When the length of 4e is set to 1.1 μm, 1.1/
0.248=4.4 times), these exposed areas 14e are affected by light diffraction and reflection, resulting in insufficient exposure. Therefore, the non-exposure area 14 sandwiched between these exposure areas 14e
The pattern width L2 (R) of d tends to become thicker, whereas the pattern width Ls (R) of the non-exposure area 14C sandwiched between the exposure area 14e and the exposure area 14f tends to become thinner and thicker. Due to the balance, the thickness tends to be the average of both.

Therefore, in the initial design, MO
Although the pattern widths L+ to L of the gate electrodes 4.4a to 4c of the 3-FET were set to be equal, at the end of the wafer process, single gate electrode type and multiple gate electrode type MO5 for each type
-Gate electrodes 4, 4a that determine the channel length of the FET
There has been an inconvenience that the pattern width L+''-La of 4C is different from each other.Furthermore, in the MO3-FET itself, which is a multiple gate electrode type, the gate electrodes 4a, 4c located at both ends of the MO3-FET are different from each other. The pattern widths Lz and Ls were supposed to be different between the gate electrode 4b located at the center.

The present invention was devised in view of these disadvantages, and provides a semiconductor integrated circuit device in which channel lengths of field effect transistors formed in a mixed manner can be made equal to each other, and variations in the channel lengths can be suppressed. The purpose is to provide

[Means to solve the problem]

In order to achieve such an object, the present invention provides a semiconductor integrated circuit device in which a plurality of field effect transistors having a single or plural gate electrodes are mixedly formed, the gate electrode of each field effect transistor being The device is characterized in that a dummy pattern made of the same material is formed on each of the outer sides of the electrode, positioned parallel to and spaced apart from the gate electrode by a predetermined distance.

[Effect]

According to the above configuration, regardless of whether the field effect transistors formed in a semiconductor integrated circuit device are single gate electrode type or multiple gate electrode type, the gate electrodes are spaced apart by a predetermined distance. It is sandwiched between dummy patterns positioned in parallel. Therefore, the exposure conditions for manufacturing these gate electrodes are the same.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. In this embodiment, it is assumed that the semiconductor integrated circuit device is an MO3 integrated circuit device consisting of a plurality of n-channel type MOS-FETs.

The MO5 integrated circuit device in this embodiment is an n-channel type MO5, which is called a single gate electrode type and a multiple gate electrode type.
It is composed of a plurality of 3-FETs, and these MO5-FETs are formed in a mixed manner on the same chip. Therefore, in the following explanation, we will first start with Figure 1 (
After explaining the configuration and manufacturing procedure of a single gate electrode type MOS-FET based on FIGS. 46(a) and 2(a) to (e),
Based on FIGS. 5(b) and 5(a) to 5(c), the structure and manufacturing procedure of MO3-FET, which is called a multiple gate electrode type, will be described. In addition, MO3 according to this example
-The overall structure of the FET is basically different from the conventional example shown in Figs. 6(a), (b) and 8(a), (b), except for the provision of a dummy pattern, which will be described later. Therefore, parts and portions that are the same or correspond to each other are given the same reference numerals.

FIG. 1(a) is a plan view showing the schematic structure of an n-channel MO3-FET, which is said to be a single gate electrode type, during the manufacturing process, and FIG. B
It is a sectional view showing a cutting structure along a line. In these figures, reference numeral 1 indicates a p-type silicon substrate, 2 an insulating film for element isolation, 3 a gate insulating film covering the channel of the MO3-FET, and 4 a gate electrode made of polysilicon or the like. Further, at each outer position of the gate electrode 4, a dummy pattern 15 made of polysilicon or the like, which is the same material as the gate electrode 4, is positioned parallel to the gate electrode 4 at a predetermined distance S. It is formed on the membrane 2. Note that these dummy patterns 15 are formed in a state electrically isolated from the gate electrode 4, and the distance S between each of these dummy patterns and the gate electrode 4 is the same as that of the multiple gate electrode type described in the conventional example. The spacing S between the gate electrodes 43 to 40 in the MOS-FET is set to be the same or approximately the same.

Further, the reference numeral 5 in the figure is an interlayer insulating film that covers each of the element isolation insulating film 2, the gate electrode 4, and the dummy pattern 15, and 6.7 is the source and drain region of an n-type MOS-FET. , these source and drain regions 6 and 7 are electrically connected through a contact hole 89 formed in the glabellar insulation [5]. Further, reference numeral 10 is a contact hole for electrically connecting the gate electrode 4, 11 is a field pattern indicating the boundary of the element isolation insulating film 2, and L determines the channel length of the MOS-FET. The pattern width of the gate electrode 4 is shown.

The manufacturing procedure of this MOS-FET is shown in Figures 2(a) to (e).
) will be explained based on the process cross-sectional diagrams shown.

First, an insulating film 12 that is to become an element isolation insulating film 2 and a gate insulating film 3 is formed on the surface of a silicon substrate 1, and then a polysilicon film 13 is formed to completely cover the surface (see FIG. 2). a)). Next, a positive type (or negative type) photoresist is applied to form the polysilicon film 13.
After covering the entire surface of the photoresist film 14, the non-exposure area 14a of the photoresist film 14, which is necessary to form the gate electrode 4 and the dummy pattern 15 spaced apart by a predetermined distance S from each other.
, 14g, and the exposed area 14h of the photoresist film 14 that is not masked by using a reduction projection exposure device or the like.

Exposure is performed by irradiating light onto 14i (see Figure 2 (b)).
. Therefore, if development is performed after exposure is completed, if the photoresist film 14 is positive type, the polysilicon film 1
3, a non-exposure region 14g remains without being removed along with a non-exposure region 14a having a pattern width L(R) (see FIG. 2(c)). In addition, here, photoresist) It! Although 14 exposures are assumed to be performed, for example, X&? The same applies to exposure using 1 or an electron beam.

Subsequently, when unnecessary portions of the polysilicon film 13 are removed by anisotropic etching, such as reactive ion etching, using the remaining non-exposure regions 14214g as a mask, the polysilicon 1Iu 13 covered with the non-exposure regions 14a and 14g is removed. A gate electrode 4 and a dummy pattern 15 having the width of the pattern are formed (see FIG. 2(d)).Next, using this unexposed area 148.14g as a mask, an n-type After implanting impurities, the non-exposure regions 14a and 14g and the insulating film 1
By removing unnecessary portions of 2 and performing thermal diffusion of n-type impurities, n0-type source and drain regions 6 and 7 are formed in the silicon substrate 1 located on both sides of the gate electrode 4 (
(See Figure 2(e)). Furthermore, after forming the glabellar insulating film 5, contact holes 8 to 10 are formed in this interlayer insulating film 5, and an n-channel so-called single gate electrode type having the configuration shown in FIGS. 1(a) and 1(b) is formed. Type MO3-FE
T will be completed. Therefore, this MOS-FET
A dummy pattern 15 is formed at each outer position of the gate electrode 4, which is positioned parallel to the gate electrode 4 and spaced apart from it by a predetermined distance S.

Note that in FIGS. 1(a) and 1(b), it is assumed that the dummy pattern 15 is electrically isolated from the gate electrode 4 and is formed on the element isolation vA film 2; It is not limited to.

That is, for example, as shown in FIG. 3(a), the dummy pattern 15 may be connected and integrated with the gate electrode 4, or as shown in FIG. 3(b), these dummy patterns Other wiring patterns 16 constituting the MO3 integrated circuit device may be used as the pattern 15;
As shown in FIG. 3C, it is also possible to configure the dummy pattern 15 as a dummy gate electrode having exactly the same configuration as the gate electrode 4.

Next, an n-channel type MO3-FET, which is called a multiple gate electrode type, will be explained based on FIGS. 4(a) and 4(b).

FIG. 4(a) is a plan view showing the schematic structure of a channel type MO3-FET, which is said to be a multiple gate electrode type, during the manufacturing process, and FIG.
It is a sectional view showing a cutting structure along a line. Note that since the basic configurations of the multiple gate electrode type MOS-FET and the single gate electrode type MOS-FET are mutually common, the first
Portions that are the same or correspond to those in FIGS. (a) and (b) are designated by the same reference numerals, and detailed description thereof will be omitted.

In other words, this MOS-F, which is said to be a multiple gate electrode type,
In ET, as shown in FIGS. 4(a) and 4(b), gate electrodes 4a to 4C made of polysilicon are formed at a predetermined distance S from each other. At each of the outer positions of these gate electrodes 42 to 4C, a dummy pattern made of the same material such as polysilicon is positioned parallel to and spaced apart from the gate electrodes 4a and 4c at both ends by a predetermined distance S. 15 is formed on the element isolation insulating film 2. Note that here, the spacing S between the gate electrode 4 and each of the dummy patterns 15 is set to be the same or approximately equal to the spacing S between the gate electrodes 4a to 4c.

Next, the manufacturing procedure of this n-channel type MO3-FET, which is called a multiple gate electrode type, will be explained. The manufacturing procedure of this MOS-FET is shown in Figure 2 (a) to (e).
Since the manufacturing procedure is basically the same as that of the single gate electrode type explained based on FIG.
Only the different steps will be described based on the process cross-sectional views shown in FIGS. 5(a) to 5(c) corresponding to FIG.

First, photoresist #14 is formed on the polysilicon film 13 covering the element isolation insulating film 2 and the insulating film 12 by the same procedure as explained based on FIG. 2(a). Thereafter, non-exposure areas 14j of the photoresist film 14 necessary for forming gate electrodes 4a to 4c and dummy patterns 15 spaced apart from each other by a predetermined distance S are formed.
, 14k are masked, and exposure is performed by irradiating light onto the exposed regions 14m and 14n of the photoresist film 14 that are not masked by using a reduction projection exposure device or the like (see FIG. 5(a)).

Therefore, if development is performed after exposure is completed, if the photoresist film 14 is positive type, the polysilicon film 13
Above, non-exposure areas 14j and 14k remain without being removed (see FIG. 5(b)). Then, the pattern radius L(R) of the non-exposure area 14j at this time is
This is a major factor in determining the channel length of a MOS-FET.

Thereafter, the polysilicon film 1 is etched by anisotropic etching using the remaining non-exposure regions 14j14k as a mask.
When unnecessary portions 3 are removed, gate electrodes 4a to 4C and dummy patterns 15 are formed which are spaced apart from each other by a predetermined distance S (see FIG. 5(c)). Then, the channel length of the MOSFET is determined by the pattern roundness of the gate electrodes 43 to 4c at this time. Furthermore, the second
When the same operation as explained based on FIG. 4(e) is performed, n-type source and drain regions 6.7 are formed in the silicon substrate II, as shown in FIG. 4(a).

An n-channel type MOS-FET, which is said to be a multiple gate electrode type, having the configuration shown in (b) is completed. Therefore, a dummy pattern 15 is formed at each of the outer positions of the gate electrodes 4a to 4c of the MOS-FET, and is positioned parallel to the gate electrodes 4a to 4c at a predetermined distance S.

The single gate electrode type and multiple gate electrode type MOS-FETs described above are both formed on the same chip, but in this case, each M
Dummy patterns 15 are formed parallel to each other at a predetermined interval S at outer positions of the gate electrodes 4.4a to 4c in the O3-FET.
4c are arranged sandwiched between the dummy patterns 15.

〔Effect of the invention〕

As explained above, according to the semiconductor device circuit device according to the present invention, regardless of whether the field effect transistors formed therein are of a single gate electrode type or a multi-gate m-pole type, , the gate electrodes are sandwiched between dummy patterns positioned parallel to each other and spaced apart by a predetermined distance. Therefore, the exposure conditions when manufacturing these gate electrodes are the same, and the pattern widths of the resulting gate electrodes are approximately the same.

As a result, the channel lengths of the field effect transistors formed in a mixed manner can be made equal to each other, and an excellent effect can be obtained in that variations thereof can be suppressed.

[Brief explanation of drawings]

1 to 5 relate to embodiments of the present invention, and FIG.
a) is an n-channel type MO3 which is said to be a single gate electrode type.
-A plan view showing a schematic structure during the manufacturing process of the FET; FIG. 1(b) is a cross-sectional view showing the cut structure along line B-B in FIG. ) is a process sectional view showing the manufacturing procedure, and FIGS. 3(a) to 3(c) are plan views showing modifications thereof. In addition, Fig. 4(a) shows an n-channel type MO3-FET, which is said to be a multiple gate electrode type.
FIG. 4(b) is a plan view showing a schematic structure in the middle of manufacturing process, and FIG. 4(b) is a cross-sectional view showing the cut structure along line B-B in FIG. ) is a process sectional view showing the manufacturing procedure. Furthermore, FIGS. 6 to 9 relate to the conventional example, and FIG. 6 (
a) is an n-channel type MO3 which is said to be a single gate electrode type.
-A plan view showing the schematic structure of the FET in the middle of the manufacturing process; FIG. 6(b) is a cross-sectional view showing the cut structure along line B-B in FIG. ) is a process sectional view showing the manufacturing procedure. In addition, FIG. 8(a) is a plan view showing a schematic structure during the manufacturing process of an n-channel type MO3-FET, which is said to be a multiple gate electrode type, and FIG. 8(b)
) is a sectional view showing the cut structure taken along the line BB in FIG. 8(a), and FIGS. 9(a) to 9(c) are process sectional views showing the manufacturing procedure thereof. In the figure, numerals 4.4a to 4c each represent a gate electrode, 15 a dummy pattern, L the pattern width of the gate electrode, and S a separation interval (predetermined interval). Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 (,)

Claims (1)

[Claims] (1) A semiconductor integrated circuit device in which a plurality of field effect transistors each having a single or multiple gate electrodes are formed in a mixed manner, in which the gate electrode and 1. A semiconductor integrated circuit device comprising dummy patterns positioned in parallel at predetermined intervals and made of the same material.