JPH11204660A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of a twin-well structure, of which reliability is improved by shalllowly forming wells under a gate electrode structure. SOLUTION: A thick-film resist pattern 7a and a thin-film resist pattern are formed through the same exposure process, using a reticle having a semi- transmitting area 6a, comprising a plurality of light-proof areas (lines) and light-transmitting areas (spaces) with dimensions smaller than the critical resolving power of the exposure system. To form wells, impurity ions are implanted by transmission of light through a thin film resist pattern 7b. Consequently, a shallow p-well is formed in the thin-film resist pattern 7b, and impurity ion implantation to the lower layer of the thick-film resist pattern 7a is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a twin-well structure including a p-well and an n-well on a semiconductor substrate.

[0002]

2. Description of the Related Art A conventional method for forming a twin well structure will be briefly described. First, a known LO is placed on a silicon semiconductor substrate.
An element isolation structure is formed by a COS method or the like, and each element active region forming a twin well is defined.

Subsequently, in forming the p-well, a resist pattern is formed by known photolithography to cover the region for forming the n-well so that p-type impurities are not introduced, and only the region for forming the p-well is formed. Open.

[0004] Then, boron (B) ions are implanted to form an ion-implanted layer on the silicon semiconductor substrate in the opened region.

Next, after removing the resist pattern, a resist pattern is formed by photolithography in the same manner as above, covering the p-well formation region where the ion implantation layer is formed and opening the region where the n-well is to be formed.

Then, phosphorus (P) ions are implanted, and n
An ion implantation layer is formed on the silicon semiconductor substrate in the well formation region. Next, high-temperature, long-time heat treatment is performed to diffuse the ion-implanted layer implanted into the p-well formation region and the n-well formation region. Thereby, thermal diffusion is performed, and a twin well structure including a p well and an n well is completed.

As described above, after the twin well structure is formed, a gate oxide film and an impurity-doped polycrystalline silicon film are sequentially formed on the element active region in each well, and photolithography and subsequent dry lithography are performed. A gate structure is formed by etching.

Then, ion implantation is performed to form a high concentration impurity diffusion layer corresponding to the source / drain. By this ion implantation, source / drain diffusion layers are formed in the surface region of the silicon semiconductor substrate on both sides of the gate structure. Then, in each of the p-well and the n-well, an M including a gate and source / drain diffusion layers is formed.
The OS transistor is completed.

FIG. 8 shows a twin well structure formed by the above-described steps and a MOS transistor formed in each well region.

That is, in FIG. 8, a silicon semiconductor substrate 21 is element-isolated by a field oxide film 24, a p-well 29 is formed in one element active region, and an n-well 30 is formed in the other element active region. Are formed. Each well has a gate oxide film 2
2. A gate structure including a gate electrode 26 is formed, and a pair of impurity diffusion layers 23 and 25 are formed in a surface region of the silicon semiconductor substrate 21 on both sides of the gate structure.

As shown in FIG. 8, according to the above-described method, both the p-well 29 and the n-well 30 are formed at the same depth immediately below the gate structure and immediately below the source / drain diffusion layers. You.

However, if wells are formed at the same depth below the gate structure and the source / drain diffusion layers as described above, the gate depletion capacitance becomes large immediately below the gate electrode structure, resulting in junction leakage. An electric current is generated. For this reason, it is necessary to take measures under low voltage.

To prevent this problem, Japanese Patent Application Laid-Open No. 7-18 / 1990
Japanese Patent No. 3514 describes a structure in which only the well layer immediately below the gate electrode structure is made shallow. According to the above publication, only a gate electrode region is covered with a thin resist film at the time of ion implantation for forming a well, and ion implantation is performed with energy transmitted through the resist film, whereby a gate electrode as shown in FIG. A shallow well 31a is formed immediately below the structure, and a normally deep well 31b is formed in another region, that is, a region immediately below the source / drain diffusion layers.

[0014]

However, according to the method described in Japanese Patent Application Laid-Open No. Hei 7-183514, in the case of a single well structure, the above structure can be formed, but the p-well and the n-well are not used. In the formed twin well structure, a shallow well could not be formed immediately below the gate electrode structure.

FIG. 10 shows a case where the method described in JP-A-7-183514 is applied to a twin well structure. When a twin well structure is formed, it is necessary to form a resist pattern 32a covering the n well when forming the p well as described above. Then, simultaneously with the formation of the resist pattern 32a covering the n-well, a thin resist pattern 32b for making the p-well just below the gate electrode structure shallow is formed.

In this case, as is apparent from FIG. 10, since the resist pattern is formed uniformly over the entire area, when impurities are ion-implanted through the thin resist pattern 32b in the p-well, Impurities are also ion-implanted into the silicon semiconductor substrate 21 in the region where the n-well is to be formed.

That is, according to the method described in Japanese Patent Application Laid-Open No. Hei 7-183514, it is not possible to make the impurity by ion implantation reach only the lower layer of the resist pattern 32b without reaching the lower layer of the resist pattern 32a. .

Accordingly, an object of the present invention is to provide a semiconductor device having a twin well structure in which each well can be formed shallow immediately below the gate electrode structure.
An object of the present invention is to provide a method for manufacturing a semiconductor device with improved reliability.

[0019]

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a well structure on a semiconductor substrate, comprising a thin film region and a thick film region, wherein the thin film region A first step of forming a first resist pattern having an adjacent opening formed on the semiconductor substrate, and using the first resist pattern as a mask to pass through the thin film region and not through the thick film region Forming a first ion-implanted layer in the semiconductor substrate such that a lower layer of the thin film region is shallower than a lower layer of the opening in the semiconductor substrate.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the first ion-implanted layer is a p-type ion-implanted layer or an n-type ion-implanted layer;
After the step, a third step of removing the first resist pattern is performed.
Forming a second resist pattern having a thin film region and a thick film region and having an opening formed adjacent to the thin film region, and covering the first ion-implanted layer with the thick film region. Performing ion implantation of a second impurity having a conductivity type opposite to that of the first impurity so as to transmit through the thin film region and not transmit through the thick film region using the second resist pattern as a mask, A fifth step of forming a second ion-implanted layer on the semiconductor substrate so that the lower layer of the thin film region is shallower than the lower layer of the opening; and performing a heat treatment on the semiconductor substrate to form the first and second ion-implanted layers. And a sixth step of forming the first and second wells by diffusing the ion-implanted layer.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the first step, a reticle having a region in which a light-transmitting portion and a light-shielding portion are alternately formed in a width less than a minimum resolution of an exposure device. The thin film region is formed by light lithography using light rays transmitted through the region.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the fourth step, a reticle having a region in which a transmissive portion and a light-shielding portion are alternately formed with a width smaller than the minimum resolution of the exposure apparatus. The thin film region is formed by light lithography using light rays transmitted through the region.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the first step, photolithography is performed using a reticle having a region composed of a halftone pattern of thin-film chromium or molybdenum silicon, The light beam transmitted through the region forms the thin film region.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the fourth step, photolithography is performed using a reticle having a region composed of a halftone pattern of thin-film chromium or molybdenum silicon, The light beam transmitted through the region forms the thin film region.

[0025]

According to the present invention, a portion of a reticle used for photolithography has a transmissive portion and a light-shielding portion alternately having a width equal to or less than the minimum resolution of the exposure apparatus. When this region is exposed, the ratio of the resist exposed to light can be reduced to less than 100% because the width of the transmission portion is formed to be equal to or less than the minimum resolution.
Also, since the diffracted light from the transmissive portions adjacent to the left and right is generated in the light-shielding portion, the amount of exposure can be made equal to that of the transmissive portion by overlapping these diffracted lights.

In the present invention, a partial region of the reticle used for photolithography is formed of a halftone pattern of a thin film of chromium (Cr), molybdenum silicon (Mo-Si), or the like. Therefore,
Assuming that the exposure energy of the normal exposure photosensitive area is 100%, the exposure energy of less than 100% is irradiated below these areas.

Therefore, the thickness of the resist pattern formed under these regions is 100%
The resist pattern is formed thinner than the remaining resist pattern.

Thus, a thin film region and a thick film region can be formed in the resist pattern. At the time of ion implantation for forming a well, the resist pattern in which the thick film region, the thin film region, and the opening adjacent to the thin film region are formed is used as a mask under conditions that allow impurities to pass through the resist pattern in the thin film region. Perform ion implantation. This allows
Since there is no barrier for impurity implantation in the lower layer of the opening, a deep bottom well is formed, and in the lower layer of the thin film region, the energy of the implantation is absorbed, so that a shallow bottom well can be formed. Since the resist pattern acts as a stopper in the thick film region, the underlying semiconductor substrate can be protected without ion-implanting impurities into the semiconductor substrate.

[0029]

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. 1 and 2 are schematic cross-sectional views showing a method of manufacturing an nMOS transistor and a pMOS transistor on a twin-well structure composed of an n-well and a p-well in the order of steps.

First, prior to the formation of a well, a field oxide film is formed on a semiconductor substrate by a so-called LOCOS (selective oxidation) method to perform element isolation.

That is, as shown in FIG. 1A, the silicon oxide film 2 is formed on the silicon semiconductor substrate 1 by a dry oxidation method or a pyrogenic method of burning water to generate water and oxidize it. It is formed to a thickness of about 300 °. This silicon oxide film 2 is a silicon nitride film 3
Plays the role of a pad when forming the semiconductor device. After that, the silicon nitride film 3 functioning as a mask at the time of selective oxidation is formed by low pressure chemical vapor deposition (LPCVD) or the like to have a thickness of 1,000 to 150 nm.
It is formed to a thickness of about 0 °.

The silicon oxide film 2 and the silicon nitride film 3
Determines the amount of bird's beak at the element isolation end of the field oxide film during oxidation by the LOCOS method, but does not directly relate to the essence of the present invention. Is possible.

Subsequently, a resist pattern having an opening formed in the element isolation region is formed by photolithography, and the silicon nitride film 3 in the element isolation region is etched by dry etching. As an example, CF ₄
The silicon nitride film 3 is selectively removed by chemical dry etching using a mixed atmosphere of / O ₂ / N ₂ .

Next, as shown in FIG. 1B, a field oxide film 4 having a thickness of about 5,000 to 7000 ° is formed at an oxidation set temperature of about 950 to 1000 ° C. by a pyrogenic method or the like. Thereby, the field oxide film 4
Of the element active regions 19 and 2
0 is defined.

The above-described steps are performed in the same manner as in the prior art.
4 shows a selective oxidation method using the S method. The feature of the present invention resides in the steps shown in FIG. 1C and thereafter, which will be described in detail below.

As shown in FIG. 1C, the element active region 1
A silicon oxide film 5 having a thickness of about 100 ° is formed on the surface of the silicon semiconductor substrate 1 at the surface of the silicon semiconductor substrate 9 by a dry oxidation method or a pyrogenic method of generating and oxidizing water by burning hydrogen. The silicon oxide film 5 can prevent damage to the silicon semiconductor substrate 1 due to ion implantation at the time of forming a well, and can also prevent out-diffusion (out diffusion) at the time of well diffusion processing by high-temperature heat treatment.

Then, resist patterns 7a and 7b are formed in the element active regions 19 and 20 by photolithography prior to ion implantation for forming p-wells.

FIG. 1C shows a reticle 6 used for this photolithographic exposure. When forming a p-well, reticle 6 is a non-transmissive region 6a in which an n-well region, which is a non-ion-implanted region other than the p-well forming region, is entirely covered with chromium.

The gate electrode forming region in the p-well forming region has a semi-transmissive region 6b composed of a plurality of light-shielding portions (lines) and a transmissive portion (space) having dimensions smaller than the limit resolution of the exposure apparatus. Have been. The p-well formation region other than the gate electrode formation region is a transmission region 6c.

This reticle 6, which is one of the features of the present invention,
3 will be described with reference to FIG. 3 taking the case of photolithography using a positive resist as an example.

As shown in FIG. 3A, the light intensity applied to the resist is 0% in a light-shielded area covered with chromium as in the non-transmissive area 6a described above. 100% remains without being exposed.

As shown in FIG. 3B, a transmission portion having a size (D ₁ ) larger than the limit resolution of the exposure apparatus is provided at the center of the same size as the light-shielding region width (gate width) in FIG. When the (space) is provided, the size of the light shielding area is also set to be equal to or greater than the limit resolution, and as a result, the light shielding area is 100%
The resist film remains, and the space between the light-shielding regions has a resist remaining film of 0%.

However, as shown in FIG. 3C, when the line width of the light-shielding region and the space sandwiched between the light-shielding regions are set to dimensions (D ₂ ) equal to or less than the limit resolution of the exposure apparatus, light-shielding Since the light intensity of the space between the regions is set to be equal to or smaller than the critical resolution, the light intensity applied to the resist does not reach 100%.

The light-shielded area shown in FIG. 3C has the light intensity shown by the solid line due to the influence of the diffracted light from the large and small space areas located on both sides, and the resist film has a thickness of 100%.
% Does not remain.

Therefore, by disposing the structure shown in FIG. 3C within the dimensions of the gate width in FIG. 4, it is possible to obtain the light intensity distribution and the resist residual film distribution shown by the solid line in FIG. That is, as shown in FIG. 4, by setting the light-shielding region and the space between the light-shielding regions, it is possible to form a resist pattern having a thin remaining film in the range of the gate width.

The control of the remaining resist film shown in FIGS. 3C and 4 can be arbitrarily set depending on the exposure energy and the width to be formed. FIG. 5 shows the remaining resist film thickness with respect to the exposure amount depending on each space width (D ₂ ) when the resist coating film thickness is set to 1.0 μm using an exposure apparatus for g-line wavelength.

In order to obtain the same resist remaining film, it is preferable that the space width and the exposure amount are arbitrarily set by obtaining the correlation shown in FIG. 5 in the exposure apparatus used.

As described above, by using the reticle 6 having the non-transmission area 6a, the semi-transmission area 6b, and the transmission area 6c,
As shown in FIG. 1C, a thick-film resist pattern 7a is formed on the n-well formation region as a blocking film at the time of ion implantation, and a thin-film resist pattern 7b is formed on the gate electrode formation region in the p-well formation region. Thin film resist pattern 7
An opening can be formed adjacent to both sides of b.

Here, the width dimension of the resist pattern 7b in the gate electrode formation region is desirably set to the following dimension A in consideration of misalignment at the time of exposure and lateral diffusion at the time of well diffusion by heat treatment. B ≦ A ≦ C Here, A: resist pattern dimension in the gate region portion B: gate electrode dimension in design C: alignment deviation (3σ value) generated in the photolithography process of forming the gate electrode.

Next, as shown in FIG. 1D, ion implantation for forming a p-well is performed. At this time, ion implantation is performed with the acceleration energy set to pass through the thin film resist pattern 7b in the gate electrode formation region. In particular,
When the thick resist pattern 7a has a thickness of about 1.2 μm and the thin resist pattern 7b has a thickness of about 0.3 μm, boron (B) is used as an impurity, acceleration energy is about 150 KeV, and dose is 9. 0 × 10 ¹¹
The ion implantation is performed under the condition of about / cm ² .

When ion implantation is performed under these conditions, impurities are implanted into the silicon semiconductor substrate 1 at a depth of about Rp = 4205 °, and are distributed in a range of about {Rp = 834}.

The resist film is almost the same as the case of the silicon semiconductor substrate 1. On the other hand, the silicon oxide film is implanted at a depth of about Rp = 4434 °,
Rp is distributed in a range of about 851 °.

Therefore, as a result, boron is not implanted into the portion where the thick-film resist pattern 7a is covered, but is slightly implanted into the gate forming region where the thin-film resist pattern 7b is formed. Then, ion implantation is performed as usual on a region not covered with the thick film resist pattern 7a and the thin film resist pattern 7b. Therefore, as shown in FIG. 1D, a shallow ion implantation layer 17a is formed in the gate formation region, and deep ion implantation is performed on both sides of the gate formation region, that is, a region where the source / drain diffusion layers are formed later. The layer 17b will be formed.

Next, as shown in FIG. 2A, after removing the resist patterns 7a and 7b, resist patterns 8a and 8b for forming an n-well in an n-well formation region are formed.
Is formed using the same method as the formation of the resist patterns 7a and 7b. That is, the ion implantation layers 17a and 17b in the p-well formation region are
a, and the gate formation region in the n-well formation region is covered with the thin-film resist pattern 8b.

Next, ion implantation for forming an n-well is performed using the resist patterns 8a and 8b as a mask.
Here, phosphorus (P) which is an impurity of a conductivity type opposite to that of boron (B) described above is ion-implanted. At this time, ion implantation is performed with the acceleration energy set to pass through the thin film resist pattern 8b in the gate electrode formation region. Specifically, when the thick-film resist pattern 8a is formed to have a thickness of about 1.0 μm and the thin-film resist pattern 8b is formed to have a thickness of about 0.12 μm, phosphorus (P) is used as an impurity, and the acceleration energy is about 150 KeV. , Dose amount 1.5 × 10 ¹³ / c
Ion implantation is performed under conditions of about m ² .

When ion implantation is performed under these conditions, impurities are implanted into the silicon semiconductor substrate 1 at a depth of about Rp = 1888 °, and are distributed in a range of about {Rp = 628}.

The resist film is almost the same as that of the silicon semiconductor substrate 1. On the other hand, the silicon oxide film is implanted at a depth of about Rp = 1535 °,
Rp is distributed in a range of about 461 °.

Therefore, as a result, phosphorus (P) is not implanted into the portion covered with the thick film resist pattern 8a, and a slight implantation is made into the gate forming region where the thin film resist pattern 8b is formed. . Then, the regions not covered with the thick film resist pattern 8a and the thin film resist pattern 8b are subjected to ion implantation as usual. Therefore, as shown in FIG. 2A, a shallow ion implantation layer 18a is formed in the gate formation region, and deep ion implantation is performed on both sides of the gate formation region, that is, a region where the source / drain diffusion layers are formed later. The layer 18b will be formed.

Next, as shown in FIG. 2B, heat treatment is performed at a temperature of about 1150 ° C. in an N ₂ atmosphere for about 6 hours in order to diffuse the ion-implanted layers 17a, 17b, 18a and 18b. Thereby, the p well 9 and the n well 10
To complete the twin well structure consisting of Then, by the above-described manufacturing process, these p-well 9 and n-well 1
It is possible to form a structure in which a shallow well layer is selectively formed only in the zero gate electrode formation region.

Next, as shown in FIG. 2C, after a gate oxide film is formed on the surfaces of the p-well 9 and the n-well 10,
A polycrystalline silicon film doped with impurities is formed by a CVD method, and is patterned into a gate electrode shape. Thereafter, a pair of impurity diffusion layers 1 serving as source / drain diffusion layers are formed in each well surface region on both sides of the gate electrode.
3 and 14 are formed. Thus, an nMOS transistor formed in the p well 9 and a pMOS transistor formed in the n well 10 are completed.

As described above, in the first embodiment, the semi-transmissive region 6a, the semi-transmissive portion (line) constituted by a plurality of light-shielding portions (lines) having a limit resolution or less of the exposure device and the transmissive portion (space). Photolithography is performed using a reticle having the region 6b and the transmission region 6c.

At this time, since the transmissive portion (space) in the semi-transmissive region 6b is formed with the minimum resolution or less,
The light exposure of the resist can be reduced. Further, in the light-shielding portion (line), diffracted light is generated from the transmissive portion (space) adjacent to the left and right, so that the amount of exposure equivalent to that of the transmissive portion (space) can be obtained by overlapping these diffracted lights.

As a result, the thick film resist pattern 7a (8a) and the thin film resist pattern 7b (8
b) can be formed simultaneously. Then, ion implantation of impurities is performed so as not to transmit the thick resist pattern 7a (8a) but to transmit the thin resist pattern 7b (8b).
(8b) A well structure having a shallow lower layer can be formed.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 and FIG.
nM on twin-well structure consisting of n-well and p-well
FIG. 7 is a schematic cross-sectional view showing a method for manufacturing an OS transistor and a pMOS transistor in the order of steps. 6 and 7
In FIG. 7, the same reference numerals are given to components and the like that are substantially the same as those in the first embodiment.

First, prior to the formation of a well, a field oxide film is formed on a semiconductor substrate by a so-called LOCOS method to perform element isolation.

That is, as shown in FIG. 6A, the silicon oxide film 2 is formed on the silicon semiconductor substrate 1 by dry oxidation or by a pyrogenic method of burning water to generate water and oxidize it. It is formed to a thickness of about 300 °. The silicon oxide film 2 serves as a pad when forming a silicon nitride film. After that, the silicon nitride film 3 functioning as a mask at the time of selective oxidation is formed by low pressure chemical vapor deposition (LPCVD) method or the like for 1000 to 1500.
It is formed to a thickness of about Å.

Subsequently, a resist pattern having an opening formed in the element isolation region is formed by photolithography, and the silicon nitride film 3 in the element isolation region is etched by dry etching. As an example, CF ₄ /
The silicon nitride film 3 is selectively removed by chemical dry etching using a mixed atmosphere of O ₂ / N ₂ .

Next, as shown in FIG. 6B, a field oxide film 4 having a thickness of about 5,000 to 7000 ° is formed at an oxidation set temperature of about 950 to 1000 ° C. by a pyrogenic method or the like. Thereby, the field oxide film 4
Of the element active regions 19 and 2
0 is defined.

Next, as shown in FIG. 6C, the surface of the silicon semiconductor substrate 1 on the surface of the element active regions 19 and 20 is subjected to dry oxidation or pyro-combustion of hydrogen to generate and oxidize water. A silicon oxide film 5 having a thickness of about 100 ° is formed by a genic method or the like. The silicon oxide film 5 can prevent damage to the silicon semiconductor substrate 1 due to ion implantation at the time of forming a well, and can also prevent out-diffusion (out diffusion) at the time of well diffusion processing by high-temperature heat treatment.

The resist patterns 7a and 7b are formed in the element active regions 19 and 20 by photolithography prior to the ion implantation for forming the p-well.

FIG. 6C shows a reticle 16 used for this photolithographic exposure. The reticle 16 has a p-well region as a transmission region 16c, and an n-well formation region other than a p-well formation region, which is a non-ion implanted region, entirely covered with chromium.
6a.

The gate electrode formation region in the p-well formation region has a halftone pattern 16b of thin film chromium (Cr), molybdenum silicon (Mo-Si), or the like used in the phase inversion technique or the like.

That is, in reticle 16, the n-well formation region is a light-shielding region, the gate electrode formation region of the p-well formation region is a semi-transmission region, and the other p-well formation regions are transmission regions. Then, photolithography exposure is performed using the reticle 16.

Thereafter, by performing development, FIG.
As shown in (c), a thick film resist pattern 7a is formed on the n-well formation region as a blocking film at the time of ion implantation,
The thin film resist pattern 7b is formed in the gate electrode formation region in the p well formation region, and openings can be formed adjacent to both sides of the thin film resist pattern 7b.

Here, as in the first embodiment, the width dimension of the resist pattern 7b in the gate electrode formation region is set to the following dimension in consideration of misalignment during exposure and lateral diffusion during well diffusion by heat treatment. It is desirable to set to A. B ≦ A ≦ C Here, A: resist pattern dimension in the gate region portion B: gate electrode dimension in design C: alignment deviation (3σ value) generated in the photolithography process of forming the gate electrode.

Next, as shown in FIG. 6D, ion implantation for forming a p-well is performed. At this time, ion implantation is performed with the acceleration energy set to pass through the thin film resist pattern 7b in the gate electrode formation region. In particular,
When the thick resist pattern 7a has a thickness of about 0.8 μm and the thin resist pattern 7b has a thickness of about 0.4 μm, boron (B) is used as an impurity, acceleration energy is about 150 KeV, and dose is 9. 0 × 10 ¹¹
The ion implantation is performed under the condition of about / cm ² .

When ion implantation is performed under these conditions, impurities are implanted into the silicon semiconductor substrate 1 at a depth of about Rp = 4205 ° and distributed in a range of about {Rp = 834}.

The resist film is almost the same as the case of the silicon semiconductor substrate 1. On the other hand, the silicon oxide film is implanted at a depth of about Rp = 4434 °,
Rp is distributed in a range of about 851 °.

Therefore, as a result, boron is not implanted into the portion covered with the thick-film resist pattern 7a, but is slightly implanted into the gate forming region where the thin-film resist pattern 7b is formed. Then, regions not covered with the resist patterns 7a and 7b are subjected to ion implantation as usual. Therefore, as shown in FIG. 6D, a shallow ion implantation layer 17a is formed in the gate formation region.
Is formed, and a deep ion-implanted layer 17b is formed on both sides of the gate formation region, that is, in a region where a source / drain diffusion layer is formed later.

Next, as shown in FIG. 7A, after removing the resist patterns 7a and 7b, resist patterns 8a and 8b for forming an n-well in an n-well formation region are formed.
Is formed using the same method as the formation of the resist patterns 7a and 7b. That is, the entire area other than the n-well formation area was covered with chromium, the gate electrode formation area in the n-well formation area was formed with a halftone pattern, and the area other than the gate electrode formation area in the n-well formation area was set as a transmission section. Photolithography exposure is performed using a reticle.

As a result, the ion-implanted layers 17a and 17b in the p-well formation region are changed to the thick resist pattern 8a.
And a resist pattern is formed so as to cover the gate formation region in the n-well formation region with the thin-film resist pattern 8b.

Next, ion implantation for forming an n-well is performed using the resist patterns 8a and 8b as a mask.
Here, phosphorus (P) which is an impurity of a conductivity type opposite to that of boron (B) described above is ion-implanted. At this time, ion implantation is performed with the acceleration energy set to pass through the thin film resist pattern 8b in the gate electrode formation region. Specifically, when the thick-film resist pattern 8a is formed to have a thickness of about 0.4 μm and the thin-film resist pattern 8b is formed to have a thickness of about 0.2 μm, phosphorus (P) is used as an impurity and an acceleration energy of about 150 KeV. , Dose amount 1.5 × 10 ¹³ / cm
Ion implantation is performed under about ² conditions.

When ion implantation is performed under these conditions, impurities are implanted into the silicon semiconductor substrate 1 at a depth of about Rp = 1888 °, and are distributed in a range of about {Rp = 628}.

The resist film is almost the same as the case of the silicon semiconductor substrate 1. On the other hand, the silicon oxide film is implanted at a depth of about Rp = 1535 °,
Rp is distributed in a range of about 461 °.

Therefore, as a result, phosphorus (P) is not implanted into the portion covered with the thick film resist pattern 8a, and a slight implantation is made into the gate forming region where the thin film resist pattern 8b is formed. . Then, regions not covered with the resist patterns 8a and 8b are subjected to ion implantation as usual. Therefore, as shown in FIG. 7A, a shallow ion implantation layer 18 is formed in the gate forming region.
a is formed, and a deep ion-implanted layer 18b is formed on both sides of the gate forming region, that is, in a region where a source / drain diffusion layer is formed later.

Next, as shown in FIG. 7B, in order to diffuse the ion-implanted layers 17a, 17b, 18a and 18b, a heat treatment is performed at a temperature of about 1150 ° C. in an N ₂ atmosphere for about 6 hours. Thereby, the p well 9 and the n well 10
To complete the twin well structure consisting of Then, by the above-described manufacturing process, these p-well 9 and n-well 1
It is possible to form a structure in which a shallow well layer is selectively formed only in the zero gate electrode formation region.

Next, as shown in FIG. 7C, after a gate oxide film is formed on the surfaces of the p well 9 and the n well 10,
A polycrystalline silicon film doped with impurities is formed by a CVD method, and is patterned into a gate electrode shape. Thereafter, a pair of impurity diffusion layers 13 and 1 serving as source / drain diffusion layers are formed in each well surface region on both sides of the gate.
4 is formed. Thereby, n formed in p well 9
MOS transistor, pMO formed in n well 10
The S transistor is completed.

As described above, in the second embodiment, the non-transmissive region 16a, the thin film chromium (Cr) used in the phase inversion technique and the like, the molybdenum silicon (Mo-S
Photolithography is performed using a reticle having a halftone pattern 16b according to i) and the like and a transmission region 16c.

At this time, in the halftone pattern 16b, the exposure of the resist can be reduced.
Therefore, it is possible to form a resist pattern having a thickness smaller than that of the resist pattern formed in the non-transmissive region 16a where light is completely shielded.

As a result, the thick film resist pattern 7a (8a) and the thin film resist pattern 7b (8
b) can be formed simultaneously. Then, ion implantation of impurities is performed so as not to transmit the thick resist pattern 7a (8a) but to transmit the thin resist pattern 7b (8b).
(8b) A well structure having a shallow lower layer can be formed.

[0091]

According to the present invention, in a semiconductor device having a twin well structure, each well can have a structure in which a region for forming a gate electrode is formed shallower than the periphery. Therefore, the gate depletion capacitance can be reduced, the sub-threshold characteristics can be improved, and the junction leak current can be reduced. This allows
A method for manufacturing a semiconductor device which achieves low power consumption and high speed can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps, following FIG. 1;

FIG. 3 is a diagram illustrating a method for forming a resist pattern of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a method for forming a resist pattern of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a characteristic diagram showing a relationship between an exposure amount of a resist pattern and a remaining film thickness of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 7 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps, following FIG. 6;

FIG. 8 is a schematic sectional view showing an example of a conventional semiconductor device.

FIG. 9 is a schematic sectional view showing another example of a conventional semiconductor device.

FIG. 10 is a schematic sectional view showing a problem in a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2, 5 Silicon oxide film 3 Silicon nitride film 6, 16 Reticle 6a, 16a Non-transmission area 6b Semi-transmission area 6c, 16c Transmission area 7a, 8a Thick resist pattern 7b, 8b Thin resist pattern 9 p-well 10 n well 13, 14 impurity diffusion layer 16b halftone pattern 17a, 18a shallow ion implantation layer 17b, 18b deep ion implantation layer 19, 20 device active region

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device having a well structure on a semiconductor substrate, comprising: a first resist pattern having a thin film region and a thick film region, wherein an opening is formed adjacent to the thin film region. Forming a first impurity on the semiconductor substrate, and performing ion implantation of a first impurity using the first resist pattern as a mask so as to transmit through the thin film region and not through the thick film region, Forming a first ion-implanted layer on the substrate such that the lower layer of the thin film region is shallower than the lower layer of the opening. 2. The method according to claim 1, wherein the first ion implantation layer is a p-type ion implantation layer or an n-type ion implantation layer, and after the second step, a third step of removing the first resist pattern. Forming a second resist pattern having a thin film region and a thick film region and an opening formed adjacent to the thin film region, and covering the first ion implantation layer with the thick film region. Performing a step of ion-implanting the first impurity and a second impurity of the opposite conductivity type so as to transmit through the thin film region and not transmit through the thick film region using the second resist pattern as a mask;
A fifth step of forming a second ion-implanted layer on the semiconductor substrate such that a lower layer of the thin film region is shallower than a lower layer of the opening, and performing a heat treatment on the semiconductor substrate to form the first and second ion-implanted layers. 6. The method according to claim 1, further comprising: a sixth step of diffusing the second ion-implanted layer to form first and second wells. 3. In the first step, photolithography is performed using a reticle having an area in which a light-transmitting part and a light-shielding part are alternately formed with a width equal to or less than the minimum resolution of the exposure apparatus, and the light is transmitted through the area. 3. The method according to claim 1, wherein the thin film region is formed by a light beam. 4. In the fourth step, photolithography is performed using a reticle having an area in which a light-transmitting portion and a light-shielding portion are alternately formed with a width equal to or less than the minimum resolution of the exposure apparatus, and the light is transmitted through the region. 4. The method according to claim 2, wherein the thin film region is formed by a light beam. 5. In the first step, photolithography is performed using a reticle having a region composed of a halftone pattern of thin film chromium or molybdenum silicon, and the thin film region is formed by light transmitted through the region. The method for manufacturing a semiconductor device according to claim 1, wherein: 6. In the fourth step, photolithography is performed using a reticle having a region composed of a halftone pattern of thin film chromium or molybdenum silicon, and the thin film region is formed by light beams transmitted through the region. The method for manufacturing a semiconductor device according to claim 2, wherein: