JPH0463435A - Semiconductor device and manufacture of same - Google Patents

Abstract

PURPOSE:To prevent a gate oxide film under a gate electrode from becoming defective and obtain a high-operation-reliability MOSFET by forming high- concentration impurity regions in contact with low-concentration impurity regions with the boundaries between them at the edges of the gate electrode. CONSTITUTION:High-concentration impurity regions 15 in contact with low- concentration impurity regions 12 composing sources or drains are formed with the boundaries between them at the edges 14a of a gate electrode 14. That is, the low-concentration impurity regions 12 are formed by implanting ions vertically, a gate oxide film and the gate electrode 14 are formed, and the high-concentration impurity regions 15 are formed. Thereby the gate oxide film under the gate electrode is free from a defect, the quality of the film is not decreased by heat treatment, and a high-operation-reliability LDD transistor is obtained.

Description

[Detailed description of the invention] [Summary] L D D (lightly doped dry
n) Regarding the MOSFET structure and its manufacturing method, the purpose is to prevent the formation of defects in the gate oxide film under the gate electrode and to obtain a MOSFET with high operational reliability. A structure is adopted in which a high concentration impurity region is formed in contact with a low concentration impurity region constituting the drain, and in the manufacturing process 17, after forming an insulating film on the semiconductor substrate, a step of forming a gate electrode dummy pattern on the surface thereof, and a step of forming a gate electrode dummy pattern on the surface thereof. A process of forming a low concentration impurity region by performing vertical ion implantation using the electrode dummy pattern as a mask, removing the insulating film and the gate electrode dummy pattern, and depositing a layer on the semiconductor substrate with a width wider than the gate oxide film and the gate electrode dummy pattern. The method includes a step of forming a gate electrode with a large impurity concentration, and a step of performing vertical ion implantation using the gate electrode as a mask to form a high concentration impurity region.

[Industrial application field]

The present invention relates to an LDD structure MOSFET and a method for manufacturing the same.

In recent years, there has been a demand for miniaturization of transistors used in LSIs, and this trend is expected to become even stronger in the future. Such miniaturization causes problems such as variations in threshold voltage V TH and mutual conductance due to hot electrons, and therefore it is necessary to suppress the pot electron effect. Therefore, LDD (LDD) transistors, which have low concentration impurity diffusion regions as part of the source and drain, have come to be used to alleviate the high electric field that causes the breakdown voltage to drop due to hot electrons. In this case, it is known that high electric field concentration can be more alleviated by forming a low concentration impurity diffusion region or by forming the region so as to overlap the region below the gate electrode.

[Conventional technology]

FIG. 2 shows a manufacturing process diagram of a conventional example. In the same figure (A), several thousand isolation regions 2 are formed on a P-type silicon substrate 1 (semiconductor substrate) using the normal LOGO3 process.
After forming the gate oxide film 3 (silicon oxide)
000 electrodes are formed, and several thousand gate electrodes 4 of polycrystalline silicon are further formed on the surface thereof.

Next, in the same figure (B), ions are implanted in an oblique direction using the gate electrode 4 as a mask.
T! -2) to form the low concentration impurity region 5. This oblique ion implantation is performed to form the low concentration impurity region 5 so as to overlap the gate electrode 4.

Subsequently, as shown in the same figure (C), a silicon oxide film 6 is formed on the surface.
' (dashed line), and then anisotropic etching is performed to form sidewall portions 6 on both sides of the gate electrode 4 with a width of 0.2 μm to 0.2 μm.
Other parts are removed so that about 4 μm remains. Next, the same figure (
As shown in D), a high concentration impurity region is formed by vertical ion implantation (the high concentration impurity is arsenic of the opposite conductivity type to the substrate 1, for example, and the dose is 1016 cm-2 or less) using the gate electrode 4 and the side wall portion 6 as a mask. form 7. Next, the same figure (E
), several hundred interlayer insulating films 8 such as PSG are used.
Electrode windows 8a are formed by one person, and several thousand wiring metals 9, such as aluminum-19 alloy, are formed therein by patterning.

C Problems to be Solved by the Invention] During the oblique ion implantation shown in FIG. 2(B), as shown in FIG. At this time, either a defect indicated by an x mark is generated in the gate oxide film 3, or a defect is caused in the gate oxide film 3, since the ion implantation is performed in an oblique direction as shown in FIG. It also exists in the gate oxide film 3 of.

For this reason, the film quality of the gate oxide film 3 under the gate electrode 4 deteriorates due to stress caused by subsequent heat treatment, resulting in problems such as deterioration of transistor characteristics and lower reliability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that prevents defects from occurring in a gate oxide film under a gate electrode and has high operational reliability, and a method for manufacturing the same.

[Means to solve the problem]

The above problem is solved by a semiconductor device characterized in that a high concentration impurity region is formed in contact with a low concentration impurity region constituting the source or drain, with the edge portion of the gate electrode as the boundary. Further, after forming an insulating film on the semiconductor substrate, a step of forming a gate electrode dummy pattern on the surface thereof, and a step of performing vertical ion implantation using the gate electrode dummy pattern as a mask to form a low concentration impurity region, The insulating film and gate electrode dummy pattern are removed, and a gate electrode with a width larger than the gate oxide film and gate electrode dummy pattern is formed on the semiconductor substrate. Vertical ion implantation is performed using the gate electrode as a mask to increase the height. The problem is solved by a method of manufacturing a semiconductor device, which is characterized by including a step of forming a concentrated impurity region.

[Effect]

In the present invention, after forming a low concentration impurity region by vertical ion implantation, a gate oxide film and a gate electrode are newly formed to form a high concentration impurity region. No defects will occur.

〔Example〕

FIG. 1 shows a manufacturing process diagram of an embodiment of the present invention.

In the same figure (A), LOCO is placed on the P-type silicon substrate 1.
The element isolation region 2 is formed using three steps, then several hundred insulating films 10 (for example, oxide films) are formed on the other parts, and then a resist film 11 (for gate electrodes) is formed on the surface of the insulating film 10. dummy pattern). In this case, the width of the resist film 11 is made to be slightly larger than the effective channel length, assuming that the effective channel length of the transistor is shortened by the heat treatment during the formation of the gate oxide film in FIG. to form. Next, the same figure (B
), vertical ion implantation is performed using the resist film 11 as a mask (the low concentration impurity is, for example, phosphorus, and the dose is 1).
Low concentration impurity region 1 due to 013~10"am-2)
form 2.

Subsequently, the resist film 11 and the insulating film 1 shown in FIG.
0 is removed, and then, as shown in FIG.
Form 000 people. In this case, the gate electrode 14 is formed so that its radius is the sum of the width of the gate electrode 4 and the side wall portion 6 in the conventional example shown in FIG.

Next, in the same figure (D), vertical ion implantation is performed using the gate electrode 14 as a mask (the high concentration impurity is, for example, arsenic).
The high concentration impurity region 15 is formed using a high concentration impurity region 15 (dose amount is 10"an-2 or less). Due to this vertical ion implantation, defects are generated in the gate oxide film 13 on the high concentration impurity region 15, or defects are formed under the gate electrode 14. gate oxide film 1
3 has no defects. Next, in FIG. 5E, an interlayer insulating film 8 is formed, an electrode window 8a is opened, and a wiring metal 9 is patterned therein.

As shown in FIG. 2E, in the semiconductor device of the present invention, the gate electrode 14 is not provided with a sidewall portion unlike the conventional example, and a highly concentrated impurity region 15 is formed with the edge portion 14a of the gate electrode 14 as a boundary. is formed. Further, the gate oxide film 13 formed under the gate electrode 14 has no defects, and the film quality does not deteriorate even if heat treatment is performed.

〔Effect of the invention〕

As explained above, according to the present invention, no defects occur in the gate oxide film under the gate electrode, the film quality does not deteriorate even after heat treatment, and the L
DD) transistor can be obtained.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process diagram of an embodiment of the present invention, FIG. 2 is a manufacturing process diagram of a conventional example, and FIG. 3 is a diagram showing defects in the conventional example. In the figure, 0 is a silicon substrate (semiconductor substrate), 0 is an insulating film, 1 is a resist film (gate electrode dummy pattern 2 is a low concentration impurity region, 3 is a gate oxide film, 4 is a gate electrode, 4a is an edge part of the gate electrode, 5 indicates a high concentration impurity region. One＼−】

Claims (2)

[Claims] (1) A transistor in which a low concentration impurity region (12) constituting a source or drain is formed in a semiconductor region under the gate electrode (14).
4) A semiconductor device characterized in that a high concentration impurity region (15) is formed in contact with the low concentration impurity region with the edge portion (14a) as a boundary. (2) In manufacturing a transistor in which a low concentration impurity region (12) forming a source or drain is formed in a semiconductor region under a gate electrode (14), an insulating film (10) is formed on a semiconductor substrate (1). After that, there is a step of forming a gate electrode dummy pattern (11) on the surface, and a low concentration impurity region (12) is formed by performing vertical ion implantation using the gate electrode dummy pattern (11) as a mask.
a step of forming the insulating film (10) and the gate electrode dummy pattern (10);
1) and forming a gate oxide film (13) on the semiconductor substrate (1) and a gate electrode (14) having a width larger than the gate electrode dummy pattern (11); ) using a mask as a mask to perform vertical ion implantation to form a high concentration impurity region (15).