JPH0463176U - - Google Patents
Info
- Publication number
- JPH0463176U JPH0463176U JP10462690U JP10462690U JPH0463176U JP H0463176 U JPH0463176 U JP H0463176U JP 10462690 U JP10462690 U JP 10462690U JP 10462690 U JP10462690 U JP 10462690U JP H0463176 U JPH0463176 U JP H0463176U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- inner layer
- conductor pattern
- common inner
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 7
- 230000001788 irregular Effects 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
Description
第１図は本考案の第１の実施例の共通内層導体
パターンの平面図、第２図は本考案の第２の実施
例の共通内層導体パターンの平面図、第３図は従
来の多層印刷配線板の共通内層導体パターンの一
例の平面図である。
１１……回路構成とは無関係な回路、１２……
回路構成とは無関係なランド、１３，２３……内
層クリアランス、１４，２４……内層導通ランド
、１５，２５……銅箔部、１６，２６……共通内
層導体パターン、１７，１８……空白部。
Fig. 1 is a plan view of a common inner layer conductor pattern according to the first embodiment of the present invention, Fig. 2 is a plan view of a common inner layer conductor pattern according to the second embodiment of the present invention, and Fig. 3 is a plan view of a common inner layer conductor pattern according to the second embodiment of the present invention. FIG. 3 is a plan view of an example of a common inner layer conductor pattern of a wiring board. 11...Circuit unrelated to the circuit configuration, 12...
Land unrelated to the circuit configuration, 13, 23... Inner layer clearance, 14, 24... Inner layer conduction land, 15, 25... Copper foil part, 16, 26... Common inner layer conductor pattern, 17, 18... Blank Department.
Claims (1)
において、前記共通内層導体パターン中に回路構
成とは無関係な独立した回路を設け、該回路上に
ランドを不等間隔に設け、かつ、該ランドの当該
外層位置にランドを設けたことを特徴とする多層
印刷配線板。 In a multilayer printed wiring board having a common inner layer conductor pattern, an independent circuit unrelated to the circuit configuration is provided in the common inner layer conductor pattern, lands are provided at irregular intervals on the circuit, and the outer layer of the land is provided with an independent circuit unrelated to the circuit configuration. A multilayer printed wiring board characterized by having lands at certain positions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10462690U JPH0463176U (en) | 1990-10-04 | 1990-10-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10462690U JPH0463176U (en) | 1990-10-04 | 1990-10-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0463176U true JPH0463176U (en) | 1992-05-29 |
Family
ID=31849986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10462690U Pending JPH0463176U (en) | 1990-10-04 | 1990-10-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0463176U (en) |
-
1990
- 1990-10-04 JP JP10462690U patent/JPH0463176U/ja active Pending