JPH0462920A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0462920A JPH0462920A JP17423090A JP17423090A JPH0462920A JP H0462920 A JPH0462920 A JP H0462920A JP 17423090 A JP17423090 A JP 17423090A JP 17423090 A JP17423090 A JP 17423090A JP H0462920 A JPH0462920 A JP H0462920A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- insulating film
- conductive layer
- resist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要]
半導体装置のコンタク1−ホールの形成方法の改良に関
し、
L部導電層に発生する障害を簡単且つ容易に防止するこ
とが可能なコンタクトホールの形成方法の提供を目的と
し、
下部導電層と上部導電層との間に形成した絶縁膜に設け
るコンタクトホールの形成方法であって、前記下部導電
層の表面に形成した絶縁膜の表面にレジスト膜を形成す
る工程と、前記コンタクトホールを形成しようとする位
置におけるレジスト膜と前記絶縁膜との接触部への露光
がディフォーカスとなるように露光し、前記レジスト膜
を現像して開口窓の下部の側壁にテーパーを形成する工
程と、前記開口窓内の下部の側壁にテーパーが形成され
た前記レジスト膜をマスクとし、前記レジスト膜と前記
絶縁膜とを同時にエツチングして側面に順デーパを有す
るコンタクトホールを形成するする工程とを含むよう構
成する。[Detailed Description of the Invention] [Summary] Concerning an improvement in the method for forming a contact hole in a semiconductor device, the present invention relates to a method for forming a contact hole that can simply and easily prevent damage occurring in the L conductive layer. A method for forming a contact hole in an insulating film formed between a lower conductive layer and an upper conductive layer, the method comprising forming a resist film on the surface of the insulating film formed on the surface of the lower conductive layer. In the process, the contact portion between the resist film and the insulating film at the position where the contact hole is to be formed is exposed to light in a defocused manner, and the resist film is developed to form a side wall at the bottom of the opening window. a step of forming a taper, and using the resist film in which a taper is formed on the lower side wall of the opening window as a mask, simultaneously etching the resist film and the insulating film to form a contact hole having a tapered side surface. The structure includes a step of forming.
本発明は、半導体装置のコンタクトホールの形成方法の
改良に関するものである。The present invention relates to an improvement in a method for forming contact holes in semiconductor devices.
近年の下部導電層と上部導電層との間の絶縁膜にコンタ
クトホールを形成する方法としては、この絶縁膜を異方
性エツチングにより除去してコンタクトホールを形成す
る方法が採用されているが、半導体装置の高集積化に応
じる微細化に伴いコンタクトホールのアスペクト比が大
きくなり、異方性エツチングによる側壁が垂直なコンタ
クトホールでは、このコンタクトホールに形成した配線
のカバレッジが悪くなり、配線の断線や導電層間のコン
タクト不良が発生している。In recent years, a method of forming a contact hole in an insulating film between a lower conductive layer and an upper conductive layer has been adopted, in which the insulating film is removed by anisotropic etching to form a contact hole. The aspect ratio of contact holes has increased as semiconductor devices have become smaller due to higher integration, and contact holes with vertical sidewalls created by anisotropic etching have poor coverage of wiring formed in these contact holes, resulting in disconnection of wiring. or poor contact between conductive layers.
以上のような状況から、コンタクトホール内に形成した
配線層に断線やコンタクト不良が発生しない半導体装置
の製造方法が要望されている。Under the above circumstances, there is a need for a method of manufacturing a semiconductor device that does not cause disconnections or contact failures in wiring layers formed in contact holes.
従来の半導体装置の製造方法を第2図により工程順に詳
細に説明する。A conventional method for manufacturing a semiconductor device will be explained in detail step by step with reference to FIG.
まず第2図(a)に示すように、下部導電層11の表面
にCVD法によりシリコン酸化膜からなる絶縁膜12を
形成し、その表面にレジスト膜13を塗布して形成する
。First, as shown in FIG. 2(a), an insulating film 12 made of a silicon oxide film is formed on the surface of the lower conductive layer 11 by the CVD method, and a resist film 13 is applied to the surface.
つぎに第2図(b)に示すように、この絶縁膜12にコ
ンタクトホールを形成しようとする位置のレジスト膜1
3に絶縁膜12の表面に対して垂直な側壁を有する開口
窓13aをフォトリソグラフィー技術を用いて形成する
。Next, as shown in FIG. 2(b), a resist film 1 is placed at a position where a contact hole is to be formed in this insulating film 12.
3, an opening window 13a having a side wall perpendicular to the surface of the insulating film 12 is formed using photolithography technology.
ついで第2図(C)に示すように、レジスト膜13のエ
ツチングレートとこの絶縁膜12のエツチングレートと
の比、即ち、選択比の大きな異方性エツチングを行って
この絶縁膜12に垂直な側壁を有するコンタクトホール
14を形成する。Next, as shown in FIG. 2(C), anisotropic etching with a large ratio of the etching rate of the resist film 13 to the etching rate of the insulating film 12, that is, a high selectivity, is performed to form a pattern perpendicular to the insulating film 12. A contact hole 14 having side walls is formed.
最後に第2図(d)に示すように、コンタクトホール1
4の底面及び内壁から絶縁膜12の表面に延在するよう
に膜厚1.0μmのアルミニウムからなる上部導電層1
5をPVD法により形成する。Finally, as shown in FIG. 2(d), the contact hole 1
The upper conductive layer 1 made of aluminum and having a thickness of 1.0 μm extends from the bottom surface and inner wall of the insulating film 12 to the surface of the insulating film 12.
5 is formed by the PVD method.
以上説明した従来の半導体装置の製造方法においては、
下部導電層の表面の絶縁膜にこの絶縁膜の表面に対して
垂直な側壁を有するコンタクトホールを形成しているの
で、第3図に示すようにこのようなコンタクトホール1
4内に上部導電層15を形成すると、コンタクトホール
14のカドレッジが悪くなり、底面及び内壁から絶縁膜
12の表面に延在する上部導電層15と下部導電層11
とのコンタクトが悪くなり、上部導電層15の膜厚が薄
い部分では膜切れが生じて断線するという問題点があっ
た。In the conventional semiconductor device manufacturing method described above,
Since a contact hole having a side wall perpendicular to the surface of the insulating film is formed in the insulating film on the surface of the lower conductive layer, such a contact hole 1 is formed as shown in FIG.
If the upper conductive layer 15 is formed in the insulating film 12, the coverage of the contact hole 14 will be poor, and the upper conductive layer 15 and the lower conductive layer 11 extending from the bottom and inner wall to the surface of the insulating film 12 will deteriorate.
There was a problem in that the contact with the upper conductive layer 15 was poor, and in the thinner portions of the upper conductive layer 15, film breakage occurred and the wire was disconnected.
本発明は以上のような状況から、上部導電層に発生する
障害を簡単且つ容易に防止することが可能なコンタクト
ホールの形成方法の提供を目的としたものである。SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, the present invention aims to provide a method for forming a contact hole that can simply and easily prevent problems occurring in the upper conductive layer.
〔課題を解決するための手段]
本発明の半導体装置の製造方法は、下部導電層と上部導
電層との間に形成した絶縁膜に設けるコンタクトホール
の形成方法であって、この下部導電層の表面に形成した
絶縁膜の表面にレジスト膜を形成する工程と、このコン
タクトポールを形成しようとする位置におりるレジスト
膜とこの絶縁膜との接触部への露光がディフォーカスと
なるように露光し、このレジスト膜を現像して開口窓の
下部の側壁にテーパーを形成する工程と、この開口窓内
の下部の側壁にテーパーが形成されたこのレジス1〜膜
をマスクとし、このレジスト膜とこの絶縁膜とを同時に
エツチングして側面に順デーパを有するコンタクトホー
ルを形成するする工程とを含むよう構成する。[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention is a method for forming a contact hole in an insulating film formed between a lower conductive layer and an upper conductive layer, the method comprising: The process of forming a resist film on the surface of the insulating film formed on the surface, and the exposure so that the contact area between the resist film and this insulating film at the position where the contact pole is to be formed is defocused. Then, there is a step of developing this resist film to form a taper on the lower side wall of the opening window, and a step of developing this resist film and forming a taper on the lower side wall of the opening window. The structure includes a step of simultaneously etching this insulating film to form a contact hole having a tapered side surface.
即ち本発明においては、下部導電層の表面に絶縁膜を形
成し、その表面にレジス1−膜を形成し、コンタクトホ
ールを形成しようとする位置におけるレジスト膜とこの
絶縁膜との接触部への露光がディフォーカスとなるよう
に露光し、現像を行ってこのレジスト膜のコンタクトホ
ール内の下部の側壁にテーパーを形成するので、このコ
ンタクトホール内の下部の側壁にはテーパーが形成され
る。That is, in the present invention, an insulating film is formed on the surface of the lower conductive layer, a resist film is formed on the surface, and a contact portion between the resist film and this insulating film is formed at a position where a contact hole is to be formed. Exposure is performed so that the exposure is defocused, and development is performed to form a taper on the lower side wall of the contact hole in this resist film, so that a taper is formed on the lower side wall of the contact hole.
このレジスト膜をマスクとし、レジスト膜のエツチング
レートと絶縁膜のエラチングレー1〜との比が、このコ
ンタクトホールのテーパに等しい異方性のドライエツチ
ングにより絶縁膜をエツチングするから、絶縁1模が垂
直方向にエツチングされるのに応じて、レジス1〜膜の
テーパ部がエツチングされて開口窓が広くなり、コンタ
クトホールの内径が大きくなるので、絶縁膜に形成した
コンタクトホールの形状が上部の内径が底部の内径より
大きな順テーパのコンタクトホールを形成することが可
能となる。Using this resist film as a mask, the insulating film is etched by anisotropic dry etching in which the ratio of the etching rate of the resist film to the etching gray of the insulating film is equal to the taper of this contact hole, so that the insulation 1 pattern is vertical. As the resist 1 to the tapered part of the film is etched in this direction, the opening window becomes wider and the inner diameter of the contact hole becomes larger. It becomes possible to form a forward tapered contact hole that is larger than the inner diameter of the bottom.
以下第1図により本発明の一実施例を工程順に詳細に説
明する。Hereinafter, one embodiment of the present invention will be explained in detail in the order of steps with reference to FIG.
まず第1図(a)に示すように、下部導電層1の表面に
CVD法によりシリコン酸化膜からなる絶縁膜2を形成
し、その表面にレジスト膜3を塗布して形成する。First, as shown in FIG. 1(a), an insulating film 2 made of a silicon oxide film is formed on the surface of a lower conductive layer 1 by the CVD method, and a resist film 3 is applied to the surface.
つぎにコンタクトホールを形成しようとする位置におけ
るレジスト膜3とこの絶縁膜2との接触部への露光がデ
ィフォーカスとなるように露光し、現像後、第1図(b
)に示すように、このレジスト膜3の開口窓3a内の下
部の側壁にテーパーを形成する。Next, the contact area between the resist film 3 and the insulating film 2 at the position where the contact hole is to be formed is exposed to light in a defocused manner, and after development, as shown in FIG.
), a taper is formed on the lower side wall of the resist film 3 within the opening window 3a.
ついでレジスト膜3のエツチングレートとこの絶縁膜2
のエツチングレートとの比、即ち、選択比が形成しよう
とするコンタクトホール4のテーパと等しい下記の条件
の異方性のりアクティブ・イオン・エツチングを行う。Next, the etching rate of the resist film 3 and this insulating film 2
Anisotropic active ion etching is performed under the following conditions in which the ratio of the etching rate to the etching rate, that is, the selectivity is equal to the taper of the contact hole 4 to be formed.
反応ガスー−−−−−−−−−−−−CF4. CHF
3.アルゴン反応ガス流量−−−−−−−−−−−−
−−−−−−−−−−−−−1、100s CCM反応
室内圧−−−−−−−−−一−−−−−−−−−−−−
−−−−−−−−4,7Torr基板加熱温度−−−−
−−−−−−−−−−−−−−−−−−−−−−−−−
−−−−−−−−1、5°C高周波電源周波数−−−−
−−−−−−−−−−−−−−−−400KHz高周波
電源出力−−−−−−−−−−−−−−−−−−−−−
−−−−−−−−−−800Wこのようなりアクティブ
・イオン・エツチングにより絶縁膜2をエツチングする
と、第1図(C)に示すようにコンタクトホール4の底
部の内径が第1図(b)のレジスト膜3の開口窓3aの
スソ部の内径に等しく、絶縁膜2の表面の内径がレジス
ト膜3の開口窓3aの上部の内径に等しいテーパのつい
たコンタクトホール4が形成され、レジスト膜3を除去
するとコンタクトホール4の形成が完了する。Reaction gas ----------------------CF4. CHF
3. Argon reaction gas flow rate----------------------
------------1, 100s CCM reaction chamber pressure-----1-----------
---------4,7Torr substrate heating temperature----
−−−−−−−−−−−−−−−−−−−−−−−−−
-----------1, 5°C high frequency power supply frequency------
−−−−−−−−−−−−−−−−−400KHz high frequency power output−−−−−−−−−−−−−−−−−−−−−
---------- 800W When the insulating film 2 is etched by active ion etching in this way, the inner diameter of the bottom of the contact hole 4 is reduced as shown in FIG. 1(C). ), a tapered contact hole 4 is formed which is equal to the inner diameter of the base of the opening window 3a of the resist film 3 and whose inner diameter of the surface of the insulating film 2 is equal to the inner diameter of the upper part of the opening window 3a of the resist film 3. When the film 3 is removed, the formation of the contact hole 4 is completed.
このようにして形成されたコンタクトホール4の底面及
び内壁から絶縁膜2の表面に延在するようにアルミニウ
ムからなる上部導電層5をPVD法により形成すると、
第1図(d)に示すようになり、従来のコンタクトホー
ルにおいて生じていた上部導電層と下部導電層との接触
不良やに部導電層の膜切れ等の障害の発生を防止するこ
とが可能となる。When an upper conductive layer 5 made of aluminum is formed by the PVD method so as to extend from the bottom surface and inner wall of the contact hole 4 thus formed to the surface of the insulating film 2,
As shown in Figure 1(d), it is possible to prevent problems such as poor contact between the upper and lower conductive layers and film breakage of the conductive layer at the edges, which occur in conventional contact holes. becomes.
以上の説明から明らかなように本発明によれば、絶縁膜
のエツチングに用いるレジスト膜の開口窓の形状を異な
った形状に形成し、エツチング材料を選択することによ
り極めて簡単に順テーパの形状を有するコンタクトホー
ルを形成することが可能となる利点があり、著しい経済
的及び、信頼性向上の効果が期待できる半導体装置の製
造方法の提供が可能である。As is clear from the above description, according to the present invention, the shape of the opening window of the resist film used for etching the insulating film is formed into a different shape, and by selecting the etching material, a forward taper shape can be obtained very easily. It is possible to provide a method for manufacturing a semiconductor device which has the advantage of being able to form a contact hole having the same structure, and which can be expected to have significant economical and reliability improvement effects.
第1図は本発明による一実施例の半導体装置の製造方法
を工程順に示す側断面図、
第2図は従来の半導体装置の製造方法を工程順に示す側
断面図、
第3図は従来の半導体装置の製造方法の問題点を示ず側
断面図、である。
図において、
■は下部導電層、 2は絶縁膜、
3はレジスト膜、 3aは開口窓、
4はコンタクトホール、
5は上部導電層、を示す。
園
区FIG. 1 is a side sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps; FIG. 2 is a side sectional view showing a conventional method for manufacturing a semiconductor device in order of steps; FIG. 3 is a sectional view of a conventional semiconductor device. FIG. 3 is a side cross-sectional view showing the problem of the method of manufacturing the device; In the figure, (2) indicates a lower conductive layer, 2 indicates an insulating film, 3 indicates a resist film, 3a indicates an opening window, 4 indicates a contact hole, and 5 indicates an upper conductive layer. Park area
Claims (1)
た絶縁膜(2)に設けるコンタクトホール(4)の形成
方法であって、 前記下部導電層(1)の表面に形成した絶縁膜(2)の
表面にレジスト膜(3)を形成する工程と、前記コンタ
クトホール(4)を形成しようとする位置における前記
レジスト膜(3)と前記絶縁膜(2)との接触部への露
光がディフォーカスとなるように露光し、前記レジスト
膜(3)を現像して開口窓(3a)の下部の側壁にテー
パーを形成する工程と、前記開口窓(3a)内の下部の
側壁にテーパーが形成された前記レジスト膜(3)をマ
スクとし、前記レジスト膜(3)と前記絶縁膜(2)と
を同時にエッチングして側面に順デーパを有するコンタ
クトホール(4)を形成するする工程と、 を含むことを特徴とする半導体装置の製造方法。[Scope of Claims] A method for forming a contact hole (4) provided in an insulating film (2) formed between a lower conductive layer (1) and an upper conductive layer (5), comprising: ) of forming a resist film (3) on the surface of the insulating film (2) formed on the surface of the insulating film (2), and forming a resist film (3) and the insulating film (2) at the position where the contact hole (4) is to be formed. ) and developing the resist film (3) to form a taper on the lower side wall of the aperture window (3a); ) using the resist film (3) with a tapered lower side wall as a mask, the resist film (3) and the insulating film (2) are simultaneously etched to form a contact hole ( 4) A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17423090A JPH0462920A (en) | 1990-06-29 | 1990-06-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17423090A JPH0462920A (en) | 1990-06-29 | 1990-06-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0462920A true JPH0462920A (en) | 1992-02-27 |
Family
ID=15974999
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17423090A Pending JPH0462920A (en) | 1990-06-29 | 1990-06-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0462920A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013169001A (en) * | 2013-05-02 | 2013-08-29 | Fujitsu Ltd | Manufacturing method of line conductor |
-
1990
- 1990-06-29 JP JP17423090A patent/JPH0462920A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013169001A (en) * | 2013-05-02 | 2013-08-29 | Fujitsu Ltd | Manufacturing method of line conductor |
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