JPH0462625B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Fields> This invention is applicable to ordinary binarized 1-bit data.
CMI coded into a 2-bit block used for transmission signals, etc. based on a data signal such as NRZ (Non-Return-to-Zero code) and a coding rule violation signal that indicates violation of the coding rules of the data signal.
(coded mark inversion) has a code rule violation suitable for creating a coded signal.
Regarding CMI encoding circuit.

<Prior art> A CMI code is a type of 1B2B code that encodes a binarized 1-bit data signal into a 2-bit block. For example, in the case of a data signal "0", it is If the data signal is “1”, the immediately preceding data signal “1” is encoded into a block of bits, regardless of the data signal “0” that occurs in the middle.
A code encoded in blocks of "00" or "11" alternately. Furthermore, the above-mentioned violation of the CMI code code rule means that the data signal “0” is encoded into a block of “10”, and the data signal “1” is converted into a CMI code immediately before the data signal “1” is converted instead of alternately.
This means that the code is encoded as a block of consecutive "00" or "11".

Conventionally, there is a CMI encoding circuit as shown in FIG. In FIG. 7, 101,
102 and 103 are input terminals, respectively, and the input terminal 101 is an input terminal for the data signal of the NRZ code. An input terminal 102 receives a coding rule violation signal (hereinafter referred to as
The input terminal 103 is an input terminal for a clock signal synchronized with the above two types of signals. Here, it is assumed that a coding rule violation occurs when the CRV signal is "1", and a coding rule violation does not occur when it is "0". The latch/delay circuit 104 latches the input data signal and outputs a signal S- when the data signal is "1".
1, and the data signal becomes “0” with a delay of half a clock.
S-2, which is output when
Separate into -3 and 3. Furthermore, the latch circuit 105 latches the input CRV signal and outputs a signal S-4 when a sign rule violation occurs.

The CMI encoding circuit 106 for data signal "0" outputs a block signal S-5 of "01" from the output signal S-4 of the latch circuit 105 and the clock signal if no violation of the coding rule occurs. If a code rule violation occurs, the “10” block signal S-
Outputs 5. This signal is output in the relationship between the signal S-4 from the latch 105 and the clock signal, regardless of the data signal.
It is also output when the data signal is "1". The CMI encoding circuit 107 for the data signal "1" generates a data signal "1" that does not violate the coding rule from the output signal S-1 of the latch/delay circuit 104, the output signal S-4 of the latch circuit 105, and the clock signal. 1'', a signal S-6 whose output level is inverted is output. In this case as well, the above signal is output even when the data signal is "0".

CMI encoding circuit 10 for the above data signal “0”
The output signal S-5 of 6 is input to the gate circuit 108 of the data signal "0", and the latch/delay circuit 10
5 outputs the signal S- delayed by the above half clock.
By opening the gate with 2, the signal S-7 is output only when the data signal is "0". Also,
CMI encoding circuit 107 for the above data signal “1”
The output signal S-6 is input to the gate circuit 109 for the data signal "1", and the latch/delay circuit 104
The signal S-3 delayed by the above half clock outputted by
By opening the gate further, the signal S-8 is output only when the data signal is "1". Then, the synthesis circuit 110 generates the output signal S-7 of the gate circuit 108 for the data signal "0" and the output signal S-8 of the gate circuit 109 for the data signal "1".
A CMI code signal S-9 is generated by combining the CMI code signal S-9 and output to the output terminal 111.

FIG. 8 is a circuit diagram of the CMI encoding circuit of FIG. 7, and FIG. 9 is a timing diagram of each output signal in FIG. In FIG. 8, an input terminal 121 is an input terminal for the data signal of the NRZ code, an input terminal 122 is an input terminal for the CRV signal of the NRZ code, and the input terminal 12
3 is an input terminal for a clock signal synchronized with the above two types of signals. Flip-flop 124, 125
The latch/delay circuit 104 for the data signal is formed by the flip-flop 126, and the latch circuit 105 for the CRV signal is formed by the flip-flop 126. Furthermore, the flip-flop 127 and the EX-OR gate 128 form the CMI encoding circuit 106 for the data signal "0", and the NOR gate 129 and the flip-flop 13
0 and CMI encoding circuit 10 for data signal “1”
form 7. Further, the NOR gate 131 connects the gate circuit 108 with the data signal "0", and the NOR gate 132 connects the gate circuit 109 with the data signal "1".
, and form the synthesis circuit 110 using the OR gate 133, respectively. 134 is a CMI code output terminal.

FIG. 9 shows the output signals of each section in FIG. 8 above. In the figure, signal a+b is data signal a.
It is a logical sum with CRV signal b, and this signal a+b
The signal k obtained by CMI encoding is the desired output signal.

<Problems to be Solved by the Invention> However, in the conventional CMI encoding circuit described above, the data signal is CMI encoding is performed separately for “0” and “1”, and in the final stage a synthesis circuit 110 consisting of an OR gate 133
Since the signal obtained by CMI-encoding the data signal "0" and the signal obtained by CMI-encoding the data signal "1" are combined and outputting the CMI-encoded signal k, the above signal i and signal j The above synthesis circuit 11 with
The problem is that the number of gates that each signal passes through until it is input to 0 is different, and a difference in gate delay occurs between both signals i and j, causing a glitch to occur at the position indicated by arrow Z of signal k in Figure 9. There is.

Furthermore, when the data signal "0" is CMI-encoded, the EX-OR gate 128 inverts a part of the clock signal and performs CMI-encoding when a coding rule violation occurs.
Due to the delay difference between CRV signal b and CRV signal b, a glitch occurs at the position indicated by arrow Y in signal f in FIG.
There is a problem in that it appears as it is at the position indicated by arrow Y of signal k.

Therefore, it is conceivable to equalize the number of gates through which signal i and signal j pass to eliminate the difference in delay between each signal due to the number of gates, but this may result in differences in the temperature characteristics of each gate and waveform distortion due to higher speeds. This also causes glitches. Therefore, in order to remove such glitches, the waveform was shaped using a clock multiplied by 2. However, as the speed increases, the above waveform becomes distorted and the glitch width widens. A drawback is that bit errors occur when the timing of the coding glitch and the doubling clock match.

Therefore, an object of the present invention is to encode a data signal of an NRZ code into a CMI code that violates the coding rule based on a CRV signal without being affected by the gate delay of each signal in the circuit.
No glitches occur in the CMI code output signal.
The object of the present invention is to provide a CMI encoding circuit that can stably perform CMI encoding even on high-speed data.

<Means for Solving the Problems> In order to achieve the above object, the CMI encoding circuit of the present invention converts a binary 1-bit data signal based on a coding rule violation signal that indicates a coding rule violation. In a CMI encoding circuit that encodes into a 2-bit block having a coding rule violation, the data signal "1" is encoded into the 2-bit block based on the data signal and the coding rule violation signal. a level storage circuit when the data is “1” that holds the level at the time; a level when the immediately preceding data signal is “1” held by the level storage circuit when the data is “1”; and the data signal. a second-half bit level determination circuit that determines and holds the level of the second-half bit of each block when the one-bit data signal is encoded into the two-bit block based on the coding rule violation signal; ” level signal at the time of the above-mentioned immediately preceding data signal “1” held in the level storage circuit,
The output level is determined based on the level signal of the second half of the two bits for the data signal one bit before, which is determined and held by the second half bit level determination circuit, the above data signal, and the above coding rule violation signal. a determination circuit that determines whether or not to invert and outputs an inverted signal if inversion is necessary;
a gate circuit that controls a clock signal for inverting the output level based on the inverted signal from the determination circuit; and a previously held signal outputted immediately beforehand based on the clock signal output from the gate circuit. an output inverting circuit that inverts and outputs the level of the second half bit when encoding the second half bit block outputted from the second half bit level judgment circuit; A comparison circuit that compares the level of the second half of the bits and outputs a signal if the above judgment level and the level of the second half bit differ; The present invention is characterized by comprising a phase control circuit that inverts the phase of the signal output from the output inversion circuit when a signal representing the above is output.

<Operation> When a binary 1-bit data signal and a coding rule violation signal are input from the input terminal, the data signal "1" is converted to 2 bits based on the data signal and the coding rule violation signal. The level when encoded into the block (“00” or “11”) is held by the level storage circuit when the data is “1”, and the level is held by the level storage circuit when the data is “1”. The 1-bit data signal (“0”,
“1”) to the above 2-bit block (“01”, “10”,
The level ("0" or "1") of the second half bit of each block when encoding into "00", "11") is determined by the second half bit level determination circuit, and the result is held.

Next, the level signal at the time of the immediately preceding data signal "1" held in the level storage circuit at the time of the data "1" and the level signal of the previous bit judged and held by the second half bit level judgment circuit are Based on the level of the second half of the two bits for the data signal, the data signal, and the sign rule violation signal, a determination circuit determines whether or not to invert the output level, and it is necessary to invert the output level. If there is, an inverted signal is output. Furthermore, when the inverted signal is output from the determination circuit, the gate of the clock signal whose output level is inverted is opened by the gate circuit, and the clock signal is outputted.

When the clock signal is output from the gate circuit, the level (“0” or “1”) of the signal held in advance by the output inversion circuit is inverted and output, and the clock signal is output from the gate circuit. If the signal is not output, the level of the signal held in advance by the output inverting circuit is output as is.

The determination level of the second half bit when encoding into a 2-bit block determined by the second half bit level determination circuit and the level of the second half bit of the two bits output from the output inverting circuit are sent to the comparison circuit. After comparison, a signal is output if the determination level and the second half bit level are different. Then, the phase control circuit inverts the phase of the signal output from the output inverting circuit and outputs the resultant signal based on the signal in which the judgment level from the comparison circuit is different from the second half bit level, and the signal output from the comparison circuit outputs the signal outputted from the output inverting circuit. If a signal whose level is different from the second half bit level is not output, the signal output from the output inversion circuit is output as is.

In this way, CMI encoding is performed by inverting or non-inverting the previous output bit level, so there is no need to synchronize to synthesize multiple signals, and there is no effect on the gate delay of each signal in the circuit. Can be CMI encoded without being
No glitches occur in the output signal.

<Examples> The present invention will be described in detail below with reference to illustrated examples.

FIG. 1 is a block diagram showing the configuration of the present invention, and 12 and 3 are input terminals. Above input terminal 1
is an input terminal for data signals such as NRZ code,
Input terminal 2 is an input terminal for an NRZ code CRV signal, and input terminal 3 is an input terminal for a clock signal synchronized with the above two types of signals. The latch/delay circuit 5 latches the data signal input from the input terminal 1, and outputs the data signal, its inverted signal, and a signal delayed by a half clock. Further, the latch circuit 6 latches the CRV signal inputted from the input terminal 2.

The level storage circuit 7 when data is "1" holds as an internal level the level obtained when the data signal is CMI encoded based on the input data signal and CRV signal. Its operation is such that when a data signal "1" is input and the CRV signal is "0", that is, when the sign rule violation is not violated, the held internal level ("0" or "1") is inverted. , In addition, when the CRV signal is "1", that is, when a coding rule violation occurs, the above-mentioned internal level is held as is. Here, the internal level refers to the level of the signal held within the circuit, and when the input data signal "1" is CMI encoded, it is determined whether it is at the level "00" or "11". This indicates whether the data has been encoded. By referring to the internal level, it is possible to determine which level, "00" or "11", should be encoded when the next input data signal "1" is CMI encoded.

The second half bit level determination circuit 9 receives the input data signal latched by the latch/delay circuit 5, the input CRV signal latched by the latch circuit 6, and the internal level held in the level storage circuit 7 when the data is "1". In other words, the previous data signal “1”
Based on the CMI encoded level, when the currently input data signal is CMI encoded based on the CRV signal, which level should the second half of the 2-bit block be set to “0” or “1”? and maintain that level. Specifically, the determination of the second half bit level is performed according to the table shown in FIG. This table shows the data signal, CRV signal,
The level signal obtained when the immediately preceding data signal "1" held in the level storage circuit 7 at the time of the data "1" is CMI encoded, and the second half bit level signal determined based on the three types of signals mentioned above. They are displayed in the same row, and a CMI code block is also shown for reference. According to this table, for example, in the case of a data signal "0" and a CRV signal "0", regardless of the holding level of the immediately preceding data signal "1", no violation of the coding rule occurs, so the CMI encoding block is 01", and the second half bit is determined to be "1". On the other hand, if the data signal is "0" and the CRV signal is "1", a coding rule violation occurs, so the CMI encoded block is determined to be "10" and the second half bit is determined to be "0". Similarly, in the case of data signal “1” and CRV signal “0”, if the holding level at the time of the previous data signal “1” is “0”, then
Since the CMI encoded block is "11", the second half bit is determined to be "1". Further, if the holding level of the immediately preceding data signal "" is "1", the block with the CMI code becomes "0 0", and the second half bit is determined to be "0". Hereinafter, the data signal "1" and the CRV signal "1" are determined in the same manner.

The determination circuit 10 receives the input data signal and delayed data signal inputted from the latch/delay circuit 5, and the input CRV inputted from the latch circuit 6.
The input data signal is determined according to the input CRV signal based on the determination output input from the second half bit level determination circuit 9, and the internal level output input from the level storage circuit 7 when the data is "1". When performing CMI encoding, it is determined whether the level of the bit to be output now (referred to as the output level) should be inverted with respect to the level of the previous bit and output. Only when it is determined that the output level is to be inverted, the gate circuit 11 is opened and a clock pulse for inverting the output level is output to the output inverting circuit 13.

The output inverting circuit 13 includes the gate circuit 11
The internal level held is inverted by the clock pulse input from the clock pulse. This output inversion circuit 13
If the internal level of the input data signal is initially reset, a normally CMI encoded signal can be obtained based on the input CRV signal, but
Depending on the initial value of the internal level of the output inversion circuit 13, the phase of the output level of the bit to be output may be opposite to the correct level. In order to prevent such malfunctions, the comparison circuit 14 encodes the judgment level input from the second half bit level judgment circuit 9 and the internal level output of the output inversion circuit 13 input from the output inversion circuit 13. The level of the second half bit of the two-bit block is compared, and if the above judgment level and the second half bit level are different, a signal indicating that the two levels are different is outputted to the phase control circuit 15. And the phase control circuit 15
, the phase of the internal level output of the output inverting circuit 13 input from the conversion inverting circuit 13 is reversed,
If the two levels are equal, the signal is output to the output terminal 17 as a CMI code signal with the same phase.

Next, regarding the operation of the determination circuit 10, the fourth and fifth
This will be explained with reference to the figure. FIG. 4 is a table for determining the first half bit of the data signal to be CMI encoded now based on the level of the second half bit of the CMI code block for the previous data signal, and FIG. 5 is a similar table. This is a table for determining the second half bit. This table also shows the data signal, CRV signal, and the previous data signal "1" held in the level storage circuit 7 when data is "1".
The level signal obtained when CMI encoding is performed, the level signal of the second half bit of the data signal one bit earlier held in the second half bit level judgment circuit 9, and the level signal of the gate circuit 11 determined based on the above four types of signals. The open or closed determination results are displayed in the same row.

First, the procedure for determining the level of the first half of the CMI code block when the data signal is "0" will be described. For example, if the data signal "0" is input as shown in the first line of FIG. CMI encoding based on "0" results in "01". At this time, the internal level held in the second half bit level determination circuit 9 is based on the currently input data signal and
If the level of the second half bit of the 2-bit block is held when the data signal 1 bit before the CRV signal is CMI encoded, and the above internal level is "0", then the currently input data signal The first half bit of the CMI code block “01” for “0” and CRV signal “0” is “0”, which is the same as the second half bit for the data signal one bit before.
Therefore, when outputting the CMI code output signal, the 1 held in the output inverting circuit 13 is
There is no need to invert the signal level "0" of the second half bit in the CMI code of the data signal before the bit. Therefore, in this case, the gate circuit 11 is closed so that no clock pulse is output. Further, as shown in the second column of FIG. 4, the level of the second half bit is "1", that is, the second half bit of the block of CMI code corresponding to the data signal one bit before is "1".
If this is the case, the data signal “0” that has just been input is
And since the first half bit of block “01” of CMI code for CRV signal “0” is “0”,
When outputting the CMI code, it is necessary to invert the level "1" of the second half bit of the data signal one bit before, which is held in the output inverting circuit 13, to "0". Therefore, in this case, the gate circuit 11 is opened and the clock pulse is output to the output inverting circuit 13, where it is held.
Invert the level of the output signal of CMI encoding,
Outputs the first half bits of the CMI code block.

In addition, as shown in the 3rd and 4th columns of FIG. Since it is “10” when converted to “10”, the first half bit of the block in CMI code is “1”.
Assuming that, as described above, the second half bit of the block of CMI code in the data signal one bit before, that is, the internal level of the output inverting circuit 13, is inverted or not inverted (that is, the gate circuit 11 is opened or (closed) is determined as shown in FIG. 4, and the gate circuit 11 is controlled. In this manner, when the data signal is "0", the first half bit of the CMI code block is determined regardless of the holding level when the data signal was "1" immediately before.

Next, a procedure for determining the level of the first half of the CMI code block when the data signal is "1" will be described. When the data signal “1” is input, the CRV signal and the previous data signal “1” are input.
Level when CMI encoded, that is, data “1”
Based on the internal level held in the current level storage circuit 7, it is determined whether the currently input data signal "1" should be encoded at the level "00" or "11", and the determination result is On the other hand, in the same way as when the data signal is "0", the output inverting circuit 13
The gate circuit 11 is controlled by determining whether or not the second half bit level of the block of CMI code in the data signal one bit earlier, which is the internal level held by the bit, is inverted or not, as shown in the table of FIG. .

Next, a procedure for determining the level of the second half bit of a CMI code block when the data signal is "0" will be described. When data signal “0” is CMI encoded, the level “1” of the second half bit of CMI encoding “01” (“10” when violation of coding rules occurs) (“0” when violation of coding rules) is Since it is necessary to invert the level "0" of the first half bit ("1" if a violation of the sign rule occurs), the gate circuit 11 is opened as shown in the first line of FIG. 5, and the clock pulse is transferred to the output inverting circuit 13. The second half bits of the CMI code block are output by inverting the level of the first half bits already output and held in the output inverting circuit 13 as described above.

Next, the procedure for determining the level of the second half bit in the case of the data signal "1" will be described. When data signal "1" is CMI encoded, the level of the second half bit of the CMI code is the same as the level of the first half bit, so the gate circuit 1 is encoded as shown in the second line of FIG.
1 is closed and the internal level held in the output inversion circuit 13 is output as is.

As described above, the determination circuit 10 converts the first half or second half bit of the CMI code block to be outputted from the one bit held in the output inversion circuit 13 to the second half bit of the previous CMI code block or the second half bit of the previous CMI code block. Compared with the first half of
Only when inversion is necessary, the gate circuit 11 is opened and a clock pulse is output to the output inversion circuit 13.

FIG. 2 shows a circuit of an embodiment of the block diagram shown in FIG. 1, where 21 is a data signal input terminal for NRZ code, etc., 22 is a CRV signal input terminal for NRZ code, and 23 is the above-mentioned 2. This is an input terminal for a clock signal synchronized with the seed signal. Flip-flops 25 and 26 form the aforementioned latch/delay circuit 5 for the data signal, and flip-flop 27 is the aforementioned latch circuit 6 for the CRV signal. NAND gate 2
9, 30, 31, 32 and flip-flop 3
4 and 35 form the second half bit level determination circuit 9, and AND gate 37 and flip-flops 38 and 39 form the level storage circuit 7 when the data is "1". Further, the EX-O gate 41 and the parity check circuit 42 are connected to the determination circuit 10.
AND gates 44, 45, 46
forms the judgment circuit 10 and the gate circuit 11 of the clock pulse. flipflop 48,4
9, 50 and the parity check circuit 51 form an output inversion circuit 13, and flip-flops 53,
54, 55 and an EX-OR gate 56 form the storage circuit 14 which compares and determines the latter half bits of the block of CMI codes. The EX-OR gate 57 is the phase control circuit 15, and also the EX-OR gate 57 is the phase control circuit 15.
Gates 58 and 59 are circuits that output the clock signal and its inverted signal so that there is no difference in gate delay, and 60 is a CMI code output terminal.

Here, the parity check circuits 42, 51
is level “1” if there is an even number of signals (0 or 2) that are level “1” among inputs A, B, and C.
If there is an odd number (1 or 3), level "0" is output from the output terminal ΣEVEN. That is, the circuit inverts the output level from the output terminal ΣEVEN when the input level of any one of the input terminals A, B, and C is inverted.

The circuit shown in FIG. 2 in this embodiment is not limited to this, and any circuit may be used as long as it realizes the function of the block diagram shown in FIG.

FIG. 3 is a diagram showing signals of each part indicated by A to O in FIG. 2. The signal A+B shown between the CRV signal B and the clock signal C in the figure is the logical sum of the data signal A and CRV signal B,
The signal obtained by CMI encoding this signal A+B is the desired output signal O. Here, among the signals A+B, "K" indicates a CMI coding rule violation signal of the data signal "0", and "J" indicates a CMI coding rule violation signal of the data signal "1". Also, below the output signal O, CMI
Signals A+B before encoding are shown in parallel.

In other words, when encoding data signal A into CMI code signal O, which is a continuous 2-bit block string, in accordance with coding rule violation signal B, the present invention provides a system that CMI code level signal G at data signal “1” of
Based on the second half bit level signal I of the CMI code in the data signal 1 bit before, the level of 1 bit of the block of CMI code that is about to be output is determined by inverting the level of the 1 bit output just before. It sequentially determines whether the data is valid or not, one bit at a time, and outputs it. Therefore, there is no need to synchronize two types of signals in order to synthesize them, and glitches do not occur.

<Effects of the Invention> As is clear from the above, the CMI encoding circuit of the present invention has two
Determine the level of the second half of the bit block.
The second half bit level signal for the data signal one bit before, the level signal when the previous data signal is "1", the binarized 1-bit data signal, and the coding rule violation signal are used. Based on this, the determination circuit determines whether or not to invert the output level to be output next, and based on the determination result, the level of the signal output just before, which is held in advance by the output inversion circuit, is Since the output is inverted or non-inverted, there is no need to synchronize and synthesize two or more types of signals to create a CMI signal, and glitches are eliminated regardless of the gate delay of each signal in the circuit. This can definitely be prevented from occurring. Therefore, it can be used in a transmission device in a place where the amount of gate delay changes drastically due to temperature changes, and the speed can be easily increased using conventional elements.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the CMI encoding circuit of the present invention, Fig. 2 is a circuit diagram of the above embodiment, Fig. 3 is a diagram showing the operation of the second half bit level judgment circuit, and Fig. 4 is a judgment A diagram showing the operation of determining the first half bit from the second half bit of the circuit, FIG. 5 is a diagram showing the operation of determining the second half bit from the first half bit of the determination circuit, and FIG. 6 shows the signals of each part in the circuit diagram of FIG. 2. Figure 7 is the timing chart for the conventional
FIG. 8 is a block diagram of the CMI encoding circuit, FIG. 8 is a circuit diagram of the conventional example, and FIG. 9 is a timing chart of signals at various parts in the circuit diagram of FIG. 1...Data signal input terminal, 2.KlCRV signal H input terminal, 7...Level storage circuit when data is "1", 9
... second half bit level judgment circuit, 10... judgment circuit,
13... Output inversion circuit, 14... Comparison circuit, 15... Phase control circuit.

Claims (1)

[Claims] 1. A CMI encoding circuit that encodes a binarized 1-bit data signal into a 2-bit block having a coding rule violation based on a coding rule violation signal that indicates a coding rule violation. a level storage circuit for storing the level when the data signal is "1", which holds the level when the data signal "1" is encoded into the 2-bit block based on the data signal and the coding rule violation signal; Based on the level at the time of the previous data signal "1" held in the level storage circuit at the time of data "1", the above data signal, and the above code rule violation signal, the above 1-bit data signal is A second half bit level determination circuit that determines and holds the level of the second half bit of each block when encoding into a 2-bit block, and the immediately preceding data signal held in the level storage circuit when the data is "1". 1'' level signal, the level signal of the second half bit of the two bits for the previous data signal determined and held by the second half bit level judgment circuit, the above data signal, and the above coding rule violation signal. a determination circuit that determines whether or not to invert the output level based on the above and outputs an inverted signal when inversion is necessary; and a determination circuit that inverts the output level based on the inverted signal from the determination circuit. a gate circuit for controlling the clock signal outputted from the gate circuit; an output inversion circuit for inverting and outputting the previously held level of the previously output signal based on the clock signal outputted from the gate circuit; The judgment level of the latter half of the 2-bit block outputted from the judgment circuit is compared with the level of the latter half of the 2 bits output from the output inversion circuit, and the judgment level is determined. a comparator circuit that outputs a signal when the level of the second half bit differs from the level of the second half bit; A CMI encoding circuit comprising: a phase control circuit for reversing the phase of a signal.