JPS63142744A - Cmi encoding circuit - Google Patents

Abstract

PURPOSE:To securely prevent the occurrence of glitch out of relation to the gate delay of respective signals in a circuit by inverting or non-inverting the level of signal which is previously held and outputted just before in an output inversion circuit according to decided result so as to output it. CONSTITUTION:A comparison circuit 14 compares a decision level inputted from a latter bit level decision circuit 9 with the level of the latter bit of two bits of block obtained by CMI encoding the internal level output of an output inversion circuit 13 inputted from the output inversion circuit 13 and outputs a signal expressing that both levels are different, if the decision level and the level of the latter. bit are different, to a phase control circuit 15. And the phase control circuit 15 inverts the phase of the internal level output of the output inversion circuit 13 inputted from the output inversion circuit 13 and if both levels are equal the circuit 15 outputs as the signal of the CMI code to an output terminal 17 in the same phase. Thus, erroneous actions can be prevented.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a data signal such as a normal binary 1-bit NRZ (non-return-to-zero) code and a code rule for the data signal. A coding rule violation signal that is suitable for creating a CMI (Coated Mark Inversion) code signal encoded into a 2-bit block used for a transmission signal, etc. based on a coding rule violation signal that indicates a violation. The present invention relates to a CM2 encoding circuit having a CM2 encoding circuit.

<Prior art> A CMI code is a system that converts a binary 1-bit data signal into 2 bits.
It is a type of 1B2B code that is encoded into a block of bits. For example, in the case of a data signal "0", it is encoded into a 2-bit block of "0 bits", and in the case of a data signal "pi", it is encoded as a data signal generated in the middle. 0'' refers to a code that is encoded in blocks of ``00° or ``l Bi'' alternately with the previous data signal ``Bi''.Also, violation of the code rule for the above CM! 0'' into a block of ``lO'', and the data signal ``bi'' is not alternately converted, but the data signal ``bi'' is encoded immediately after the CMI code of the converted data signal ``bi''.
” or “encoded into l bi blocks.

Traditionally, CM! As an encoding circuit, there is one shown in FIG. In Figure 7, 101°102.103
are input terminals, and the input terminal 101 is the input terminal NR.
This is an input terminal for a Z code data signal. Input terminal 102
is an input terminal for a code rule violation signal (hereinafter referred to as a CRV signal) that instructs the output of a code rule violation of the NRZ code, and input terminal 103 is an input terminal for a clock signal synchronized with the above two types of signals. Here, it is assumed that a violation of the coding rule occurs when the CRV signal is “B” and a violation of the coding rule does not occur when it is “0”.The latch/delay circuit 104 latches the inputted data signal and outputs the data signal A signal S-t is output when the data signal is "0" after being delayed by half a clock, and a signal S-2 is output when the data signal is "0" after being delayed by half a clock. Output signal S
Separate into -3 and 3. Further, the latch circuit 105 latches the inputted CR■ signal and outputs a signal S-4 when a violation of the sign rule occurs.

The data signal "0" CMI encoding circuit 106 uses the output signal S-4 of the latch circuit 105 and the clock signal to
If the coding rule is not violated, the signal S-5 of the "0 bit" block is output, and if the coding rule is violated, the signal S-5 of the "lO" block is output. Regardless of whether the signal S from the latch 105
Since it is output in the relationship between -4 and the clock signal,
It is also output when the data signal is “B”.
The CMI encoding circuit 107 for Bi uses the output signal S-1 of the latch/delay circuit 104, the output signal S-4 of the latch circuit 105, and the clock signal to generate a data signal that does not violate the coding rule. Signal S- to invert the output level
Outputs 6. In this case as well, the above signal is output even when the data signal is "0".

The output signal S-5 of the CMI encoding circuit 106 for the data signal "0" is inputted to the gate circuit 108 for the data signal "0", and the signal delayed by the half clock is outputted by the fourth delay circuit 105. By opening the gate with S-2, the signal S-7 is output only when the data signal is "0". In addition, the CMI encoding circuit 1 for the data signal “BI”
The output signal S-6 of 07 is converted into the data signal
By opening the gate with the signal S-3 delayed by the half clock and output from the latch/delay circuit 104, the signal S-8 is input to
Output. Then, the synthesis circuit 110 synthesizes the output signal S-7 of the gate circuit 108 for the data signal "0" and the output signal S-8 of the gate circuit 109 for the data signal "B" to generate the CMI code signal S-9. generate and output terminal I
Output to 11.

8 is a circuit diagram of the CMI encoding circuit of FIG. 7, and FIG. 9 is a timing chart of each output signal in FIG. 8. In FIG. 8, an input terminal 121 is an input terminal for the data signal of the NRZ code, an input terminal 122 is an input terminal for the CRV signal of the NRZ code,
The input terminal 123 is an input terminal for a clock signal synchronized with the above two types of signals. Flip-flop 124, 125
forming the latch/delay circuit 104 for the data signal,
The flip-flop 126 forms the latch circuit 105 for the CRV signal. Also, flip-flop 127 and E
The X-OR gate 128 forms the CMI encoding circuit 106 for the data signal "0", and the NOR gate 129 and the flip-flop 130 form the CMI encoding circuit 107 for the data signal "BI". The gate circuit 108 for the data signal "0" is formed by the NOR gate 132, the gate circuit 109 for the data signal "B" is formed by the NOR gate 132, and the synthesis circuit 110 is formed by the OR gate 133. 134 is a CMI code output terminal.

FIG. 9 shows the output signals of each section in FIG. 8 above. Signal a+b in the figure is the logical sum of data signal a and CRV signal S, and signal k obtained by CMI encoding this signal a+b is the desired output signal.

<Problems to be Solved by the Invention> However, in the conventional CMI encoding circuit, the CMI encoding circuit 106 for the data signal "0" and the CMI encoding circuit 107 for the data signal "BI" convert the data signal to " CMI encoding is performed separately for "0" and "any time," and in the final stage, a synthesis circuit 1 consisting of an OR gate 133 is applied.
At step 10, a signal obtained by CMI encoding the data signal "0" and a signal obtained by CMI encoding the data signal "B" are combined,
Since the I-encoded signal k is output, the above signal i
The number of gates through which the signals i and j pass through until they are manually input to the synthesis circuit llO is different, and a difference in gate delay occurs between the two signals i and j, as shown by the arrow Z in the signal in FIG. There is a problem with position glitches.

Furthermore, when data signal "0" is CMI-encoded, the EX-OR gate 128 inverts a part of the clock signal and CMI-encodes it when a coding rule violation occurs. There is a problem in that a glitch occurs at the position shown by arrow Y in the signal f in FIG. 9 due to the delay difference between the signals, and this glitch appears as it is at the position shown by arrow Y in the signal.

Therefore, it is conceivable to equalize the number of gates through which signal i and signal j pass to eliminate the difference in delay between each signal due to the number of gates. Glitches still occur due to distortion. Therefore, in order to remove such glitches, the waveform was shaped using a clock that was doubled, but as the speed was increased, the above waveform became wider than the distortion glitch width, so the widened glitch width There is a drawback that a bit error occurs when the glitch of the CMI code containing the glitch matches the timing of the double clock.

Therefore, an object of the present invention is to
When encoding a Z code data signal into a CMI code that violates the coding rules, it is possible to encode high-speed data without being affected by the gate delay of each signal in the circuit and without causing glitches in the output signal of the CMI code. CM is stable even against
The object of the present invention is to provide a CMI encoding circuit capable of I encoding.

Means for Solving the Problems In order to achieve the above object, the CMI encoding circuit of the present invention converts a binarized 1-bit data signal based on a coding rule violation signal that indicates a coding rule violation. The CMI encoding circuit encodes the data signal "Bi" into the 2-bit block based on the data signal and the coding rule violation signal. a level storage circuit for data "B" that holds the level at "B", and a level for the immediately preceding data signal "B" held by the level storage circuit for the data "B";
Based on the data signal and the code rule violation signal,
The second half bit level determination circuit determines and holds the level of the second half bit of each block when the 1-bit data signal is encoded into the 2-bit block, and the level storage circuit when the data is stored is used. The level signal of the immediately preceding data signal "B", the level signal of the second half bit of the two bits for the previous data signal determined and held by the second half bit level judgment circuit, and the above a determination circuit that determines whether or not to invert the output level based on the data signal and the sign rule violation signal, and outputs an inverted signal if inversion is necessary; and an inverted signal from the determination circuit. a gate circuit that controls a clock signal that inverts the output level based on the clock signal; and a gate circuit that inverts and outputs the level of the previously output signal held in advance based on the clock signal output from the gate circuit. the determination level of the second half bits when encoding into the 2-bit block output from the second half bit level determination circuit; and the determination level of the second half bits of the two bits output from the output inversion circuit. a comparison circuit that compares the levels and outputs a signal when the judgment level and the level of the second half bits are different; and a signal that indicates that the judgment level and the level of the second half bits are different from the comparison circuit. The present invention is characterized by comprising a phase control circuit that inverts the phase of the signal output from the output inversion circuit when

<Operation> When a binarized 1-bit data signal and a code all violation signal are input from the input terminal, the above data.

Based on the evening signal and the coding rule violation signal, the data signal “B” is converted into a 2-bit block (“00’ or “11”).
The level when the data signal "B" is encoded is held by the level storage circuit when the data "1" is encoded, and the level when the data "1" is encoded is held by the level storage circuit when the data "1" is encoded. signal and the code rule violation signal, the l-bit data signal (0', "Bi) is converted into the 2-bit block ("0 Bi, "l G", "
The level ("0" or "bi") of the second half bit of each block when encoding into QO", "1bi" is determined by a second half bit level determination circuit, and the result is held.

Next, the level signal at the time of the above-mentioned immediately preceding data signal "B" held in the level storage circuit at the time of the above-mentioned data "1",
The output level is determined based on the level of the second half of the two bits for the data signal one bit before, which is determined and held by the second half bit level determination circuit, the data signal, and the code rule violation signal. A determination circuit determines whether or not to invert, and if inversion is necessary, an inversion signal is output. Furthermore, when the inverted signal is output from the determination circuit, the gate circuit opens the gate of the clock signal whose output level is inverted, and the clock signal is output.

When the clock signal is output from the gate circuit, the signal level (“0” or “bi”) held in advance by the output inversion circuit is inverted and output, and when the clock signal is not output from the gate circuit is the determination level of the second half bit when the level of the signal held in advance by the output inversion circuit is output as is and is encoded into a 2-bit block determined by the second half bit level determination circuit, and the determination level of the second half bit of the signal held in advance by the output inversion circuit. The comparison circuit compares the level of the latter half of the two bits output from the comparison circuit, and if the above judgment level and the latter half bit level are different, a signal is output.Then, the judgment level from the comparison circuit The phase control circuit reverses the phase of the signal output from the output inverting circuit based on the signal in which the second half bit level is different from the second half bit level, and outputs the signal after inverting the phase thereof.
If the comparing circuit does not output a signal whose determination level is different from the second half bit level, the signal output from the output inverting circuit is output as is.

In this way, CMr encoding is performed by inverting or non-inverting the previous output bit level, so there is no need to synchronize to synthesize multiple signals, and there is no effect on the gate delay of each signal in the circuit. CMI encoding can be performed without causing any glitches in the output signal.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 is a block diagram showing the configuration of this invention.
2.3 is an input terminal. The input terminal 1 is an input terminal for a data signal such as an NRZ code, and the input terminal 2 is an input terminal for a data signal such as an NRZ code.
The input terminal 3 is an input terminal for a CRV signal of the code, and the input terminal 3 is an input terminal for a clock signal synchronized with the above two types of signals.

The latch/delay circuit 5 latches the data signal input from the input terminal 1, and outputs the data signal, its inverted signal, and a signal delayed by a half clock. Further, the false circuit 6 latches the CRV signal input from the input terminal 2.

The level storage circuit 7 at data "1" stores the level obtained when the data signal is CMI encoded based on the input data signal and CRV signal as an internal level. If the CRV signal is “0”, that is, if no coding rule violation occurs, the internal level held (“0” or “B”) is inverted, and the CRV signal is “B”. In the case of , that is, when a sign rule violation occurs, the above internal level is maintained as is. Here, the internal level is the level of the signal held in the circuit, and when the input data signal "BI" is CMI encoded, it is encoded at the level "00" or "Ebi". This shows whether the results have been changed.

By referring to the above-mentioned internal level, it is possible to determine which level should be used to encode the data signal "00" or "Ebi" when CMI-encoding the next input data signal "BI".

The second half bit level determination circuit 9 is the latch/delay circuit 5 described above.
The input data signal latched by the latch circuit 6, the human-powered CRV signal latched by the latch circuit 6, and the internal level held in the 1 o'clock level storage circuit 7, that is, the direct data signal, were CMI encoded. Based on the level and
CM the currently input data signal based on the CRV signal
When performing I encoding, it is determined whether the second half bit of a 2-bit block should be set to the level "0" or "B", and that level is held.The determination of the second half bit level is specifically is carried out according to the table shown in Fig. 3.This table shows the data signal, CRV signal, and the level when the data signal "B" is CMI encoded. The signal and the second half bit level signal determined based on the above three types of signals are displayed in the same line, and blocks of CMI codes are also displayed for reference.

According to this table, for example, data signal "0", CRV signal "
In the case of "0", there is no violation of the coding rule regardless of the holding level when the previous data signal "B" occurs, so the block of the CMI code becomes "0B", and the second half of the hit is determined to be "B". On the other hand, in the case of the data signal "0" and the CRV signal "B", a code rule violation occurs, so the CMI code block is determined to be 10, and the second half hits are determined to be "0". Similarly, in the case of data signal “BI” and CRV signal “0”,
If the holding level when the previous data signal is “1” is “0”, it is “1” NA I B Association/7'l-f Port -
+ r dimension "11") t; 00", and the second half bit is determined to be "0". Hereinafter, the data signal "B".

The determination is made in the same manner in the case of the CRV signal "B".

The judgment circuit 10 receives an input data signal and a delayed data signal input from the latch/delay circuit 5, an input CRV signal input manually from the latch circuit 6, and a judgment output input from the second half bit level judgment circuit 9. , the level of the bit to be output now (output level ) should be inverted and output with respect to the level of the previous bit. Only when it is determined that it is inverted, the gate circuit 11 is opened and a clock pulse that inverts the output level is output. Output to the inverting circuit 13.

The output inversion circuit 13 inverts the internal level held by the clock pulse input from the gate circuit II. When the internal level of this output inverting circuit 13 is initially reset, the manual data signal is input to the manual CRV.
Although a normally CMI encoded signal can be obtained based on the signal, depending on the initial value of the internal level of the output inverting circuit 13, the output level of the bit to be output now may be in phase opposite to the correct level. It may become. In order to prevent such malfunction, the comparator circuit 1
In step 4, the determination level inputted from the second half bit level determination circuit 9 and the level of the second half bit of the CMI-encoded 2-bit block of the internal level output of the output inversion circuit I3 manually inputted from the output inversion circuit I3 are determined. When the comparison is made and the determination level is different from the level of the second half bit, the phase control circuit 15 sends a signal indicating that the two levels are different.
Output to. Then, the phase control circuit 15 inverts the phase of the internal level output of the output inversion circuit 13 that is input from the output inversion circuit 13, and if the two levels are equal, the CMI code is sent to the output terminal 17 with the same phase. It appears as a signal.

Next, the operation of the determination circuit 1o will be described with reference to FIG. 4.5. FIG. 4 is a table for determining the first half bit of a data signal to be CMI encoded based on the level of the second half bit of a CMI code block for a 1-bit data signal, and FIG. This is a table for determining the second half bit. Also, this table shows the data signal, CI? CM V signal, the previous data signal held in the level storage circuit 7 when data is “1”
The level signal of the gate circuit 11 determined based on the level signal when I-encoded, the level signal of the second half bit with respect to the data signal 1 bit earlier held in the second half bit level determination circuit 9, and the four types of signals described above. The open or closed determination results are displayed in the same row.

First, the procedure for determining the level of the first half bit of a CMI code block when the data signal is "θ' will be described. For example, as shown in the first line of FIG. 4, the data signal "θ" is input, and the CRV signal " If 0 is input and a coding rule violation does not occur, this data signal 0 is CMI encoded based on the CRV signal 0, resulting in a 0 bit. At this time, the internal level held in the second half bit level determination circuit 9 is the intervening data signal and CRV.
If the level of the second half bit of the 2-bit block is held when the data signal 1 bit before the signal is CMI encoded, and the above internal level is "0", then the currently input data signal " 0” and CRV signal “O”
Since the first half bit of the block "0 Ravi" of the CMI code for "0" is "0", which is the same as the second half bit for the data signal before the above I bit, it is held in the output inverting circuit 13 when outputting the output signal of the CMr code. There is no need to invert the signal level "0" of the second half bit in the CMI code of the data signal before the summer bit. Therefore, in this case, the gate circuit 11 is closed and no clock pulse is output. As shown in the second line of FIG. 2, if the level of the second half bit is "B", that is, the second half bit of the CMI code block corresponding to the data signal 1 bit/1 bit before is "B", then the intervening data signal "
0” and the CRV signal “0”, the first half bit of the block “0 bit” of the CM! code is “0”, so when outputting the CMI code, the previous bit held in the output inverting circuit 13 It is necessary to invert the level "B" of the second half bit in the data signal to "0". Therefore, in this case, the gate circuit 11 is opened and a clock pulse is output to the output inverting circuit 13, and the clock pulse is held by the output inverting circuit 13. By inverting the level of the output signal of CMI encoding,
The first half bits of the MI code block are output.

In addition, as shown in the 3.4th line of Figure 4, the data signal “0”
If the cRV signal “Bi” is input and a coding rule violation occurs, the first half bits of the block in the CMl code will be “10” when the data signal “0” is encoded with the CMr code. If so, as described above,
As shown in FIG. 4, it is determined whether the second half bit of the block of CMI code in the previous data signal, that is, the internal level of the output inverting circuit 13, is inverted or not (that is, whether the gate circuit 11 is opened or closed). The gate circuit 11 is controlled based on the determination. In this manner, when the data signal is "0", the first half bits of the CMI code block are determined regardless of the holding level when the previous data signal "B".

Next, we will discuss the level determination procedure for the first half bits of the CMI code block when the data signal is "Bi".When the data signal "Bi" is input, the CRV signal and the immediately preceding data signal "l" are converted into the CMI code. The currently input data signal “B” is set to “00” by the level when the data “1” is reached, that is, the internal level held in the level storage circuit 7 at the time of the data “1”.
” or “l-bi” to be encoded, and based on the determination result, the internal level held in the output inverting circuit 13 is determined in the same manner as when the data signal is “0”. The gate circuit [1 is controlled by determining whether or not to invert the second half bit level of the CMI code block in the data signal one bit before, as shown in the table of FIG.

Next, a procedure for determining the level of the second half bit of the CMI code block when the data signal is "0" will be described. When data signal “0” is CMI encoded, the level “bi” of the second half bit of the CMI code “0 bit (“IO” if it violates the coding rule) is the first half bit (“0” if it violates the coding rule). Since it is necessary to invert the level "0" (or "B" in case of violation of the sign rule), the gate circuit 11 is opened as shown in the first line of FIG. 5 and the clock pulse is sent to the output inverting circuit 13. The second half bits of the CMI code block are output by inverting the level of the first half bits already output and held in the output inverting circuit 13 as described above.

Next, we will discuss the level determination procedure for the second half bit in the case of the data signal "BI". When CMI encoding the data signal "1", the level of the second half bit of the CMI code is the same as the level of the first half bit, so 5. As shown in the second line of FIG. 5, the gate circuit 11 is closed and the internal level held in the output inversion circuit 13 is output as is.

As described above, the determination circuit IO determines whether the first half or second half bits of the CMI code block to be output are the second half bits of the 1-bit previous CMI code block held in the output inversion circuit 13 or the first half bits within the same block. The gate circuit 11 is opened and a clock pulse is output to the output inverting circuit 13 only when inversion is necessary.

FIG. 2 shows a circuit of an embodiment of the block diagram shown in FIG. 1, in which 21 is a data signal input terminal such as NRZ code, 22 is a CRV signal input terminal of NRZ code, and 23
is an input terminal for a clock signal synchronized with the above two types of signals. The flip-flops 25 and 26 form the latch/delay circuit 5 for the data signal, and the flip-flop 27 is the latch circuit 6 for the CRV signal. The latter half bit level determination circuit 9 is formed by the NAND gates 29, 30, 31, and 32 and the flip-flops 34 and 35.
The EX-OR gate 41 and the parity check circuit 42 form a part of the judgment circuit 10, and the AND gates 44, 45, and 46 form a part of the judgment circuit 10. The gate circuit II of the double clock pulse is formed.Flip-flop 48,
49.50 and the parity check circuit 51 form the output inversion circuit 13, and the flip-flops 53, 54.55
The EX-OR gate 56 forms the comparison circuit 14 that compares and determines the latter half bits of each CMI code block. The EX-OR gate 57 is the phase control circuit 15, and the EX-OR gates 58 and 59 are circuits that output the clock signal and its inverted signal so that there is no difference in gate delay. is the output terminal of the CMI code.

Here, the parity check circuits 42 and 51 check the level "B" if the signals at the level "B" among the signals A, B, and C are an even number 9 (0 or 2), and the level "B" for the odd number (1 or 3) If so, level "0" is output from the output terminal ΣEVEN. In other words, any one of the input terminals A1BSC
When two input levels are inverted, the output terminal ΣEVEN
This is a circuit that inverts the output level from the .

The circuit shown in FIG. 2 in this embodiment is not limited to this, and any circuit may be used as long as it realizes the function of the block diagram shown in FIG.

FIG. 3 is a diagram showing signals of each part indicated by A to 0 in FIG. 2. CRV signal B and clock signal C in the diagram
The signal A+B shown between the above data signal A and CRV
This is the logical sum with signal B, and the signal obtained by CMI encoding this signal A+B is the desired output signal 0. Here signal A+
Among H, "K" indicates a CMI coding rule violation signal of data signal "0", and "J" indicates a CMI coding rule violation signal of data signal "1". Furthermore, CMI encoded signals A+B are shown in parallel below the output signal 0.

In other words, the present invention converts the data signal A into C, which is a continuous 2-bit block sequence, according to the coding rule violation signal B.
When encoding the MI code signal 0, the above data signal A
and CRV signal B and the previous data signal “CMI at
Code level signal G and C in the data signal 1 bit before
Based on the second half bit level signal I of the MI code, the level of 1 bit of the block of CM code to be outputted is sequentially determined by 1 whether or not the level of the 1 bit output immediately before should be inverted and output. Determine and output bit by bit. Therefore, there is no need to synchronize two types of signals in order to synthesize them, and glitches do not occur.

<Effects of the invention> As is clear from the above, the commercial of this invention! The encoding circuit is! The level of the second half bit of the 2-bit block with respect to the data signal before the bit is determined and held, and the level signal of the second half bit with respect to the data signal of this 1-bit song, the level signal when the immediately preceding data signal "B", Based on the converted 1-bit data signal and the sign rule violation signal, the determination circuit determines whether or not to invert the output level to be output next, and based on the determination result, the output inversion circuit By inverting or non-inverting the level of the previously output signal that is held, there is no need to synchronize and synthesize two or more types of signals to create a CMI signal, and the circuit It is possible to reliably prevent glitches from occurring regardless of the gate delay of each signal within.

Therefore, it can be used in a transmission device in a place where the amount of gate delay changes drastically due to temperature changes, and the speed can be easily increased using conventional elements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the CMI encoding circuit of the present invention, FIG. 2 is a circuit diagram of the above embodiment, FIG. 3 is a diagram showing the operation of the second half bit level determination circuit, and FIG. 5 shows the operation of determining the first half bit from the second half bit of the determination circuit. FIG. 6 shows the signal of each part in the circuit diagram of FIG. 2. Timing chart, Figure 7 is a conventional CM
The block diagram of the I encoding circuit, FIG. 8, is the above conventional example 771.
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Claims (1)

[Claims] (1) In a CMI encoding circuit that encodes a binarized 1-bit data signal into a 2-bit block having a coding rule violation based on a coding rule violation signal that indicates a coding rule violation, the above data a level storage circuit for storing the level when the data signal "1" is encoded into the 2-bit block based on the signal and the coding rule violation signal; The 1-bit data signal is stored in the 2-bit block based on the level of the previous data signal "1" held in the current level storage circuit, the data signal, and the sign rule violation signal. a second half bit level determination circuit that determines and holds the level of the second half bit of each block when encoding, and a level storage circuit that stores the level of the previous data signal "1" when the data is "1". the level signal of the latter bit of the 2 bits for the data signal of 1 bit earlier determined and held by the latter half bit level determination circuit, the above data signal, and the above coding rule violation signal. a determination circuit that determines whether or not to invert the output level based on the output level, and outputs an inversion signal if inversion is necessary; and a determination circuit that inverts the output level based on the inversion signal from the determination circuit. a gate circuit that controls a clock signal; an output inversion circuit that inverts and outputs the previously held signal level of a previously output signal based on the clock signal output from the gate circuit; The judgment level of the second half bits output from the judgment circuit when encoding into the 2-bit block is compared with the level of the second half bits of the 2 bits output from the output inversion circuit, and the judgment level and a comparison circuit that outputs a signal when the level of the second half bit is different from the level of the second half bit. A CMI encoding circuit comprising: a phase control circuit for reversing the phase of a signal.