JPH0462459B2 - - Google Patents
Info
- Publication number
- JPH0462459B2 JPH0462459B2 JP59060996A JP6099684A JPH0462459B2 JP H0462459 B2 JPH0462459 B2 JP H0462459B2 JP 59060996 A JP59060996 A JP 59060996A JP 6099684 A JP6099684 A JP 6099684A JP H0462459 B2 JPH0462459 B2 JP H0462459B2
- Authority
- JP
- Japan
- Prior art keywords
- protruding electrodes
- protruding
- width
- lead
- film carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 20
- 238000000034 method Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 13
- 239000010410 layer Substances 0.000 description 9
- 238000007747 plating Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910015363 Au—Sn Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はフイルムキヤリアを用いる半導体素子
の実装法において、フイルムキヤリアのリード先
端部に、予め突起電極を形成する、突起電極付フ
イルムキヤリアに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a film carrier with protruding electrodes, in which protruding electrodes are formed in advance at the lead ends of the film carrier, in a semiconductor device mounting method using a film carrier.
（従来例の構成とその問題点）
従来フイルムキヤリアを用いる半導体素子の実
装においては、半導体素子の電極上に突起電極を
形成しておく必要があつた。第１図に半導体素子
上に形成した突起電極の構造を示した。図におい
て１は半導体素子、２は酸化膜、３はAl等によ
る配線層、４は保護膜、５は金属膜、６はAu又
はAu合金、あるいは半田等によるメツキ層であ
る。(Structure of Conventional Example and its Problems) Conventionally, when mounting a semiconductor element using a film carrier, it has been necessary to form protruding electrodes on the electrodes of the semiconductor element. FIG. 1 shows the structure of a protruding electrode formed on a semiconductor element. In the figure, 1 is a semiconductor element, 2 is an oxide film, 3 is a wiring layer made of Al or the like, 4 is a protective film, 5 is a metal film, and 6 is a plating layer made of Au or Au alloy, or solder.
以上の構成による半導体素子１上の突起電極に
フイルムキヤリアのリード先端部がボンデイング
される。フイルムキヤリアを用いた実装方法では
通常数＋ピン以上の電極の一括ボンデイングが可
能であり、ワイヤボンデイングに比べ極めて高束
のボンデイングができるものである。しかしなが
ら、フイルムキヤリア実装においては、前述した
ように半導体素子上への突起電極の形成が必要で
あり、このため
突起電極形成に長時間のプロセスを必要とす
る。 Lead tips of the film carrier are bonded to the protruding electrodes on the semiconductor element 1 having the above structure. In a mounting method using a film carrier, it is possible to bond more than the usual number of electrodes at once, and compared to wire bonding, it is possible to bond with an extremely high flux. However, in film carrier mounting, as mentioned above, it is necessary to form protruding electrodes on the semiconductor element, and therefore a long process is required to form the protruding electrodes.
突起電極形成中に半導体素子が破壊され、歩
留りが低下する場合がある。 The semiconductor element may be destroyed during the formation of the protruding electrodes, resulting in a decrease in yield.
以上により半導体素子のコストが高くなる。 Due to the above, the cost of the semiconductor element increases.
等の問題点があつた。There were other problems.
以上のフイルムキヤリア実装方法の問題点を改
善する手段として、第２図、第３図に示した方法
が提案されている。この方法を図を用いて説明す
る。まず第２図ａに示したように、絶縁性材料よ
り成る基板７の一面に単層あるいは複数層より成
る導電層８を蒸着法等の手段により形成する。次
に絶縁性樹脂あるいは酸化膜等より導電層８の表
面を覆った後、選択エツチング法により部分的に
開口部を設けた絶縁マスク９を形成した後、電気
メツキにより前記開口部に突起電極１０を形成す
る。次いで、前記突起電極１０上にフイルムキヤ
リアのリード１１の先端部を位置合せしめ、上部
より加圧及び加熱せしめる。これにより第２図ｂ
に示したごとく、前記リード１１の先端部に突起
電極１０が接合され、導電層８より剥離する。こ
の場合、フイルムキヤリアのリード端子１１と突
起電極１０の接合は、通常、リード１１が表面を
Snメツキした銅（Cu）箔、突起電極１０が金
（Au）により形成されているため、Au−Sn共晶
により成されるものである。尚第３図には突起電
極の形成された基板の上面図を示した（以下、前
記の方法を「転写パンプ」と呼ぶ。）
以上のプロセスでフイルムキヤリアのリードの
先端部に突起電極を接合した後、第４図ａに示す
ように、半導体素子１２の電極部１３（通常Al）
にフイルムキヤリアのリード１１に接合された突
起電極１０を位置合せした後、再度、加圧及び加
熱し第４図ｂに示すごとく、半導体素子１２の電
極部１３と突起電極１０が接合される。この時の
接合はAu−Alの熱圧着でなされる。 The methods shown in FIGS. 2 and 3 have been proposed as means for improving the problems of the film carrier mounting method described above. This method will be explained using figures. First, as shown in FIG. 2a, a conductive layer 8 consisting of a single layer or a plurality of layers is formed on one surface of a substrate 7 made of an insulating material by means such as vapor deposition. Next, after covering the surface of the conductive layer 8 with an insulating resin or an oxide film, an insulating mask 9 having a partial opening is formed by selective etching, and a protruding electrode 10 is formed in the opening by electroplating. form. Next, the tip of the lead 11 of the film carrier is positioned on the protruding electrode 10, and pressure and heat are applied from above. As a result, Figure 2b
As shown in FIG. 3, the protruding electrode 10 is bonded to the tip of the lead 11 and is peeled off from the conductive layer 8. In this case, the lead terminal 11 of the film carrier and the protruding electrode 10 are usually connected so that the lead 11 does not touch the surface.
Since the Sn-plated copper (Cu) foil and the protruding electrode 10 are made of gold (Au), it is made of Au-Sn eutectic. Figure 3 shows a top view of the substrate on which the protruding electrodes are formed (hereinafter, the above method is referred to as "transfer pumping"). The protruding electrodes are bonded to the tips of the leads of the film carrier through the above process. After that, as shown in FIG. 4a, the electrode part 13 (usually Al) of the semiconductor element 12 is
After aligning the protruding electrodes 10 bonded to the leads 11 of the film carrier, pressure and heat are again applied to bond the electrode portions 13 of the semiconductor element 12 and the protruding electrodes 10, as shown in FIG. 4B. At this time, the bonding is done by Au-Al thermocompression bonding.
以上記述した「転写バンプ」を用いたフイルム
キヤリア実装方法は、従来の半導体素子の電極部
に直接突起電極を形成する方法の問題点を改善す
る上で極めて優れたものである。しかしながら、
この方法においては、次のような問題点を残して
いる。即ち、この「転写バンプ」を用いる実装方
法においては、二度のボンデイングが必要であ
り、特に半導体素子の電極部とリードに接合され
た突起電極を接合する二度目のボンデイング時に
突起電極のつぶれが多くなることにより、リード
が半導体素子に接触しやすくなり、いわゆるエツ
ジタツチが発生しやすくなる。これを防止するに
は、突起電極の厚みを厚くする方法がある。しか
しながら、突起電極を形成する電気メツキ法にお
いては、メツキ厚さとほぼ同等に横方向にもメツ
キが成長する。したがつて突起電極を厚くするこ
とは、必然的に突起電極の形状も大きくなり、ボ
ンデイングには不要な部分すなわちリードの幅よ
りも広い部分が多くなる。このためAuの使用量
が増大し、コストが高くなる。 The film carrier mounting method using "transfer bumps" described above is extremely excellent in overcoming the problems of the conventional method of forming protruding electrodes directly on the electrode portions of semiconductor elements. however,
This method still has the following problems. In other words, in this mounting method using "transfer bumps," bonding is required twice, and especially during the second bonding between the electrode part of the semiconductor element and the protruding electrode bonded to the lead, the protruding electrode may be crushed. As the number of leads increases, the leads tend to come into contact with the semiconductor element, and so-called edge touching tends to occur. To prevent this, there is a method of increasing the thickness of the protruding electrode. However, in the electroplating method for forming protruding electrodes, plating also grows in the lateral direction to approximately the same thickness as the plating. Therefore, increasing the thickness of the protruding electrode necessarily increases the shape of the protruding electrode, and increases the portion that is unnecessary for bonding, that is, the portion that is wider than the width of the lead. This increases the amount of Au used and increases the cost.
又、前記したようにメツキが横方向にも成長す
るため、特にフイルムキヤリアのリードのピツチ
が狭いものは突起電極による短絡も発生しやすく
なる。これらの問題を解決する手段としては、フ
イルムキヤリアのリード先端部の幅よりも突起電
極の幅を同等か、もしくは小さくする方法があ
る。しかしながらこの方法であると、位置合せを
上部から見て行うので突起電極とリード先端部の
位置合せが困難になる。 Furthermore, as described above, since the plating also grows in the lateral direction, short circuits due to the protruding electrodes are likely to occur, especially in film carriers with narrow lead pitches. One way to solve these problems is to make the width of the protruding electrode equal to or smaller than the width of the lead tip of the film carrier. However, with this method, alignment is performed by looking from above, making it difficult to align the protruding electrodes and the lead tips.
（発明の目的）
本発明の目的は前述した従来例の問題点を改善
し、突起電極とリードの接合時の位置合せの容易
性は保持しつつ、シヨートあるいはエツジタツチ
等の問題のない突起電極付フイルムキヤリアを提
供するものである。(Objective of the Invention) The purpose of the present invention is to improve the problems of the conventional example described above, and to provide a protruding electrode without problems such as shooting or edge touching while maintaining ease of positioning when bonding the protruding electrode and the lead. It provides a film carrier.
（発明の構成）
上記目的を達成するために、本発明は半導体素
子の電極部に対応した複数素子分の突起電極を、
予め基板上に形成する場合に、各々の素子分の突
起電極の中で、任意の距離離間した少なく共二点
の突起電極の幅を、フイルムキヤリアのリード端
子先端の幅よりも広く形成した後、前記突起電極
を前記フイルムキヤリアのリード端子に接合転写
することを特徴としたものである。(Structure of the Invention) In order to achieve the above object, the present invention provides protruding electrodes for multiple elements corresponding to the electrode portions of semiconductor elements.
When forming on a substrate in advance, among the protruding electrodes for each element, at least two protruding electrodes spaced apart by an arbitrary distance are formed to have a width wider than the width of the lead terminal tip of the film carrier. , the protruding electrode is bonded and transferred to the lead terminal of the film carrier.
（実施例の説明）
次に本発明の実施例を図を用いて説明する。第
５図は本発明の一実施例であり、半導体素子の電
極に対応した突起電極を形成した基板の上面図を
示す。第５図において基板７上に形成された突起
電極１２−ａ，１２−ｂのうち四隅の突起電極１
２−ｂを他の突起電極１２−ａより大きくなるよ
うに形成したものである。この突起電極１２−
ａ，１２−ｂの大きさはメツキ厚みを一定とすれ
ばメツキ前のマスクパターンの形状により決定さ
れる。通常マスクパターンの幅（Ｗ）と突起電極
の厚さ（Ｈ）と突起電極の幅（WB）との関係は
ほぼWB＝Ｗ＋2Hとなる。本実施例においては四
隅の突起電極１２−ｂの幅は、この突起電極を接
合転写させるフイルムキヤリアのリード端子の幅
よりも広くなるように、その他の突起電極１２−
ａの幅は、前記リード端子の幅と同等か、もしく
は小さくなるようにマスクパターンを形成した。
第６図は、第５図の突起電極を形成した基板を用
いた、突起電極とフイルムキヤリアのリード端子
との接合転写状態の断面図を示している。第６図
ａにおいて基板７上には導電層８が形成され、そ
の上には絶縁材料より成るメツキ用マスク９が形
成され、開口されたマスクパターン面上には突起
電極１２−ａ，１２−ｂがメツキにより形成され
ている。突起電極１２−ａ，１２−ｂ上にはフイ
ルムキヤリアのリード端子１１が位置合せされ
る。この場合、突起電極１２−ａは前記リード端
子１１とほぼ同じ幅であり、両端の突起電極１２
−ｂはリード端子１１よりも広い幅となつてお
り、突起電極１２−ａ，１２−ｂとリード端子１
１との位置合せは、広い幅の突起電極１２−ｂ部
で行われる。第６図ｂはリード端子１１と突起電
極１２−ａ，１２−ｂとが熱圧着により接合（通
常Au−Sn共晶による）され、突起電極１２−
ａ，１２−ｂが基板７の導電層８より剥離した状
態を示している。(Description of Embodiments) Next, embodiments of the present invention will be described with reference to the drawings. FIG. 5 is an embodiment of the present invention, and shows a top view of a substrate on which protruding electrodes corresponding to electrodes of a semiconductor element are formed. In FIG. 5, the protruding electrodes 1 at the four corners of the protruding electrodes 12-a and 12-b formed on the substrate 7
2-b is formed to be larger than the other protruding electrodes 12-a. This protruding electrode 12-
The sizes of a and 12-b are determined by the shape of the mask pattern before plating, assuming that the plating thickness is constant. Normally, the relationship between the width (W) of the mask pattern, the thickness (H) of the protruding electrode, and the width (W B ) of the protruding electrode is approximately W B =W+2H. In this embodiment, the width of the protruding electrodes 12-b at the four corners is wider than the width of the lead terminal of the film carrier to which the protruding electrodes are bonded and transferred.
The mask pattern was formed so that the width of a was equal to or smaller than the width of the lead terminal.
FIG. 6 shows a cross-sectional view of a state in which the protruding electrodes and the lead terminals of the film carrier are bonded and transferred using the substrate on which the protruding electrodes of FIG. 5 are formed. In FIG. 6a, a conductive layer 8 is formed on a substrate 7, a plating mask 9 made of an insulating material is formed on the conductive layer 8, and protruding electrodes 12-a, 12- b is formed by plating. Lead terminals 11 of the film carrier are aligned on the protruding electrodes 12-a and 12-b. In this case, the protruding electrodes 12-a have approximately the same width as the lead terminals 11, and the protruding electrodes 12-a at both ends
-b is wider than the lead terminal 11, and the protruding electrodes 12-a, 12-b and the lead terminal 1
The alignment with the protruding electrode 12-b is performed at the wide protruding electrode 12-b. In FIG. 6b, the lead terminal 11 and the protruding electrodes 12-a, 12-b are joined by thermocompression bonding (usually by Au-Sn eutectic), and the protruding electrode 12-
A and 12-b are shown separated from the conductive layer 8 of the substrate 7.
次に他の実施例を第７図を用いて説明する。第
７図において、基板７上に形成された突起電極１
２−ａ，１２−ｂのうち対角上にある突起電極１
２−ｂの幅を第一の実施例と同様にフイルムキヤ
リアのリード端子の幅よりも広く、他の突起電極
１２−ａの幅を前記リード端子の幅と同等もしく
は小さく形成したものである。したがつてこの場
合、リード端子と突起電極の位置合せは対角上に
ある突起電極１２−ｂを用いて行うことになる。
以下は第一の実施例と同様である。本発明は以上
の二つの実施例の他、半導体素子に対応した突起
電極の中で、任意の距離離間した少なく共二点の
突起電極の幅を、フイルムキヤリアのリード端子
の幅よりも大きくすることで達成することができ
る。 Next, another embodiment will be described using FIG. 7. In FIG. 7, a protruding electrode 1 formed on a substrate 7
Protruding electrode 1 on the diagonal of 2-a and 12-b
Similarly to the first embodiment, the width of the protruding electrode 12-b is wider than the width of the lead terminal of the film carrier, and the width of the other protruding electrode 12-a is equal to or smaller than the width of the lead terminal. Therefore, in this case, the lead terminals and the protruding electrodes are aligned using the diagonally located protruding electrodes 12-b.
The following is the same as the first embodiment. In addition to the above two embodiments, the present invention also provides protruding electrodes compatible with semiconductor devices, in which the width of at least two protruding electrodes spaced apart from each other by an arbitrary distance is made larger than the width of the lead terminal of the film carrier. This can be achieved by
（発明の効果）
以上記述したように本発明によれば突起電極と
フイルムキヤリアのリードとの位置合せに必要な
任意の距離離間した少なく共、二点の突起電極の
幅をリード端子部の幅よりも広く形成し、他の突
起電極は、リード端子の幅かそれ以下とすること
により位置合せの容易性は保持したまま微細なパ
ツドピツチの半導体素子などの接合の際に発生し
やすい突起電極間の短絡を減少させることが可能
となつた。又、同時にリード端子との位置合せに
必要な少なく共二点以外の突起電極の幅を小さく
できることになり、メツキ量を減少することにな
り、したがつてコストの低減もできるものであ
る。(Effects of the Invention) As described above, according to the present invention, the width of the protruding electrodes at at least two points separated by an arbitrary distance necessary for alignment of the protruding electrodes and the leads of the film carrier is equal to the width of the lead terminal portion. By forming the other protruding electrodes wider than the width of the lead terminal, the other protruding electrodes can be formed to be the width of the lead terminal or smaller, thereby maintaining ease of alignment and reducing the gap between the protruding electrodes, which tends to occur when bonding semiconductor devices with fine pad pitches. It has become possible to reduce short circuits. Moreover, at the same time, the width of the protruding electrodes other than at least two points necessary for alignment with the lead terminals can be reduced, the amount of plating can be reduced, and the cost can therefore be reduced.
第１図は従来法による半導体素子の実装法を示
す図、第２図はリード先端部に突起電極を接合す
る方法を示す図、第３図は突起電極の形成された
基板を示す上面図、第４図はリードに接合された
突起電極を半導体素子の電極部に接合する方法を
示す図、第５図は本発明の第一の実施例による突
起電極が形成された基板の上面図、第６図は本発
明の第一の実施例による突起電極付リードの製造
法を示す図、第７図は本発明の第二の実施例によ
る突起電極が形成された基板の上面図である。
７……基板、１１……フイルムキヤリアのリー
ド端子、１２−ａ，１２−ｂ……突起電極。
FIG. 1 is a diagram showing a conventional method for mounting a semiconductor element, FIG. 2 is a diagram showing a method for bonding a protruding electrode to a lead tip, and FIG. 3 is a top view showing a substrate on which a protruding electrode is formed. FIG. 4 is a diagram showing a method of joining a protruding electrode bonded to a lead to an electrode portion of a semiconductor element; FIG. 5 is a top view of a substrate on which a protruding electrode according to the first embodiment of the present invention is formed; FIG. 6 is a diagram showing a method of manufacturing a lead with protruding electrodes according to the first embodiment of the present invention, and FIG. 7 is a top view of a substrate on which protruding electrodes are formed according to the second embodiment of the present invention. 7...Substrate, 11...Lead terminals of film carrier, 12-a, 12-b...Protruding electrodes.
Claims (1)
極のうち、転写形成時にリード端子との位置合せ
用に選択され任意の距離だけ離間した少なくとも
二点の突起電極の幅が前記リード端子群の端子幅
より広く形成されており、残余の突起電極の幅は
端子幅と同一又はそれより狭く形成されているこ
とを特徴とする突起電極付フイルムキヤリア。1 Among the protruding electrodes transferred and formed on a plurality of lead terminal groups, the width of at least two protruding electrodes selected for alignment with the lead terminals at the time of transfer formation and separated by an arbitrary distance is the terminal of the lead terminal group. 1. A film carrier with protruding electrodes, characterized in that the width of the remaining protruding electrodes is equal to or narrower than the terminal width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59060996A JPS60206158A (en) | 1984-03-30 | 1984-03-30 | Film carrier with projecting electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59060996A JPS60206158A (en) | 1984-03-30 | 1984-03-30 | Film carrier with projecting electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60206158A JPS60206158A (en) | 1985-10-17 |
| JPH0462459B2 true JPH0462459B2 (en) | 1992-10-06 |
Family
ID=13158548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59060996A Granted JPS60206158A (en) | 1984-03-30 | 1984-03-30 | Film carrier with projecting electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60206158A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100798896B1 (en) | 2007-06-07 | 2008-01-29 | 주식회사 실리콘웍스 | Pad layout structure of semiconductor chip |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57152147A (en) * | 1981-03-16 | 1982-09-20 | Matsushita Electric Ind Co Ltd | Formation of metal projection on metal lead |
-
1984
- 1984-03-30 JP JP59060996A patent/JPS60206158A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57152147A (en) * | 1981-03-16 | 1982-09-20 | Matsushita Electric Ind Co Ltd | Formation of metal projection on metal lead |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60206158A (en) | 1985-10-17 |
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| EXPY | Cancellation because of completion of term |