JPH0461279A - Vertical mos field effect transistor - Google Patents
Vertical mos field effect transistorInfo
- Publication number
- JPH0461279A JPH0461279A JP17230490A JP17230490A JPH0461279A JP H0461279 A JPH0461279 A JP H0461279A JP 17230490 A JP17230490 A JP 17230490A JP 17230490 A JP17230490 A JP 17230490A JP H0461279 A JPH0461279 A JP H0461279A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- region
- impurity concentration
- semiconductor
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims description 42
- 230000015556 catabolic process Effects 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 210000003127 knee Anatomy 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- FBOUIAKEJMZPQG-AWNIVKPZSA-N (1E)-1-(2,4-dichlorophenyl)-4,4-dimethyl-2-(1,2,4-triazol-1-yl)pent-1-en-3-ol Chemical compound C1=NC=NN1/C(C(O)C(C)(C)C)=C/C1=CC=C(Cl)C=C1Cl FBOUIAKEJMZPQG-AWNIVKPZSA-N 0.000 description 1
- 241000218645 Cedrus Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は半導体装置に関し、特にＤＳＡ構造を持つ縦形
ＭＯＳ電界効果トランジスタ（ＦＥＴ）に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a vertical MOS field effect transistor (FET) having a DSA structure.
［従来の技術］
この種の従来の縦形ＭＯＳＦＥＴの断面図を第３図に示
す。半導体基板はドレイン耐圧を高めるため、ｎ１基板
１上にこれより不純物濃度が低いｎ−エビタキシャル層
２を形成したものが用いられている。ｎ−エピタキシャ
ル層２内には、Ｐ４高不純物濃度領域３を形成Ｌノだ後
、これより不純物濃度が低いＰチヤンネル領域４が形成
され、このＩ’チャンネル領域４内に、ｎ＋ソース領域
５が形成されている。ここでＰ１高不純物濃度領域３．
Ｉ）チャンネル領域４と、ｎ″エピタキシヤルＮ２の間
に形成されるＰＮ接合により、トレイン耐圧が定まる。[Prior Art] A cross-sectional view of a conventional vertical MOSFET of this type is shown in FIG. In order to increase the drain breakdown voltage, the semiconductor substrate used is one in which an n-evitaxial layer 2 having a lower impurity concentration is formed on an n1 substrate 1. After forming a P4 high impurity concentration region 3 in the n- epitaxial layer 2, a P channel region 4 with a lower impurity concentration is formed in the I' channel region 4, and an n+ source region 5 is formed in this I' channel region 4. It is formed. Here, P1 high impurity concentration region 3.
I) The train breakdown voltage is determined by the PN junction formed between the channel region 4 and the n'' epitaxial layer N2.
ｎ゛ソース領域５及びｉｌ−エピタキシャル層２と１）
チャンネル領域４上には、ゲート酸化膜（絶縁膜）６を
介して、多結晶シリコンを用いたゲート電極７が形成さ
れている。n゛source region 5 and il-epitaxial layer 2 and 1)
A gate electrode 7 made of polycrystalline silicon is formed on the channel region 4 with a gate oxide film (insulating film) 6 in between.
中間絶縁層８がゲート酸化膜６とゲート電極７を被うよ
うここ形成され、その上にソース電極９がＰチヤンネル
領域４と、ｎ゛ソース領域５に接続″する杉で形成され
ている。An intermediate insulating layer 8 is formed here to cover the gate oxide film 6 and the gate electrode 7, and thereon a source electrode 9 is formed of cedar which is connected to the P channel region 4 and the source region 5.
［発明が解決しようどする課題］
この従来の縦形ＭＯＳＦＥＴは、その内部に、ｎ〜エピ
タキシャル層２の１１−層をコレクタ、■）チャンネル
領域４の■）領域をベース、ｎ°ソー・ス領域５のｎ゛
領域ニーミッタとする寄生バ、イボーラトランジスタが
形成される構造とな−）こおり、」フージの発生により
次のような問題が牛じバζしＪ、・λ（いた。[Problem to be solved by the invention] This conventional vertical MOSFET has an n~11- layer of epitaxial layer 2 as a collector, ■) a channel region 4 as a base, and an n° source region. In the structure in which an Ibora transistor and a parasitic barrier are formed as n-region knee emitters of 5, the following problems arise due to the occurrence of fuges.
サージ印加時の電流針路１ジ１を第７１［イｊに示す。The current course 1 when a surge is applied is shown in the 71st [Ij.
負荷電流を遮断した際、ドレイン耐１４１を超える高電
圧のす・−ジが発生すると、このサージはｎ エピタキ
シャル層２と、■）チャンネル領域、、／１の間のＰＮ
接合のニーづ一部ａに加わりやすい。ぞ−して、ぞのコ
ーナ一部ａ、で、アバランシェ降伏を起ｆｆ”、、 Ｌ
７、そのブレークダウン電流ｌ〕がｒ）チャネル領域１
１を経てソース電極９に池、れる４、
Ｐチヤンネル領域４は、前記のよ・うに寄生バイポーラ
トランジスタのベース領域に半Ｈ当するので、そのベー
ス抵抗が大きいと、ブレークダウン電流すによる電圧効
果で、寄生バイポーラトランジスタのエミッタ・へ゛−
ス開が順バイアスされ、この結果、寄生バイポーラトラ
ンジスタはオン状態どなり、発熱り、ざらζこ電流が増
大するといった内部現象により破壊傾向が生じるとい・
う問題があった。When the load current is cut off, if a high voltage surge exceeding the drain resistance 141 occurs, this surge will cause the PN between the epitaxial layer 2 and the channel region, /1
It is easy to join the joint knee part a. Then, avalanche surrender occurred at part a of the corner.ff",,L
7, its breakdown current l] is r) channel region 1
As mentioned above, the P channel region 4, which is connected to the source electrode 9 through the P channel region 4, corresponds to half the base region of the parasitic bipolar transistor, so if its base resistance is large, the voltage effect due to the breakdown current will be reduced. Then, the emitter of the parasitic bipolar transistor
As a result, the parasitic bipolar transistor turns on, generates heat, and tends to break down due to internal phenomena such as increased current.
There was a problem.
［課題を解決するための丁段コ
本発明の縦形ＭＯＳＦＥ’ｌ”は、ｎ１工ピタキシヤル
層とＰチャンネル領域とのＰＮ接合の：２−ナー部での
アバランシェ降伏を起こしにくくするために、ｎ＋基板
に逆バイアス電圧を加えたとぎ、Ｐ゛高不純物濃度領域
でｎ−エピタキシャル層の方にのびる空乏層が、Ｐチャ
ンネル領域のコーナ一部でのＰＮ接合の耐圧より、低い
電圧で、ｎ−基板にぶつかり、リーチスルーを起こす様
な深さに押し込んだＰ４高不純物濃度領域を備えている
。[To solve the problem] The vertical MOSFE'l'' of the present invention has an n+ When a reverse bias voltage is applied to the substrate, the depletion layer extending toward the n- epitaxial layer in the P high impurity concentration region forms an n- It has a P4 high impurity concentration region that is pushed to a depth that hits the substrate and causes reach-through.
すなわち、第１導電形の半導体基板と、この半導体基板
上に、形成された当該半導体基板よりは、不純物濃度の
低い第１導電形の半導体層と、この半導体層内に形成さ
れた第２導電形の半導体領域と前記第１導電形の半導体
層の輪状の内部の前記第２導電形の半導体領域下部に接
して形成されて当該第２導電形の半導体領域より、不純
物濃度が高い、第２導電形の高不純物濃度領域と第２導
電形の半導体領域に輪状に形成された第１導電形の半導
体領域と、この輪状に形成された第１導電形の゛１′、
導体領域及び前記第２導電形の半導体領域ト。That is, a semiconductor substrate of a first conductivity type, a semiconductor layer of a first conductivity type formed on this semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, and a second conductivity type formed in this semiconductor layer. a second conductivity type semiconductor region formed in contact with a lower part of the second conductivity type semiconductor region inside the ring-shaped semiconductor layer of the first conductivity type and having a higher impurity concentration than the second conductivity type semiconductor region; a semiconductor region of a first conductivity type formed in a ring shape in a high impurity concentration region of a conductivity type and a semiconductor region of a second conductivity type;
a conductor region and the second conductivity type semiconductor region;
にケート絶縁膜を介して配設されたゲート電極とを有゛
４る縦形ＭＯＳ電界効果トランジスタにおいて、前記第
１導電形の半導体層と０月）Ｎ接合の前記半導体基板に
電圧を加えたときに、前記第２導電形の高不純物濃度領
域から第１導電形の半導体層へのびる空乏層が、第２導
電形の半導体領域のコーナ一部と第１導電形の半導体層
とのＰＮ接合の耐圧より低い電圧で、第１導電形の半導
体基板に到達する深さに前記第２導電形の高不純物濃度
領域を形成したことを特徴とする。In a vertical MOS field effect transistor having a gate electrode disposed through a gate insulating film, when a voltage is applied to the semiconductor layer of the first conductivity type and the semiconductor substrate in an N junction. The depletion layer extending from the second conductivity type high impurity concentration region to the first conductivity type semiconductor layer forms a PN junction between a part of the corner of the second conductivity type semiconductor region and the first conductivity type semiconductor layer. The semiconductor device is characterized in that the high impurity concentration region of the second conductivity type is formed at a depth that reaches the semiconductor substrate of the first conductivity type at a voltage lower than the breakdown voltage.
［実施例コ 次に本発明について、図面を参照して説明する。[Example code] Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例に係る縦形ＭＯ３ＦＥＴの断
面図である。半導体基板はｎ゛基板１上に、ｎ−エピタ
キシャル層２を形成したものを用いている。FIG. 1 is a sectional view of a vertical MO3FET according to an embodiment of the present invention. The semiconductor substrate used is one in which an n-epitaxial layer 2 is formed on an n-substrate 1.
エピタキシャル層２の内には、Ｐ″高不純物濃度領域３
を形成した後、Ｐチヤンネル領域４を形成し１・である
。このＰ＋高不純物濃度領域３は、１１゛茫析１に電月
、を加えたどき、Ｐ′高不純物濃度領域ニオで、１〕
エピタキシＡ・ル層２の方（・”のびる空乏層が、Ｉ−
〉チャンネル領域４の一ノーナー・部ａ、ての）’Ｎ按
ａの耐圧より、低い電圧て′、丁ビ基板」にぶつか４様
な深さに押し込み形成しである。In the epitaxial layer 2, there is a P″ high impurity concentration region 3.
After forming P channel region 4, step 1. This P+ high impurity concentration region 3 is P′ high impurity concentration region 1]
The epitaxy A/L layer 2 (・”The extending depletion layer is I-
〉One corner part a of the channel region 4 is pressed into the substrate at a voltage lower than the withstand voltage of 〉N㉉a〉to a different depth.
そしｙ”’Ｃ，Ｐチャンネル領域７１内ここ、ｉ”ｌ＋
ソース領域５が形成され、１１″′ソース領域らおよび
ｉｉ エピタキシ４・ノＬ層２とＰチャンネル領域７１
１Ｊには、ケ゛゛−Ｉ−酸化膜（絶縁膜）６を介し・で
多結晶シリ−７ンを用いたゲート電極７が形成し、で゛
ある。・ぞし・で。Then y'''C, P here in the channel area 71, i''l+
A source region 5 is formed, 11'' source region et al. and ii epitaxial layer 2 and a P channel region 71.
A gate electrode 7 using polycrystalline silicon 7 is formed on the gate electrode 1J with a silicon oxide film (insulating film) 6 interposed therebetween.・Zoshi・de.
中間絶縁層８をゲー用・酸化１ｍ（３ど、ゲ・〜叫・電
極゛ｉを被うように形成し・、そのｊ、に、ソース電極
９をＰベース領域４ど１１４ソース領域ζこ接続４”る
形て形成しマある。An intermediate insulating layer 8 is formed with 1 m of oxidation layer (3, 3, 3, 3, 4, 4, 5, 4, 5, 4 layers, covering the 114 source regions ζ). It is possible to form a connection 4".
次に、その動作についで説明する。Next, its operation will be explained.
この実施例こ（，４１、トしイン耐圧を越える高電汀６
（ノーンが加わると、■）チャンネル領域ｌ］、の−ズ
ー・ナ一部２Ｉの耐圧より、低い電圧でＰ＋高不純物濃
度領域３がリーチスルーを起ごずようにしまたたぎ〕、
こ′の１ノ・〜ジがＰ゛高不純物濃度領域、；３に加わ
り易くなり、■戸高不純物濃度領域：３−（アバ−〉ン
シ１．険法を起こし！、そのブＬ／−クダウン電治、は
曲線的な経路てぞのＪ：まソース電極９４Ｑ’−；■れ
る。This example (, 41, high voltage exceeding the input breakdown voltage 6
(When non is added, ■) the channel region l], the -zu na part 2I straddled so that the P+ high impurity concentration region 3 does not reach through at a voltage lower than the withstand voltage of the part 2I],
This '1 No. ~ ji easily joins P゛ high impurity concentration region; Denji's curved path leads to the source electrode 94Q'-;
［発明の効果コ
以上説明したよ・−）に、本発明の縦形Ｍ ＯＳ Ｆ
ＦＴは、高電圧サージが１Ｌ′ｆ？・ンネル領域ニー
ｌ・−８１３より１〉°高不純物濃度領域ζ１：加わり
易＜ Ｌ、ｙ、イーの鈷宋ブ１．／−クダウン電流か、
Ｐ゛高不純物濃追領域から１）・Ｊヤンネル領域どノ・
−スミ極どの接合部を通り、ソース電極へ）が［、れる
の（、寄仕ハイボー″ントランジスタがオン状態（、、
−なりにくくなり、このためによる発熱は起こらず、破
壊傾向が生じここくくなるという効果を有する。[The effects of the invention have been explained above], the vertical MOSFET of the present invention
FT has a high voltage surge of 1L'f?・Nel area knee
1〉°high impurity concentration region ζ1 from l・-813: easy to add < L, y, E's Gongsongbu 1. /-down current,
From P゛high impurity concentration region 1), J channel region,
- Through which junction of the sumi electrodes and the source electrodes pass through (to the source electrodes).
- This has the effect of making it less likely to cause heat generation due to this, and making it more difficult to cause a tendency to break.
第１図は本発明の一実施例の断ｍ図、第一２．図は本発
明の一実施例の１ノ一ジ印加時の電ｄ１．経銘を説明”
する概念図、第：３図はｉＮ来の縦形ＭＯΣ−； Ｆ
Ｅ Ｔの断面図、第４１ｆｆｌ ：ｉ ｉ’＋′ＩＴ、
Ｅ ｔ；っｈ’ｔ 形１’ｉ （い−； Ｆ Ｅ Ｔの
１カー何、印加時の電流経路４］・説明する侃、’６Ｈ
ｌイｌでＬ；５ ’Ｓ （。
１ ・ ・ ・ ・ ・ ・ ・ ｒｉ ″基＋反２′
）・・・・・・・ｒｉ ’エビタギジャル１蕾、３・・
・・・・・１）″高不純物濃度領域、！■・・・・・・
・Ｐチャンネル領域、５・・・・・・・丁）゛ソース領
域、
〔逼・・・・・・・ゲー ト酸化膜、
７・・・・・・・ケート電極、８
８・・・・・・・中間絶縁膜、
９・・・・・・・ソース電極。
第、ろ囚
特許出願人 日本電気株式会社FIG. 1 is a sectional view of one embodiment of the present invention. The figure shows the voltage d1 when one voltage is applied according to an embodiment of the present invention. Explaining the sutra inscription”
Figure 3 is a conceptual diagram of the vertical MOΣ-; F
ET cross-sectional view, 41st ffl: i i'+'IT,
E t; っ h't form 1'i (I-; 1 car of F E T, current path 4 when applied)・Explain, '6H
1 ・ ・ ・ ・ ・ ・ ri ″ group + anti 2′
)・・・・・・ri 'Evitagijaru 1 bud, 3...
・・・・・・1) ″High impurity concentration region,!■・・・・・・
・P channel region, 5....... Source region, 〼... Gate oxide film, 7... Gate electrode, 8 8... ...Intermediate insulating film, 9...Source electrode. No. 1 patent applicant: NEC Corporation
Claims (1)
成された当該半導体基板よりは、不純物濃度の低い第１
導電形の半導体層と、この半導体層内に形成された第２
導電形の半導体領域と前記第１導電形の半導体層の輪状
の内部の前記第２導電形の半導体領域下部に接して形成
されて当該第２導電形の半導体領域より、不純物濃度が
高い、第２導電形の高不純物濃度領域と第２導電形の半
導体領域に輪状に形成された第１導電形の半導体領域と
、この輪状に形成された第１導電形の半導体領域及び前
記第２導電形の半導体領域上にゲート絶縁膜を介して配
設されたゲート電極とを有する縦形ＭＯＳ電界効果トラ
ンジスタにおいて、前記第１導電形の半導体層とのＰＮ
接合の前記半導体基板に電圧を加えたときに、前記第２
導電形の高不純物濃度領域から第１導電形の半導体層へ
のびる空乏層が、第２導電形の半導体領域のコーナー部
と第１導電形の半導体層とのＰＮ接合の耐圧より低い電
圧で、第１導電形の半導体基板に到達する深さに前記第
２導電形の高不純物濃度領域を形成したことを特徴とす
る縦形ＭＯＳ電界効果トランジスタ。a first conductivity type semiconductor substrate; a first conductivity type semiconductor substrate formed on the semiconductor substrate;
A conductive type semiconductor layer and a second semiconductor layer formed within this semiconductor layer.
A second conductivity type semiconductor region is formed in contact with a lower part of the second conductivity type semiconductor region inside the ring-shaped semiconductor layer of the first conductivity type and has a higher impurity concentration than the second conductivity type semiconductor region. a semiconductor region of a first conductivity type formed in a ring shape in a high impurity concentration region of a second conductivity type and a semiconductor region of a second conductivity type; a semiconductor region of the first conductivity type formed in a ring shape and the second conductivity type; a vertical MOS field effect transistor having a gate electrode disposed on a semiconductor region of the semiconductor layer with a gate insulating film interposed therebetween;
When a voltage is applied to the semiconductor substrate of the junction, the second
The depletion layer extending from the high impurity concentration region of the conductivity type to the semiconductor layer of the first conductivity type is at a voltage lower than the breakdown voltage of the PN junction between the corner part of the semiconductor region of the second conductivity type and the semiconductor layer of the first conductivity type, A vertical MOS field effect transistor, characterized in that the high impurity concentration region of the second conductivity type is formed at a depth that reaches a semiconductor substrate of the first conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17230490A JPH0461279A (en) | 1990-06-28 | 1990-06-28 | Vertical mos field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17230490A JPH0461279A (en) | 1990-06-28 | 1990-06-28 | Vertical mos field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0461279A true JPH0461279A (en) | 1992-02-27 |
Family
ID=15939443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17230490A Pending JPH0461279A (en) | 1990-06-28 | 1990-06-28 | Vertical mos field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0461279A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997016853A1 (en) * | 1995-11-02 | 1997-05-09 | National Semiconductor Corporation | Insulated gate semiconductor devices with implants for improved ruggedness |
| US5701023A (en) * | 1994-08-03 | 1997-12-23 | National Semiconductor Corporation | Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness |
-
1990
- 1990-06-28 JP JP17230490A patent/JPH0461279A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701023A (en) * | 1994-08-03 | 1997-12-23 | National Semiconductor Corporation | Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness |
| US5897355A (en) * | 1994-08-03 | 1999-04-27 | National Semiconductor Corporation | Method of manufacturing insulated gate semiconductor device to improve ruggedness |
| WO1997016853A1 (en) * | 1995-11-02 | 1997-05-09 | National Semiconductor Corporation | Insulated gate semiconductor devices with implants for improved ruggedness |
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