JPH0461135A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0461135A JPH0461135A JP2164583A JP16458390A JPH0461135A JP H0461135 A JPH0461135 A JP H0461135A JP 2164583 A JP2164583 A JP 2164583A JP 16458390 A JP16458390 A JP 16458390A JP H0461135 A JPH0461135 A JP H0461135A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- opening
- resist
- film
- metallic film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 12
- 230000008020 evaporation Effects 0.000 abstract description 3
- 238000001704 evaporation Methods 0.000 abstract description 3
- 150000002739 metals Chemical class 0.000 description 3
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000008096 xylene Substances 0.000 description 2
- 241000288673 Chiroptera Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 235000011389 fruit/vegetable juice Nutrition 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は半導体装置の製造方法に係り、特にポンディン
グパッド用金属層の形成方法を改良し、再現性、安定性
に優れ信頼性の高いポンディングパッドを製造する方法
に関する。[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular improves a method for forming a metal layer for a bonding pad to improve reproducibility and stability. This invention relates to a method for manufacturing superior and reliable bonding pads.
（従来の技術）
ＧａＡｓ基板上に形成されたショットキー接合電界効果
トランジスタ（以下ＭＥＳＦＥＴと略称する）は、ソー
ス電極、ゲート電極、ドレイン電極と各電極のボンディ
ング用パッドで構成されている。ボンディング用パッド
は、腐蝕されにくく安定でしかもポンデイグ性の良好な
金属膜で構成され、また、各電極（ソース電極、ゲート
電極、ドレイン電極）やＧａＡｓ基板との接触面で素子
特性を劣化させるような反応が進まない金属で構成され
ることが要求されており、一般に例えばＡｕ ／ Ｎｏ
／ Ｔｉのような積層構造が使われている。以下、従
来のＭＥＳＦＥＴの製造方法について第２図（ａ）〜（
ｄ）を参照して説明する。第２図（ａ）に示すように、
半絶縁性ＧａＡｓ基板２１上に高純度ＧａＡｓバッファ
層２２．ｎ型の導電性を持った能動層２３が積層され、
この能動層２３上にオーム性接触よりなるソース電極２
４．ドレイン電極２５を形成した後、ソース電極２４、
ドレイン電極２５に挾まれた領域に例えばＡ１を用いた
、ショットキー接合よりなるゲート電極２６を形成する
０次に第２図（ｂ）に示すように、レジスト膜２７を全
１ｈｆに塗布し、このレジスト膜２７を所定の形状にパ
ター・ニングする。ついで第２図（ｅ） Ｌ：示す、よ
・うに、ポンディングパッド用金属膜２８、例えばＡｕ
／Ｎｏ／Ｔｉを全面に蒸着する。次いで、リフトオフ法
によ−）でレジスト２７ 、、Ｊ−の金属膜２８をごの
エツジスト２７とともに除去し、第２図（ｄ）に示すＭ
ＥＳＦＥＴが完成する。(Prior Art) A Schottky junction field effect transistor (hereinafter abbreviated as MESFET) formed on a GaAs substrate is composed of a source electrode, a gate electrode, a drain electrode, and bonding pads for each electrode. The bonding pad is made of a metal film that is resistant to corrosion, stable, and has good bonding properties, and is made of a metal film that does not deteriorate the device characteristics at the contact surface with each electrode (source electrode, gate electrode, drain electrode) or the GaAs substrate. It is required to be composed of a metal that does not undergo a serious reaction, and is generally made of a metal such as Au/No.
/ A laminated structure such as Ti is used. Below, the conventional MESFET manufacturing method will be explained in Figs. 2(a) to (
This will be explained with reference to d). As shown in Figure 2(a),
A high purity GaAs buffer layer 22. is formed on a semi-insulating GaAs substrate 21. An active layer 23 having n-type conductivity is laminated,
A source electrode 2 made of ohmic contact is placed on this active layer 23.
4. After forming the drain electrode 25, the source electrode 24,
A gate electrode 26 made of a Schottky junction using, for example, A1 is formed in the region sandwiched by the drain electrode 25. Next, as shown in FIG. 2(b), a resist film 27 is applied to the entire 1hf. This resist film 27 is patterned into a predetermined shape. Then, as shown in FIG. 2(e), a metal film 28 for a bonding pad, for example, Au
/No/Ti is deposited on the entire surface. Next, the metal film 28 of the resist 27, .
ESFET is completed.
（発明が解決しようとする課題）
叙−１−の従来の方法では、ポンディングパッド用のメ
タルＡυ／Ｍｏ／Ｔｉは同一のレジストパターンで蒸着
、リフトオフを行なっており、理想的しＪはＡｕ／Ｍｏ
／Ｔｉが第；３図（ａ）に示すように奇麗な積層構造と
なる。しかし現実の蒸着では、基板に対して蒸着金属が
垂直に入射する条件から多少なりともずれる、段差部分
のステップカバレッジが必ずし、も良くない、積層メタ
ルの最」一部に使われるＡｕのような物質は他の積層メ
タルであるＴｊ−３ＭＯのような金属よりも厚くするこ
とが一般的である等の理由から、第３図（ｂ）に示すよ
うにＡｕ層３４１がＧａＡｓ基板と接触したり、第３図
（ｂ）に破線円で囲んで示すようにＡｕ層３４２がゲー
トメタルであるＡ１層と接触したりする部分が生じる。(Problems to be Solved by the Invention) In the conventional method described in Section 1-1, the metals Aυ/Mo/Ti for the bonding pad are deposited and lifted off using the same resist pattern, and the ideal J is Au. /Mo
/Ti is No.; As shown in FIG. 3(a), a beautiful laminated structure is formed. However, in actual evaporation, there is a slight deviation from the condition in which the evaporated metal is incident perpendicularly to the substrate, and the step coverage at the stepped portion is not always good. For this reason, the Au layer 341 is in contact with the GaAs substrate as shown in FIG. In addition, there is a portion where the Au layer 342 comes into contact with the A1 layer, which is the gate metal, as shown by the broken line circle in FIG. 3(b).
これレコより、この部分でＡｕ−ＧａＡｓやＡｕ−Ａ１
巻・生成、する反応４起こし、抵抗値の増大等の特性変
動が起きるなどの信頼性に関する問題点があった。From this record, in this part Au-GaAs and Au-A1
There were problems with reliability, such as winding/formation, reaction 4, and fluctuations in characteristics such as an increase in resistance.
本発明は１−記従来の欠点を改良し、再現性と安定性に
優れ信頼性の高いボンディングバットの製造方法を提供
することを目的とするものである。It is an object of the present invention to improve the conventional drawbacks described in 1-1 and to provide a method for manufacturing a bonding bat that is excellent in reproducibility and stability and is highly reliable.
（課題を解決するための手段）
本発明に係る半導体装置の製造方法は、′４″、導体基
板」−のフォトレジスト膜に」一部が下部よりも狭い開
［］す設ける工程と、前記半導体基板を開Ｅ】を中心に
回転させるとともにこの開口に対し斜め方向から蒸着物
質を入射させ第一の金属膜を形成する工程と、前記間Ｕ
に対し垂直上方から蒸着物質を入射させ第二の金属膜を
形成する工程と、前記フォトレジスト膜上の第一および
第二の両金属膜をフォトレジスト膜とともにリフトオフ
除去する工程を含むものである６
（作 用）
本発明によれば、Ａｕ−ＧａＡｓや＾ｕ−Ａｌを生成す
るなどの反応しやすい物質同志の接触を避けることがで
き、半導体装置のボンディング用金属膜が、高い信頼性
で、再現性よく形成できる。(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes the steps of providing an opening in the photoresist film of the conductor substrate, in which a part is narrower than the lower part; forming a first metal film by rotating the semiconductor substrate around the opening E and injecting a vapor deposition material from an oblique direction into the opening;
The method includes a step of injecting a vapor deposition material from vertically above to form a second metal film, and a step of lift-off removing both the first and second metal films on the photoresist film together with the photoresist film. Effect) According to the present invention, it is possible to avoid contact between easily reactive substances such as those that generate Au-GaAs and u-Al, and the metal film for bonding of semiconductor devices can be reproducibly and reliably bonded. Can be formed easily.
（実施例）
以下２本発明の一実施例にかかる半導体装置の製造方法
について、これを工程順に示す第１図（、）〜（ｅ）を
参照して説明する。第１図（ａ）に示すように、高純度
ＧａＡｓバッファ層１２、ｎ型導電性の能動層１３が積
層して形成された半絶縁性基板１１における該能動層１
．３ｆに例えばＮｉ／ＡｕＧｅで構成され、オーム性接
触より成るソース電極１４、ドレイン電極１５を形成し
た後、ドレイン電極１５とソース電極１４に挾まれた領
域に、例えばＡ１を用いたショットキー接合よりなるゲ
ート電極１６を形成する６次に第１図（ｂ）に示すよう
に、レジスト１７を塗布し１例えばキシレンデイツプ処
理等の方法を用い、露光、現像によりレジスト上部の開
孔サイズが、レジスト下部の開孔サイズよりも小さい、
いわゆるオーバーハング形状の断面を持った開孔１７ａ
を所定の形状にパターンニングする。次に第］−図（Ｃ
）に示すように、前記半導体基板１】を回転させかつ該
半導体基板１１に対し所望の角度で斜め方向から第一の
ポンディングパッド用金属膜１８、例えばＮｏ／Ｔｉを
全面に蒸着する。次に第１図（ｄ）に示すように、前記
半導体基板１１に垂直に第二の金属膜１９、例えばＡｕ
を入射させる。さらに、レジスト膜１７上の第一の金属
膜１８と、第二の金属膜１９、レジスト膜１７をリフト
オフ法によって除去し、第１図（ｅ）に示すＭＥＳＦＥ
Ｔが完成する。(Embodiment) A method of manufacturing a semiconductor device according to two embodiments of the present invention will be described below with reference to FIGS. As shown in FIG. 1(a), the active layer 1 in a semi-insulating substrate 11 is formed by laminating a high-purity GaAs buffer layer 12 and an n-type conductive active layer 13.
．． After forming a source electrode 14 and a drain electrode 15 made of, for example, Ni/AuGe and having ohmic contact on 3f, a Schottky junction using, for example, A1 is formed in the region sandwiched between the drain electrode 15 and the source electrode 14. 6. Next, as shown in FIG. 1(b), a resist 17 is applied, and by exposing and developing the resist 17, for example, xylene dip treatment is used to form the gate electrode 16, as shown in FIG. 1(b). smaller than the aperture size at the bottom of the resist,
Opening hole 17a with a so-called overhang-shaped cross section
patterned into a predetermined shape. Next] - Figure (C
), the semiconductor substrate 1 is rotated and a first bonding pad metal film 18, for example No/Ti, is deposited on the entire surface of the semiconductor substrate 11 from an oblique direction at a desired angle. Next, as shown in FIG. 1(d), a second metal film 19, for example, an Au film, is formed perpendicularly to the semiconductor substrate 11.
is made incident. Furthermore, the first metal film 18, second metal film 19, and resist film 17 on the resist film 17 are removed by a lift-off method, and the MESFE shown in FIG.
T is completed.
上記実施例から明らかなように、本発明にかかる製造方
法で形成したＭＥＳＦＥＴは、第一のポンディングパッ
ド用金属膜であるＮｏ／Ｔｉの蒸着にあたり、半導体基
板を回転させこれに斜め方向から蒸着するのでステップ
カバレッジ良く形成でき、さらに第二のポンディングパ
ッド用金属膜である＾Ｕが。As is clear from the above examples, in the MESFET formed by the manufacturing method according to the present invention, the semiconductor substrate is rotated and the No/Ti film, which is the first bonding pad metal film, is vapor-deposited from an oblique direction. Therefore, it is possible to form a step with good step coverage, and in addition, the second bonding pad metal film ^U can be formed.
第一のポンディングパッド用金属膜であるＮｏ／Ｔｉよ
り小さいという形状がセルフアライメントで形成できる
。このため、従来法の欠点であったｍｕ−ＧａＡｓやＡ
ｕ−ＡＵを生じるような反応しやすい金属同志の接触を
避けることができ、このことに起因する特性変動による
信頼性上の問題を解決することができる。A shape smaller than the No/Ti metal film for the first bonding pad can be formed by self-alignment. Therefore, mu-GaAs and A
It is possible to avoid contact between metals that are likely to react and cause u-AU, and it is possible to solve reliability problems due to characteristic fluctuations caused by this.
なお、上記実施例ではオーバーハング形状のレジストパ
ターンを形成するのにキシレンデイツプ処理を用いたが
他の方法、例えば多層レジストによる方法でもよく、半
導体層、金属膜シこつぃても上記に限られない。更に５
本発明はＭＥＳＮＥＴのみならず、高電子移動度トラン
ジスタ、あるいは集積回路等にも活用できる。In the above example, xylene dip treatment was used to form the overhang-shaped resist pattern, but other methods, such as a method using a multilayer resist, may be used, and even if a semiconductor layer or a metal film is used, the method is not limited to the above. I can't. 5 more
The present invention can be applied not only to MESNET but also to high electron mobility transistors, integrated circuits, etc.
以上述べたように本発明で形成した半導体装置は、第一
のポンディングパッド用金属膜をカバレッジ良く形成で
き、また１反応性の高い第二のポンディングパッド用金
属膜を第一のポンディングパッド用金属膜よりも小さく
形成することができる。このため、第二のポンディング
パッド用金属膜と反応しやすい、下地半導体や金属同志
の接触を避けることができ、これに起因する特性変動な
どの信頼性上の問題が解決できた。さら１．、：、、
、、１：記のような特徴を持つボンディングバット用金
属膜の形成がセルフアライメントで形成できるため、微
細なパターン・に、または集積度の高いパターンに対し
ても再現性、安定性良く達成できる効果がある。As described above, in the semiconductor device formed according to the present invention, the first metal film for bonding pads can be formed with good coverage, and the second metal film for bonding pads with high reactivity can be formed in the first bonding pad. It can be formed smaller than the pad metal film. Therefore, it was possible to avoid contact between the underlying semiconductor and the metals, which tend to react with the second bonding pad metal film, and it was possible to solve reliability problems such as characteristic fluctuations caused by this. Further 1. , :,,
,,1: Since the metal film for bonding bats with the characteristics described below can be formed by self-alignment, it can be achieved with good reproducibility and stability even for fine patterns or patterns with a high degree of integration. effective.
第１図（ａ）〜（ｅ）は本発明の一実施例番４゛かかる
ＭＥＳＦＥＴの製造方法を工程順に示すいずれも断面図
、第２図（、）〜（ｄ）は従来のＭＥＳＦＥＴの製造方
法を工程順に示すいずれも断面図、第３図（ａ）〜（ｂ
）は従来方法でポンディングパッド用金属膜を形成しま
た場合の欠点を説明するためのいずれも断面図である。
１１・・・半絶縁性ＧａＡｓ基板、１２・・・ＧａＡｓ
バッファ層、１３・・・能態層、１７・・フォトレジス
ト層、１８・・・第１のポンディングパッド用金属膜、
。
１９・・・第２のポンディングパッド用金属膜。
代理人 弁理士 大 胡 典 失
１ｍ４ｅＪシ＆ ４Ｅ Ｇ ａ Ａｓ ＪＥＪ ｋ。
１２： 帛吐瑣ＱａＡＳバ、７７層
１９： １へ２１Ｆｌ汁：）デ１ンフ゛パプド用塗属月
斐！７：ｔ５ンストノー
１７ａ ： Ｌ９．ｚｒ層ｎ１ｆ１子し第 １ 図
（ｑ丙２）
１８ ：ＩＡ ＋の、ぢンガンフ゛バ、ド用４シ島ル１
第 １１！１Ｉｎ（ｙの１）
、＞３：ｆ！動層 ２４．ソースｔ＆ ２５−
ＦＦインｆ七に２６； ケート１１絃に
第 ２ 図 （号の１）
しりスト膜
２７ａ ： Ｌ ＊ ２ｌ−）１％ ａｙ ％ ロ２
８：
本ン１ンヂ、ぐッ）″Ｗ５ジＲ更
鼾
図
（ｖａ２）
３１ ： ｅａＡｓ耘
３４１ ： Ａｕ層
３２ ： ｒｉ層
３５：Ｍ層
３３：Ｍｏ層
３４２：立層
果
凶FIGS. 1(a) to (e) are cross-sectional views showing the manufacturing method of MESFET according to the fourth embodiment of the present invention in order of process, and FIGS. 2(a) to (d) are sectional views of conventional MESFET manufacturing method. 3(a) to 3(b) are cross-sectional views showing the method in the order of steps.
) are cross-sectional views for explaining the drawbacks of forming a metal film for a bonding pad using a conventional method. 11... Semi-insulating GaAs substrate, 12... GaAs
buffer layer, 13... active layer, 17... photoresist layer, 18... first bonding pad metal film,
. 19... Second bonding pad metal film. Agent Patent Attorney Nori Ogo Loss 1m4eJshi & 4EGa As JEJk. 12: QaAS bar, 77 layers 19: 21Fl juice to 1:) De 1 pump for application! 7: t5 strike no 17a: L9. Figure 1 (q 2)
11th!1In (1 of y), >3: f! Dynamic layer 24. sauce t&25-
FF in f7 26; Kate 11 string 2 Figure (No. 1) Last film 27a: L * 2l-) 1% ay % ro 2
8: Hon 1 nji, ugh)''W5jiR drawing (va2) 31: eaAs耘341: Au layer 32: ri layer 35: M layer 33: Mo layer 342: Standing layer result
Claims (1)
狭い開口を設ける工程と、前記半導体基板を開口を中心
に回転させるとともにこの開口に対し斜め方向から蒸着
物質を入射させ第一の金属膜を形成する工程と、前記開
口に対し垂直上方から蒸着物質を入射させ第二の金属膜
を形成する工程と、前記フォトレジスト膜上の第一およ
び第二の両金属膜をフォトレジスト膜とともにリフトオ
フ除去する工程を含む半導体装置の製造方法。forming an opening in a photoresist film on a semiconductor substrate, the upper part of which is narrower than the lower part, and rotating the semiconductor substrate around the opening and injecting a vapor deposition substance into the opening from an oblique direction to form a first metal film. a step of injecting a vapor deposition material from vertically above into the opening to form a second metal film; and a step of lifting off and removing both the first and second metal films on the photoresist film together with the photoresist film. A method for manufacturing a semiconductor device including a process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2164583A JPH0461135A (en) | 1990-06-22 | 1990-06-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2164583A JPH0461135A (en) | 1990-06-22 | 1990-06-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0461135A true JPH0461135A (en) | 1992-02-27 |
Family
ID=15795931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2164583A Pending JPH0461135A (en) | 1990-06-22 | 1990-06-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0461135A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5737642A (en) * | 1994-09-07 | 1998-04-07 | Canon Kabushiki Kaisha | Camera having a line-of-sight detecting means |
-
1990
- 1990-06-22 JP JP2164583A patent/JPH0461135A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5737642A (en) * | 1994-09-07 | 1998-04-07 | Canon Kabushiki Kaisha | Camera having a line-of-sight detecting means |
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