JPH045942U - - Google Patents
Info
- Publication number
- JPH045942U JPH045942U JP4453390U JP4453390U JPH045942U JP H045942 U JPH045942 U JP H045942U JP 4453390 U JP4453390 U JP 4453390U JP 4453390 U JP4453390 U JP 4453390U JP H045942 U JPH045942 U JP H045942U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- cpu
- inputs
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Editing Of Facsimile Originals (AREA)
- Dot-Matrix Printers And Others (AREA)
- Color, Gradation (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
第１図の各部の動作を説明するタイミングチヤー
ト、第３図はレーザープリンタの制御回路の一例
を示す図、第４図は従来の画素密度判定装置の回
路例図である。
１……マイクロコンピユータ（ＣＰＵ）、２…
…画像書込み制御回路（ＬＳＩ）、６−１〜６−
３……基準発振器、１０……ＩＯポート、１１−
１〜１１−３……３ステートバツフア、１２……
クロツクセレクタ、１３……データラツチ回路、
１４……分周回路、１５−１〜１５−３……Ｄフ
リツプフロツプ。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a timing chart explaining the operation of each part in Fig. 1, Fig. 3 is a diagram showing an example of a control circuit of a laser printer, and Fig. 4 is a diagram showing an example of a control circuit of a laser printer. FIG. 2 is a circuit example diagram of a conventional pixel density determination device. 1... Microcomputer (CPU), 2...
...Image writing control circuit (LSI), 6-1 to 6-
3...Reference oscillator, 10...IO port, 11-
1~11-3...3 state buffer, 12...
Clock selector, 13...data latch circuit,
14... Frequency dividing circuit, 15-1 to 15-3... D flip-flop.
Claims (1)
する複数の基準発振器を備えた画像形成装置にお
いて、該複数の基準発振器の出力を夫々入力する
クロツクセレクタ及び該基準発振器と同数個のＤ
フリツプフロツプと、該Ｄフリツプフロツプの出
力を夫々入力とし、ＣＰＵからのデータ読出し信
号によりＯＮ／ＯＦＦ動作する３ステートバツフ
アと、該３ステートバツフアを介して得られる前
記Ｄフリツプフロツプの出力をＣＰＵへ伝達する
ＩＯポートとからなることを特徴とする画像形成
装置の画素密度判定装置。 In an image forming apparatus equipped with a plurality of reference oscillators that generate reference clocks according to the pixel density used, a clock selector that inputs the outputs of the plurality of reference oscillators, respectively, and a clock selector having the same number of Ds as the reference oscillators, are provided.
A flip-flop and a 3-state buffer which receives the outputs of the D flip-flop as inputs and which are turned ON/OFF by a data read signal from the CPU, and transmits the output of the D flip-flop obtained through the 3-state buffer to the CPU. 1. A pixel density determination device for an image forming apparatus, comprising: an IO port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4453390U JPH045942U (en) | 1990-04-27 | 1990-04-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4453390U JPH045942U (en) | 1990-04-27 | 1990-04-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH045942U true JPH045942U (en) | 1992-01-20 |
Family
ID=31557925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4453390U Pending JPH045942U (en) | 1990-04-27 | 1990-04-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH045942U (en) |
-
1990
- 1990-04-27 JP JP4453390U patent/JPH045942U/ja active Pending
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