JPH05113833A - Clock generating circuit for slave - Google Patents

Abstract

PURPOSE:To improve the performance of a computer system by enabling a clock generating circuit to generate the best clock for the states of slaves. CONSTITUTION:The clock generating circuit 11 inputs an external high-speed fundamental clock CL and state monitor signals S1, S2-Sn from slaves 13 and 14 and generates various clocks CLK. The slaves request the clock generating circuit to generate the best clock with the state monitor signals. The clock generating circuit generates the best clock according to which state monitor signal becomes active.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator circuit.

[0002]

2. Description of the Related Art In a conventional clock generation circuit, since the frequency and duty of the clock are constant during the cycle execution of the CPU or the bus master, it is necessary to design the slave to be optimum for the clock.

[0003]

The above-described clock generation circuit has a drawback that the system performance is degraded if the slave cannot be optimally designed with respect to the clock because the clock is constant during execution of cycles by the CPU or bus master. In addition, when the clock standard is changed, there is also a drawback that the slaves according to the standard before the change may not be usable.

It is an object of the present invention to provide a clock generation circuit which does not have the above drawbacks.

[0005]

A clock generation circuit according to the present invention receives a status monitoring signal from a slave and generates an optimum clock corresponding to the status monitoring signal.

Further, it is preferable that the optimum clock has its frequency lowered or raised according to the slow operation of the slave, and has its duty ratio lowered or raised according to the slow operation of the slave.

[0007]

The clock generation circuit inputs the state monitoring signal sent from the slave, monitors the state of the slave, and generates a clock optimum for the state of the slave.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a block diagram showing a first embodiment of a clock generation circuit of the present invention. Clock generation circuit 1
Receives the basic clock CL from the basic clock generation circuit 2 and receives the state monitoring signals S ₁ , S ₂ , ..., from the slave 3.
_Sn (hereinafter referred to as signals S ₁ , S ₂ , ..., S _n ) is input, and the state of the slave 3 is determined based on which signal S ₁ , S ₂ , ..., S _n is active. Generates the optimum clock CLK for

FIG. 2 is a block diagram showing a second embodiment of the present invention, and FIG. 3 is a time chart for explaining the operation of the embodiment of FIG. 2 in comparison with the operation of the conventional example. In this embodiment, the slave comprises a memory 14 and a memory controller 13 that controls the memory 14. Clock generation circuit 1
1 is the basic clock CL from the basic clock generation circuit 12
, The signals S ₁ , S ₂ ,
~, Type S _n, the signal S _1, S _2, ~, and a clock CLK memory controller 13 to fit S _n C
Output to PU15. The memory controller 13 inputs the address status AS from the CPU 15 based on the preset memory map, detects the function of the memory 14 allocated on the memory map, and adapts to the function of the memory 14. The signals S ₁ , S ₂ , ..., S _n are output. Further, the memory controller 13 inputs the clock CL corresponding to the output signals S ₁ , S ₂ , ..., S _n.
Based on K, the memory chip select signal SEL (hereinafter,
A select signal SEL) is output to cause the CPU 15 to read or write the data DD with respect to the memory 14.

Next, the operation of this embodiment will be described with reference to FIG.
Explain. In FIGS. 3 and 4, T_S Is the start
State, T_c Is the command state, T_CWIs Commando
Eight state, start state T_S Currently
Of the command state T_C 
Indicates the execution cycle, and the command wait state T _CW
Is the command state T_C If the cycle does not end with
It shows the extended state.

First, in the first operation example, the memory 14 is high.
The fast case will be described with reference to FIG. Conventional black
Clock CLK₀ Is the time t₁ , T₃ , T₇ Rises to the time
t₂, T₆ A pulse with a constant frequency falling
It Therefore, the data DD₀Setup time SU₀
 Is time t_Four , T₇ And the execution time EX₀ 
Is the time t₁ , T₇ Will be in between. On the other hand, in the case of this embodiment,
The clock CLK is at time t ₂ Address stay entered in
From TAS AS, the memory 14 is
It is detected that it is a high-speed one, and time t₃ More clock
Increase the frequency of CLK. Therefore the signal S₁ At time t
₃ And sample the select signal SEL at time t₃ , T₆ 
Set data DD by activating between
Up time SU is time t_Four , T₆ Only during the period. this child
And the execution time EX is the time t₁ , T₆ Time between
Tick t₆ , T₇The shortened time between TT and the execution time are accelerated
There is. Contrary to the case of this embodiment, when the memory 14 is low speed
If you don't have enough setup time,
Command wait state is used by supplying
It is feasible without it.

A third embodiment of the present invention will be described with reference to FIG. The operation of the memory 14 of the present embodiment is different from that of the memory of the second embodiment, and the duty ratio of the clock CLK needs to be adjusted. That is, the select signal SEL falls in synchronization with the fall of the command state T _C. The conventional clock CLK ₀ is output with a constant duty ratio, and since there is not enough time for setting up the data DD ₀ between times t ₅ and t ₇ ,
The command wait state T _CW is inserted and the select signal SEL ₀ is made active during the times t ₅ and t ₉ . Therefore, the execution time EX ₀ is between the times t ₁ and t ₉ . On the other hand, in this embodiment, the duty of the command state T _C is changed between the times t ₃ and t ₅ and the times t ₃ and t ₄ . Therefore, the time until the start of setup at time t ₆ is sufficient, and the execution time EX of the cycle is shortened by the shortening time TT, which is between times t ₁ and t ₇ . Further, by using both the clock frequency and the clock duty optimized for the slave, more efficient slave operation can be expected.

[0013]

As described above, the present invention can generate a clock that is optimum for the slave state of the execution cycle of the CPU or the bus master, so that the dead time of the cycle can be eliminated and the system performance can be improved. .. In addition, since the slave can receive the clock that is most suitable for itself, the slave can be easily designed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a clock generation circuit of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment of FIG.

FIG. 4 is a time chart showing the operation of the third embodiment of the present invention.

[Explanation of symbols]

 1, 11 Clock generation circuit 2, 12 Basic clock generation circuit 3 Slave 13 Memory controller 14 Memory 15 CPU

Claims (3)

[Claims] 1. A status monitoring signal from a slave is input,
A clock generation circuit that generates the optimum clock corresponding to the status monitoring signal. 2. The clock generation circuit according to claim 1, wherein the optimum clock has a frequency which is lowered or raised according to the slow speed of the slave operation. 3. The clock generation circuit according to claim 1, wherein the optimum clock has a duty ratio that is lowered or raised according to a slow speed of a slave operation.