JPH0650474B2 - Microcomputer development support device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a microcomputer development support device used for developing a microprocessor of a user system and acting as a substitute for the operation of the microprocessor of the user system. The present invention relates to a microcomputer development support device used by being connected to a socket for a microprocessor via a connector, a cable, a bus buffer and the like.

[Prior Art] Conventionally, a microcomputer development support device has been known as a tool for developing a microprocessor of a user system. The conventional configuration of this device is shown in FIG.

Inside the support device pod unit 1, a CPU 2 for development support is provided.
And a bus buffer 3 for relaying between the CPU 2 and the user system 9, which are connected via a data bus 4, an input control bus 5, an address bus 6 and an output control bus 7. The support device pod unit 1 and the CPU socket 10 of the user system 9 are connected via a cable 8 and a connector (not shown). At the time of connection, the bus buffer 3 and the user system 9
The data bus 11, the input control bus 12, the address bus 13 and the output control bus 14 are connected to the CPU socket 10 of FIG.

In the above configuration, the system clock and the memory are those of the user system 9, and the CPU is C of the support device.
When using the PU 2, the system clock from the user system 9 is input to the CPU 2 via the CPU socket 10, the input control bus 12, the bus buffer 3 and the input control bus 5. The CPU 2 outputs an address signal and an output control signal in synchronization with the input system clock. The address signal and the output control signal are the address bus 6 and the output control bus 7, the bus buffer 3, the address bus 13 and the output control bus 14, and the CPU socket 10.
Is provided to a memory arranged on the user system side (not shown).

[Problems to be Solved by the Invention] By the way, normally, the system clock and the C
A delay time td ₀ ′ exists between the address signal or the output control signal output from the PU.

For example, as shown in FIG. 7, one bus cycle ends with two clocks T ₁ and T ₂ , and the clock frequency is about 15M.
In the case of Hz (1 clock 67 ns), the above td _o ′ is about 40 ns. The user system 9 sets various control timings in consideration of the delay time td ₀ ′.

However, when using the support device described above,
By the time the system clock generated in the user system 9 is input to the CPU 2 of the support device, the CPU socket 1
0, the input control bus 12, the bus buffer 3 and the input control bus 5, the delay time td ₁ ′ is generated as shown in FIG. Further, the address bus 6 (or the output control bus 7), the bus buffer, and the address bus 13 are provided until the address signal (or the output control signal) output from the CPU 2 in synchronization with the system clock is given to the memory on the user system 9 side.
Since it goes through (or the output control bus 14) and the CPU socket 10, a delay time td ₂ ′ is generated as shown in FIG. 7. These td ₁ ′ and td ₂ ′
Are about 20 ns, respectively. Therefore, when the assisting device is used, the delay time td _o ′ (40 n
s) and these delay times td ₁ ′ + td ₂ ′ are added 8
0 ns becomes a delay time from the system clock output to the address input.

As described above, in the conventional microcomputer development support device, there is a delay from the generation of the system clock to the input of the address signal and the control signal depending on whether the support device is mounted in the CPU socket of the user system or the CPU is directly mounted. The time is different by td ₁ ′ + td ₂ ′, which is a major obstacle in CPU development.

The present invention has been made in view of such problems,
An object of the present invention is to provide a microcomputer development supporting device capable of obtaining substantially the same timing when a normal CPU is inserted into a CPU socket of a user system and when a microcomputer development supporting device is connected.

[Means for Solving Problems] In the microcomputer development support device according to the present invention, the I / O unit for introducing at least the system clock from the user system and the decision timing of the address signal and the output control signal with respect to the system clock are normally set. A microprocessor for an assisting device earlier than the timing of the processor, a sampling signal generating circuit for generating a sampling signal of an address signal and an output control signal based on the input / output control signal of the processor, and the address based on the sampling signal. And a holding circuit which holds a signal and an output control signal.

[Operation] In the present invention, since the microprocessor for the support device outputs the address signal and the output control signal at a timing earlier than the normal processor with respect to the system clock, the time is longer than that when the normal processor is used. Therefore, it is possible to absorb the signal delay in the I / O unit such as the bus buffer, the cable and the socket described above within this time. The output timing of the address signal and the output control signal with respect to the user system can be arbitrarily determined by appropriately adjusting the sampling signal generation timing of the sampling signal generation circuit and adjusting the holding timing of the address signal and the like in the holding circuit. it can. Therefore, according to the present invention, it is possible to obtain substantially the same access timing when the normal CPU is inserted in the CPU socket of the user system and when the support device is connected.

Embodiments Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a microcomputer development support apparatus according to the first embodiment of the present invention, and FIG. 2 is a timing chart thereof.

Inside the support device pod unit 21, the support device CPU 2 is provided.
2, bus buffer 23, FF (flip-flop) 24
And an FF control signal generator 25.

The support device CPU 22 and the bus buffer 23 are connected via a data bus 26 and an input control bus 27. The support device CPU 22 and the FF 24 are connected via an address bus 28 and an output control bus 29, and the FF 24 and the bus buffer 23 are connected via an address bus 30 and an output control bus 31. Further, the signals on the input control bus 27 and the output control bus 29 are also given to the FF control signal generator 25,
The FF control signal line 32 from is connected to the FF 24. The support device pod 21 and the CPU socket 10 of the user system 9 are connected via a cable 8 and a connector (not shown). At the time of connection, the bus buffer 3 and the CPU socket 10 of the user system 9 are connected by the data bus 11, the input control bus 12, the address bus 13 and the output control bus 14.

The support device CPU 22 has a feature that the address signal and the output control signal with respect to the system clock are determined more quickly than a normal CPU. That is,
As shown in FIG. 2, the output signal of the normal CPU changes the output signal when td _o time elapses from the rise of the system clock.
U22 changes the output signal when td _o time elapses from the fall of the system clock which is earlier by half a cycle. As shown in FIG. 2, the CPU 22 for the support device has two bus cycles of T ₁ and T ₂ for one bus cycle.
Ends with a clock, in particular outputs T ₁ rising enable signal indicating the rise of T _1.

The bus buffer 23 relays the support device CPU 22 and the user system 9, and constitutes the I / O unit of the support device together with the cable 8 and a connector (not shown).

The FF 24 constitutes a holding circuit that holds the address signal and the output control signal output from the support device CPU 22 at an early timing based on the FF control signal.

The FF control signal generator 25 receives the FF from the system clock input to the CPU 22 via the input control bus 27 and the T ₁ rising enable signal output from the CPU 22 via the output control bus 29.
It has a function of generating a control signal (sampling signal) and outputting this signal to the FF 24 via the FF control signal line 32.

Next, the operation of the microcomputer development support device according to the present embodiment configured as described above will be described. Now, when the system clock and the memory are those of the user system 9 and the CPU is the CPU 22 for the supporting device, first, the system clock generated from the user system 9 is the CPU socket 10 and the connector (not shown). ), Input control bus 12, bus buffer 2
3. Support device CP via input control bus 27
Input to U22. The cable 8 and the bus buffer 23 cause a delay in the user system clock from the CPU socket 10 to the support device CPU 22. This delay corresponds to td ₁ in FIG. That is, the CPU input system clock input to the support device CPU 22 is delayed by td _{1 with} respect to the user system clock.

The CPU 22 for assisting device outputs an address signal and an output control signal that are fixed earlier than the normal CPU by a half clock (t ₀ ) of the system clock in synchronization with the CPU input system clock. The address signal and the output control signal are input to the FF 24 via the address bus 28 and the output control bus 29, respectively.

The address signal and the output control signal input to the FF 24 are held (fixed) in the FF 24 in synchronization with the rising of T ₁ . The address signal and the output control signal are held at the rising edge of T _{1 because} the address signal and the like change in synchronization with the rising edge of T ₁ .
Needless to say, if it is determined at another timing, it may be fixed at that timing.

The FF control signal generator 25 gives the timing of holding the address signal and the like in the FF 24. FIG. 3 is a circuit diagram showing a specific example of this sampling. The FF control signal generator 25 is composed of a D-type flip-flop, and outputs a T ₁ rising enable signal (see FIG. 2) to D
The enable signal is input to the terminal and held at the rising edge of the CPU input system clock input to the clock terminal. As a result, the FF control signal shown in FIG. 2 is output to the Q output of the FF control signal generator 25.

The FF 24 also comprises a D-type flip-flop, inputs the address signal and the output control signal to the D terminal, and holds these signals at the falling edge of the FF control signal. As a result, the Q output of FF24 is
The held address signal and output control signal are output.

The address signal and the output control signal are delayed by td ₂ (FIG. 2) in the bus buffer 23, and the CPU
Delay in the cable 8 while reaching the power socket 10
_{With 3} . Now, set the system clock frequency to 15 MH
z (1 clock 67 ns), the delay td _{o of the} CPU 22 itself with respect to the rise of T ₁ of the clock is 40 n.
s, CPU rises from the rise of the user system clock
The time until the address signal and the output control signal arrive at the socket 10 is td ₁ (20 ns) + td
₂ (10 ns) + td ₃ (20 ns) = 50 ns. Therefore, the output signal obtained from the assisting device with respect to the signal normally output by the CPU is td ₁ + td ₂ + td ₃ −.
The delay is about td _o = 10 ns.

As described above, conventionally, a delay of about 40 ns has occurred under the same condition, but in the present embodiment, it can be reduced to a delay of about 10 ns, and a microcomputer development support device can be obtained with less timing deviation.

Needless to say, the above delay time can be further reduced by further advancing the generation timing of the FF control signal.

FIG. 4 shows the configuration of the second embodiment of the present invention, and FIG. 5 shows its timing chart. Incidentally, in FIG. 4, the same components as those in FIG. 1 are designated by the same reference numerals.

In this embodiment, the support device memory 4 is provided inside the support device.
When the system clock is supplied from the user system, the memory uses the support device memory 41 inside the support device. The support device memory 41 is connected to the bus buffer 23 by a data bus 42 and an output control bus 43. Further, since the logical address output from the bus buffer 23 is converted into the physical address of the support device memory 41, the bus buffer 23
The logical address bus 44 from the address conversion unit 45 is guided to the address conversion unit 45, and the converted address from the address conversion unit 45 is transferred via the physical address bus 46 to the support device memory 4
It is given to 1.

Also, a CPU socket 1 of a user system (not shown)
An input control signal such as a user system clock output via 0 is input into the assisting device via a cable and a bus buffer 47 (not shown) and is given to the assisting device CPU 22 via the input control bus 27.

In the microcomputer development support apparatus according to the present embodiment configured as described above, since the memory to be used in the user system is provided inside the support apparatus, the logical address output from the support apparatus CPU 22 is supported. Address conversion is required to allocate to the physical area in which the device memory 41 exists. That is, the CPU for the support device
The address signal output by 22 is input to the FF 24 and T
It is fixed in synchronization with the rise of ₁ . In the FF control signal generator 25, an FF control signal that falls in synchronization with the rise of T ₁ is generated, and the FF 24 sends this FF control signal to the FF control signal line 32.
Received through and fix the address. The address fixed by the FF24 reaches the bus buffer 23 from the FF24 through the address bus 30, and the T
It is output with a delay td ₂ (about 10 ns) relative to the rise of ₁ and reaches the address conversion unit 45 (see FIG. 5).

The address conversion unit 45 converts the logical address output from the assisting device CPU 22 into a physical address in advance according to a pattern of stored data. The physical address is given to the support device memory 41 through the physical address bus 46. In this address conversion unit 45, t
A delay of d _m (about 60 ns) occurs (see FIG. 5). When reading data from the memory 41, the assisting device memory 41 outputs the data after the time td _a (delay depending on the type of memory) has elapsed since the physical address was fixed. The output data reaches the bus buffer 23 via the data bus 42, and reaches the support device CPU 22 via the data bus 26. The delay in the bus buffer 23 of the data from the assisting device memory 41 to the assisting device CPU 22 is indicated by td _b (about 20 ns) in FIG.

These are delays after the address conversion unit 45 td _m + td _a
Since + td _b is equivalent in circuit to the conventional support device, it is the same as the conventional one. However, with this support device, a normal C
Since the address input to the address conversion unit 45 is earlier than the conventional support device using the PU by td _o −td ₂ = (about 20 ns) based on the rise of T ₁ ,
The timing of the data sampled by the CPU is also td _o -t
It becomes faster by d ₂ (Fig. 5).

Normally, in the CPU, it is necessary to complete the reading of the memory within the time of one bus cycle. Therefore, conventionally, only the memory having a fast access time (td _{a in} FIG. 5) can be used. In particular, in recent years, the system clock has become faster,
Although it is required to design a microprocessor support device with a small number of clocks per bus cycle,
Due to the access time (td _a ), there is a problem that the existing memory cannot be used and the design of the support device becomes difficult. However, according to the support apparatus of the present embodiment, the output signal of the CPU such as the address is determined half a clock earlier than the system clock and the signal is fixed at the rising edge of T _1. Therefore, the normal CPU is used. It is possible to select a memory whose access time is slower by about 20 ns than that of the supporting device. This facilitates the design of the support device.

[Effects of the Invention] As described above, according to the present invention, assistance is provided in which the address signal and output control signal of a microprocessor acting on behalf of the microprocessor of a user system are fixed earlier than the timing of a normal microprocessor. Since the device microprocessor is used and the address signal and output control signal from the support device microprocessor are fixed at arbitrary timing by the holding circuit, the signal output from the microprocessor is a normal microprocessor. Confirms faster than when using. Therefore, the delay in the bus buffer and the cable can be absorbed within this time difference, and when the normal CPU is inserted into the CPU socket of the user system and the support device is used for the output signal of the microprocessor. The timing deviation can be reduced.

In addition, in the assisting device of the present invention, a high-speed clock and a low clock count per bus cycle, which would be difficult for an assisting device using a normal CPU, are used.
Even for the PU, there is a margin in timing of various signals, and it is possible to design a support device for a high-performance CPU without changing the method of the existing support device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram thereof, and FIG. 3 is a circuit diagram showing a concrete example of signal fixing in the embodiment. FIG. 4 is a block diagram showing another embodiment of the present invention, FIG. 5 is a timing diagram thereof, FIG. 6 is a block diagram showing a conventional microcomputer development support device, and FIG. 7 is a timing diagram thereof. is there. 1, 21; support device pod unit, 2; CPU, 3, 2
3, 47; bus buffer, 4, 11, 26, 42; data bus, 5, 12, 27; input control bus, 6,
13, 28, 30; address bus, 7, 14, 29, 3
1, 43; output control bus, 8; cable, 9;
User system, 10; CPU socket, 22; Support device CPU, 24; FF (flip-flop), 2
5; FF control signal generation unit, 41; support device memory, 44; logical address bus, 45; address conversion unit, 46; physical address bus

Claims (2)

[Claims] 1. A microcomputer development support device connected to a microprocessor socket of a user system to substitute for the operation of the microprocessor of the user system, comprising an I / O unit for introducing at least a system clock from the user system. Based on the microprocessor for the assisting device and the input / output control signal of the microprocessor for the assisting device, the time to finalize the address signal and the output control signal for the system clock is faster than the microprocessor to be used in the user system. A sampling signal generating circuit for generating a sampling signal of an address signal and an output control signal output from the microprocessor for the supporting device;
And a holding circuit for holding an address signal and an output control signal output from the microprocessor for assisting device based on the sampling signal from the sampling signal generating circuit. 2. The I / O unit is a connector connected to a bus buffer provided between the microprocessor for the supporting device and the holding circuit and the user system, and a socket for the microprocessor of the user system. And a cable for connecting the connector and the bus buffer, and the microcomputer development support device according to claim 1.