JPH0179147U - - Google Patents
Info
- Publication number
- JPH0179147U JPH0179147U JP1987175352U JP17535287U JPH0179147U JP H0179147 U JPH0179147 U JP H0179147U JP 1987175352 U JP1987175352 U JP 1987175352U JP 17535287 U JP17535287 U JP 17535287U JP H0179147 U JPH0179147 U JP H0179147U
- Authority
- JP
- Japan
- Prior art keywords
- section
- serial transfer
- cpu
- status
- status display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012806 monitoring device Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は、この考案によるシリアル転送動作監
視装置の一実施例の全体構成図、第２図はこの考
案のステータス表示制御部の詳細な構成図、第３
図はこの考案によるステータス表示制御部の動作
タイムチヤート、第４図は従来のシリアル転送の
構成図である。
図において１はＣＰＵ部、２はシリアル転送部
、３はステータス表示部、４はコントロール信号
、５はアドレス信号、６はデータ信号、７はシリ
アルデータ信号、８はステータス表示制御部、９
はＣＰＵホールド信号、１０はラツチされたステ
ータス信号、１１は発振回路、１２は分周比設定
用スイツチ回路、１３は分周回路、１４Ａ〜１４
Ｅは単安定マルチバイブレータ、１５Ａ〜１５Ｄ
は遅延回路、１６はシリアル転送部のステータス
レジスタのアドレス設定用スイツチ回路、１７は
インバータ回路、１８Ａ〜１８Ｃは３ステート・
バツフア回路、１９はＤ型フリツプフロツプ回路
、２０はシリアル転送部のステータス・レジスタ
読み出し制御信号、２１はシリアル転送部のステ
ータスのアドレス出力制御信号、２２はステータ
ス読み込み制御信号、２３はステータス・ラツチ
信号、２４は論理素子の電源電圧である。なお、
図中同一あるいは相当部分には同一符号を付して
ある。
FIG. 1 is an overall configuration diagram of an embodiment of a serial transfer operation monitoring device according to this invention, FIG. 2 is a detailed configuration diagram of a status display control section of this invention, and FIG.
The figure is an operation time chart of the status display control section according to this invention, and FIG. 4 is a block diagram of conventional serial transfer. In the figure, 1 is a CPU section, 2 is a serial transfer section, 3 is a status display section, 4 is a control signal, 5 is an address signal, 6 is a data signal, 7 is a serial data signal, 8 is a status display control section, 9
is a CPU hold signal, 10 is a latched status signal, 11 is an oscillation circuit, 12 is a frequency division ratio setting switch circuit, 13 is a frequency division circuit, 14A to 14
E is monostable multivibrator, 15A to 15D
is a delay circuit, 16 is a switch circuit for setting the address of the status register of the serial transfer section, 17 is an inverter circuit, and 18A to 18C are 3-state circuits.
A buffer circuit, 19 a D-type flip-flop circuit, 20 a status register read control signal for the serial transfer section, 21 a status address output control signal for the serial transfer section, 22 a status read control signal, 23 a status latch signal, 24 is the power supply voltage of the logic element. In addition,
Identical or corresponding parts in the figures are designated by the same reference numerals.
Claims (1)
ｇ Ｕｎｉｔ）部と、ＣＰＵ部の制御に基づきシ
リアル転送を行なうシリアル転送部と、シリアル
転送部のステータスをＣＰＵ部の動作と独立に読
み出すステータス表示制御部と、ステータス表示
制御部の出力及びＣＰＵ部の出力を表示するステ
ータス表示部をシリアル転送の送信側と受信側に
それぞれ備えていることを特徴とするシリアル転
送監視装置。 CPU (Central Processing)
g Unit) section, a serial transfer section that performs serial transfer based on the control of the CPU section, a status display control section that reads the status of the serial transfer section independently of the operation of the CPU section, and an output of the status display control section and the CPU section. 1. A serial transfer monitoring device characterized in that a status display section for displaying the output of the serial transfer is provided on a transmitting side and a receiving side of the serial transfer, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987175352U JPH0179147U (en) | 1987-11-17 | 1987-11-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987175352U JPH0179147U (en) | 1987-11-17 | 1987-11-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0179147U true JPH0179147U (en) | 1989-05-26 |
Family
ID=31467146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987175352U Pending JPH0179147U (en) | 1987-11-17 | 1987-11-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0179147U (en) |
-
1987
- 1987-11-17 JP JP1987175352U patent/JPH0179147U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0179147U (en) | ||
| JPS6128070U (en) | digital frequency phase comparator | |
| JPH01102944U (en) | ||
| JPS6051486U (en) | electronic clock | |
| JPS6035649U (en) | Operation mode recognition device | |
| JPS6044320U (en) | Chattering removal circuit | |
| JPH01135559U (en) | ||
| JPS5984697U (en) | Arithmetic circuit | |
| JPS605590U (en) | Rear window differential circuit | |
| JPS6273274U (en) | ||
| JPS62187874U (en) | ||
| JPS6030004U (en) | Bus line selection connection structure in combination unit | |
| JPS61133833U (en) | ||
| JPS59144960U (en) | button telephone device | |
| JPS60158310U (en) | Temperature compensated crystal oscillator circuit | |
| JPS62117641U (en) | ||
| JPS58103394U (en) | Electronic clock with alarm | |
| JPH01135558U (en) | ||
| JPS6055125U (en) | Inverted signal generation circuit | |
| JPS63131228U (en) | ||
| JPH01135560U (en) | ||
| JPS6020605U (en) | Bus line selection connection structure in combination unit | |
| JPS6397103U (en) | ||
| JPS62138253U (en) | ||
| JPS6059686U (en) | signal monitoring circuit |