JPS63182130U - - Google Patents
Info
- Publication number
- JPS63182130U JPS63182130U JP7424687U JP7424687U JPS63182130U JP S63182130 U JPS63182130 U JP S63182130U JP 7424687 U JP7424687 U JP 7424687U JP 7424687 U JP7424687 U JP 7424687U JP S63182130 U JPS63182130 U JP S63182130U
- Authority
- JP
- Japan
- Prior art keywords
- print information
- receiving buffer
- stored
- timer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Laser Beam Printer (AREA)
- Dot-Matrix Printers And Others (AREA)
Description
第１図は本実施例に用いるページプリンタの回
路ブロツク図、第２図ａ，ｂは本実施例のページ
プリンタ制御装置の動作フローチヤートである。
１……ページプリンタ、２……インターフエイ
ス制御部、３……プリント部、５……ＣＰＵ、６
……ページメモリ、１０……ＲＡＭ、１０ａ……
受信バツフア、１０ｂ……レジスタ、１０ｃ……
タイマーカウンタ、１１……基準クロツク発生器
、１２……分周器、１３……印字部、１５……ホ
ストコンピユータ。
FIG. 1 is a circuit block diagram of a page printer used in this embodiment, and FIGS. 2a and 2b are operational flowcharts of the page printer control device of this embodiment. 1...Page printer, 2...Interface control section, 3...Print section, 5...CPU, 6
...Page memory, 10...RAM, 10a...
Reception buffer, 10b...Register, 10c...
Timer counter, 11... Reference clock generator, 12... Frequency divider, 13... Printing section, 15... Host computer.
Claims (1)
受信バツフアと、該受信バツフア内に前記印字情
報が記憶されているか否かを検出する検出回路と
、前記受信バツフアに記憶された印字情報の中の
印字データを所定量記憶するページメモリと前記
検出回路が前記印字情報を検出した時点で初期設
定され、前記受信バツフアに印字情報が入力しな
い間計時を行なうタイマー回路と、該タイマー回
路が所定時間の計時を終了すると前記ページメモ
リに記憶された印字データを印字出力する印字出
力回路とを有することを特徴とするページプリン
タ制御装置。 A receiving buffer that receives and stores print information input from an external device, a detection circuit that detects whether or not the print information is stored in the receiving buffer, and printing in the print information stored in the receiving buffer. a page memory that stores a predetermined amount of data; a timer circuit that is initialized when the detection circuit detects the print information; and a timer circuit that measures time while no print information is input to the reception buffer; and a timer circuit that measures a predetermined time. and a print output circuit that prints out the print data stored in the page memory upon completion of the page printer control apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7424687U JPS63182130U (en) | 1987-05-18 | 1987-05-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7424687U JPS63182130U (en) | 1987-05-18 | 1987-05-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63182130U true JPS63182130U (en) | 1988-11-24 |
Family
ID=30919283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7424687U Pending JPS63182130U (en) | 1987-05-18 | 1987-05-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63182130U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01131533U (en) * | 1988-03-03 | 1989-09-06 | ||
| JPH02235135A (en) * | 1989-03-09 | 1990-09-18 | Brother Ind Ltd | Printing control device |
-
1987
- 1987-05-18 JP JP7424687U patent/JPS63182130U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01131533U (en) * | 1988-03-03 | 1989-09-06 | ||
| JPH02235135A (en) * | 1989-03-09 | 1990-09-18 | Brother Ind Ltd | Printing control device |