JPH0458551A - Multichip module - Google Patents

Multichip module

Info

Publication number
JPH0458551A
JPH0458551A JP17096590A JP17096590A JPH0458551A JP H0458551 A JPH0458551 A JP H0458551A JP 17096590 A JP17096590 A JP 17096590A JP 17096590 A JP17096590 A JP 17096590A JP H0458551 A JPH0458551 A JP H0458551A
Authority
JP
Japan
Prior art keywords
via
heat
lsi chip
heat sink
attached
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17096590A
Inventor
Toshiyuki Ota
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP17096590A priority Critical patent/JPH0458551A/en
Publication of JPH0458551A publication Critical patent/JPH0458551A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors

Abstract

PURPOSE: To reduce a heat resistance by a method wherein the face on which an LSI chip element is formed is sealed by using a resin and a heat sink is attached, via a metal sheet or directly, to a face opposite to the face on which the element is formed.
CONSTITUTION: The part between an LSI chip 101 and a mounting circuit board 103 is sealed by using a resin layer 105 by a potting operation or the like. A copper tungsten sheet 107 is attached to the mounting circuit board 103 via a silicone resin layer 106. On the other hand, a metal sheet 109 composed of copper or the like is connected to the rear of the LSI chip 101 via a silver paste layer 108. A heat sink 111 is attached to a heat sink 109 via a resin layer 110, for heat-sink bonding use, which uses a silicone or the like. Heat generated at the LSI chip 101 is released from the heat sink 111. Thereby, a heat resistance can sharply be reduced.
COPYRIGHT: (C)1992,JPO&Japio
JP17096590A 1990-06-28 1990-06-28 Multichip module Pending JPH0458551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17096590A JPH0458551A (en) 1990-06-28 1990-06-28 Multichip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17096590A JPH0458551A (en) 1990-06-28 1990-06-28 Multichip module

Publications (1)

Publication Number Publication Date
JPH0458551A true JPH0458551A (en) 1992-02-25

Family

ID=15914654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17096590A Pending JPH0458551A (en) 1990-06-28 1990-06-28 Multichip module

Country Status (1)

Country Link
JP (1) JPH0458551A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604978A (en) * 1994-12-05 1997-02-25 International Business Machines Corporation Method for cooling of chips using a plurality of materials
US5757073A (en) * 1996-12-13 1998-05-26 International Business Machines Corporation Heatsink and package structure for wirebond chip rework and replacement
US6313521B1 (en) 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
US6720650B2 (en) * 2000-07-13 2004-04-13 Nec Electronics Corporation Semiconductor device having heat spreader attached thereto and method of manufacturing the same
EP1198005A4 (en) * 1999-03-26 2004-11-24 Hitachi Ltd Semiconductor module and method of mounting
US6940162B2 (en) 1999-03-26 2005-09-06 Renesas Technology Corp. Semiconductor module and mounting method for same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604978A (en) * 1994-12-05 1997-02-25 International Business Machines Corporation Method for cooling of chips using a plurality of materials
US5724729A (en) * 1994-12-05 1998-03-10 International Business Machines Corporation Method and apparatus for cooling of chips using a plurality of customized thermally conductive materials
US5757073A (en) * 1996-12-13 1998-05-26 International Business Machines Corporation Heatsink and package structure for wirebond chip rework and replacement
US6134776A (en) * 1996-12-13 2000-10-24 International Business Machines Corporation Heatsink and package structure for wirebond chip rework and replacement
US6313521B1 (en) 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
EP1198005A4 (en) * 1999-03-26 2004-11-24 Hitachi Ltd Semiconductor module and method of mounting
US6940162B2 (en) 1999-03-26 2005-09-06 Renesas Technology Corp. Semiconductor module and mounting method for same
US6720650B2 (en) * 2000-07-13 2004-04-13 Nec Electronics Corporation Semiconductor device having heat spreader attached thereto and method of manufacturing the same

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