JPH0458551A - Multichip module - Google Patents
Multichip moduleInfo
- Publication number
- JPH0458551A JPH0458551A JP17096590A JP17096590A JPH0458551A JP H0458551 A JPH0458551 A JP H0458551A JP 17096590 A JP17096590 A JP 17096590A JP 17096590 A JP17096590 A JP 17096590A JP H0458551 A JPH0458551 A JP H0458551A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- heat sink
- lsi chip
- circuit board
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 239000011347 resin Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052802 copper Inorganic materials 0.000 abstract description 6
- 239000010949 copper Substances 0.000 abstract description 6
- 229920001296 polysiloxane Polymers 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 4
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052709 silver Inorganic materials 0.000 abstract description 4
- 239000004332 silver Substances 0.000 abstract description 4
- 229920002050 silicone resin Polymers 0.000 abstract description 3
- 238000004382 potting Methods 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000005028 tinplate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はマルチチップモジュールに関し、特に実装基板
に複数のＬＳＩチップをフリップチップ接続してなるマ
ルチチップモジュールに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-chip module, and more particularly to a multi-chip module in which a plurality of LSI chips are flip-chip connected to a mounting board.
ＬＳＩの多ピン化に伴いＬＳＩパッケージは大型化して
いる。また装置は小型化、高性能化の傾向が強くなって
いる。従って従来のパッケージを使用したモジュールで
は
（１）モジュールが大型化する。As LSIs have more pins, LSI packages are becoming larger. Additionally, there is a strong trend toward smaller devices and higher performance. Therefore, in a module using a conventional package, (1) the module becomes large;
（２）チップとチップの間の距離が大きくなり、チップ
間の信号遅延時間が大きくなり、高速性を要求される装
置には適合しなくなる。(2) The distance between chips increases, and the signal delay time between chips increases, making it unsuitable for devices requiring high speed.
等の問題があった。There were other problems.
これらの問題を解決する方法としてマルチチップモジュ
ールを用いる方法が多く用いられるようになっている。As a method to solve these problems, a method using a multi-chip module is increasingly used.
マルチチップモジュールとして各種のものが提案されて
おり、ワイヤボンディングを用いるもの、ＴＡＢを用い
るもの、フリップチップを用いるもの等がある。Various types of multi-chip modules have been proposed, including those using wire bonding, those using TAB, and those using flip chips.
これらの中で、面実装が可能で、かつリードのインダク
タンスの最も小さいフリップチップ接続を用いたマルチ
チップモジュールは性能面では最も期待される実装技術
の一つである。プリラグチップを用いたマルチチップモ
ジュールの従来技術として例えば、Ｃ，Ｔ、 Ｂａｒ口
ｅｔｔ ｅｔ、ａｌ、 ”Ｈｕｌｔｉ−Ｃｈｉｐ Ｐ
ａｃｋａｇｉｎｇ Ｄｅｓｉｇｎ ｆｏｒ ＶＬＳＩ−
Ｂａｓｅｄ ５ｙｓｔｅｎ”ＩＥＥＥ Ｐｒｏｃ、 ｏ
ｆ ３７ｔｈ Ｅ、Ｃ，Ｃ，（１９８７）、 ｐ１３５
１８−５２５に示されるものがある。Among these, multi-chip modules using flip-chip connections, which can be surface-mounted and have the smallest lead inductance, are one of the most promising mounting technologies in terms of performance. As a conventional technology of a multi-chip module using a pre-lag chip, for example, C, T, Bar et al, "Hulti-Chip P"
ackaging Design for VLSI-
Based 5ysten”IEEE Proc, o
f 37th E, C, C, (1987), p135
There is one shown in No. 18-525.
これはシリコーンを用いた実装基板上にポリイミド膜と
銅配線よりなる多層配線を形成している。In this method, multilayer wiring consisting of a polyimide film and copper wiring is formed on a silicone mounting board.
ＬＳＩチップに半田バンプを形成し、その実装基板にフ
リップチップ接続している。そして全体をセラミックパ
ッケージの中に入れて気密封止している。Solder bumps are formed on the LSI chip and connected to the mounting board by flip-chip. The entire device is then placed in a ceramic package and hermetically sealed.
この従来のマルチチップモジュールではＬＳＩチップで
発生した熱は半田バンプを通って実装基板に伝わり、そ
の下に取り付けられたヒートシンクを介して大気中に放
熱される。In this conventional multi-chip module, the heat generated in the LSI chip is transmitted to the mounting board through the solder bumps, and is radiated into the atmosphere through the heat sink attached below.
以上述べたように、この従来のマルチチップモジュール
はチップで発生した熱は半田バンプを介して放熱される
か、形成プロセスでの制約から半田バンプをある程度小
さくしなけれはならないなめ、その部分で大きな熱抵抗
が生じる。このためモジュール全体でも大きな熱抵抗に
なってしまい、発熱量の大きなチップには適用できない
という大きな問題点があった。As mentioned above, in this conventional multi-chip module, the heat generated in the chip is dissipated through the solder bumps, or the solder bumps have to be made small to some extent due to constraints in the formation process. Heat resistance occurs. As a result, the entire module has a large thermal resistance, which poses a major problem in that it cannot be applied to chips that generate a large amount of heat.
また従来のマルチチップモジュールはセラミックパッケ
ージに封止されているため特殊なパッケージであること
にもよりコストが高く、また大型パッケージとなるため
封止が困難である等の問題点もあった。Furthermore, since conventional multi-chip modules are sealed in ceramic packages, the costs are high due to the special packaging, and there are also problems such as difficulty in sealing the large packages.
本発明の目的は上記課題を解決したマルチチップモジュ
ールを提供することにある。An object of the present invention is to provide a multi-chip module that solves the above problems.
前記目的を達成するため、本発明に係るマルチチップモ
ジュールにおいては、複数のＬＳＩチップを回路基板に
フリップチップ実装してなるマルチチップモジュールで
あって、
前記ＬＳＩチップの少なくとも素子の形成された面は樹
脂により封止され、かつ前記素子の形成された面と反対
面は金属板を介してあるいは直接にヒートシンクに取り
付けであるものである。In order to achieve the above object, a multi-chip module according to the present invention is a multi-chip module in which a plurality of LSI chips are flip-chip mounted on a circuit board, wherein at least the surface of the LSI chip on which elements are formed is It is sealed with a resin, and the surface opposite to the surface on which the element is formed is attached to a heat sink via a metal plate or directly.
また、前記ＬＳＩチップと前記回路基板との隙間に前記
樹脂がポッティング形成されているものであり、
また前記ＬＳＩチップおよび前記回路基板との全体が樹
脂でモールドされているものである。Further, the resin is potted in a gap between the LSI chip and the circuit board, and the LSI chip and the circuit board are entirely molded with resin.
本発明のマルチチップモジュールはＬＳＩチップをフリ
ップチップ接続しており
（１）ＬＳＩチップの裏面に金属板およびヒートシンク
が接続されている。In the multi-chip module of the present invention, LSI chips are flip-chip connected, and (1) a metal plate and a heat sink are connected to the back surface of the LSI chip.
（２）ＬＳＩチップと基板間を樹脂で封止し、チップの
気密性を確保する。(2) Seal the space between the LSI chip and the substrate with resin to ensure airtightness of the chip.
という特徴をもっている。It has the following characteristics.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
（実施例１） 第１図は本発明の実施例１を示す断面図である。(Example 1) FIG. 1 is a sectional view showing a first embodiment of the present invention.
図において、本発明の実施例１では、ＬＳＩチップ１０
１には半田バンプ１０２を形成している。また実装回路
基板１０３はシリコーンを用いて形成されており、その
上にポリイミド層と銅配線よりなる多層配線層１０４が
形成されている。ＬＳＩチップ１０１と実装回路基板１
０３は半田バンプ１０２を介してフリップチップ接続さ
れている。In the figure, in the first embodiment of the present invention, an LSI chip 10
1 has solder bumps 102 formed thereon. Moreover, the mounted circuit board 103 is formed using silicone, and a multilayer wiring layer 104 made of a polyimide layer and copper wiring is formed thereon. LSI chip 101 and mounted circuit board 1
03 are flip-chip connected via solder bumps 102.
ＬＳＩチップ１０１と実装回路基板１０３の間にはポッ
ティング等により樹脂層１０５により封止されている。The space between the LSI chip 101 and the mounted circuit board 103 is sealed with a resin layer 105 by potting or the like.
実装回路基板１０３はシリコーン樹脂層１０６を介して
銅ダンゲステン板１０７が取り付けられている。A copper dungesten plate 107 is attached to the mounted circuit board 103 via a silicone resin layer 106.
ＬＳＩチップ１０１の裏面には銀ペースト層１０８を介
して銅等よりなる金属板１０９を接続しである。A metal plate 109 made of copper or the like is connected to the back surface of the LSI chip 101 via a silver paste layer 108.
放熱板１０９にはシリコーン等を用いたヒートシンク接
着用樹脂層１１０を介してヒートシンク１１１が取り付
けられている。A heat sink 111 is attached to the heat sink 109 via a heat sink adhesive resin layer 110 made of silicone or the like.
本発明の実施例１では、ＬＳＩチップ１０１で発生した
熱は主として金属板１０９を介してヒートシンク１１１
より放出されるため、熱の経路を短く、かつ広くとれる
こととなり、熱抵抗を小さくできるという大きな利点を
有することが分かる。In the first embodiment of the present invention, the heat generated in the LSI chip 101 is mainly transferred to the heat sink 111 via the metal plate 109.
It can be seen that this has the great advantage of being able to make the heat path shorter and wider, and the thermal resistance can be lowered.
これを熱シミュレーションにより確認したところ、熱抵
抗値は
従来のマルチチップモジュール
・・・３．２３ （’Ｃ／Ｗ ＞
本発明のマルチチップモジュール
・・・１．９８（”Ｃ／Ｗ）
となっており、熱抵抗を大幅に低減できることが分かる
６
また本発明ではＬＳＩチップ１０１を樹脂層１０５を用
いて封止している。このなめ、低コストであり、封止も
容易である。またヒートシンク１１１の取付時にはＬＳ
Ｉチップ１０１に大きな力が加わるが、その力は樹脂層
１０５により大幅に緩和されるという利点もある。When this was confirmed by thermal simulation, the thermal resistance value was 3.23 ('C/W) for the conventional multi-chip module > 1.98 ('C/W) for the multi-chip module of the present invention. It can be seen that the thermal resistance can be significantly reduced.6 Furthermore, in the present invention, the LSI chip 101 is sealed using the resin layer 105.This layer is low in cost and easy to seal.In addition, the heat sink LS when installing 111
Although a large force is applied to the I-chip 101, there is also the advantage that the force is significantly alleviated by the resin layer 105.
（実施例２） 第２図は本発明の実権例２を示す断面図である。(Example 2) FIG. 2 is a sectional view showing a second practical example of the present invention.
図において、本発明の実施例２は、基本的には実施例１
と同じであり、実施例１と同様にＬＳＩチップ２０１は
半田バンプ２０２を介し多層配線層２０３の形成された
実装回路基板２０４とフリップチップ接続されている。In the figure, Embodiment 2 of the present invention basically corresponds to Embodiment 1.
Similarly to the first embodiment, an LSI chip 201 is flip-chip connected to a mounted circuit board 204 on which a multilayer wiring layer 203 is formed via solder bumps 202.
ＬＳＩチップ２０１の裏面には銀ペースト層２０５を介
して銅等よりなる金属板２０６を接続しである。A metal plate 206 made of copper or the like is connected to the back surface of the LSI chip 201 via a silver paste layer 205.
これらの各部品２０１〜２０６全体にエポキシ樹脂等を
用いてモールドし樹脂層２０７を形成し、金属板２０６
上部にのみヒートシンク取り付は穴２０８を形成してい
る。さらに放熱板２０６上部にはシリコーン等を用いた
ヒートシンク接続用樹脂層２０７を介してヒートシンク
２１０が取り付けられている。The entirety of each of these parts 201 to 206 is molded using epoxy resin or the like to form a resin layer 207, and the metal plate 206
A hole 208 is formed only in the upper part for attaching the heat sink. Furthermore, a heat sink 210 is attached to the upper part of the heat sink 206 via a heat sink connecting resin layer 207 made of silicone or the like.
この本発明の実施例２では実施例１に比べＬＳＩチップ
２０１および多層配線層２０３の全体を樹脂層２０７で
覆うことかできるため、耐湿性を大幅に向上のみならず
、実装回路基板２０４にシリコーンを用いる場合に強度
を確保できるため、銅タングステン板等の補強が必要な
くなりコストも低減するという利点を有する。In the second embodiment of the present invention, compared to the first embodiment, the entire LSI chip 201 and the multilayer wiring layer 203 can be covered with the resin layer 207, which not only greatly improves the moisture resistance but also coats the mounted circuit board 204 with silicone. Since strength can be ensured when using copper tungsten plates, there is no need for reinforcement with copper tungsten plates, etc., which has the advantage of reducing costs.
以上説明したように本発明により、モジュール全体の熱
抵抗が低くなるという大きな利点を有する。また本発明
は従来技術よりも低コストであり、封止も容易であると
いう利点も有する。As explained above, the present invention has the great advantage of lowering the thermal resistance of the entire module. The present invention also has the advantage of being lower cost and easier to seal than the prior art.
第１図は本発明の実施例１を示す断面図、第２図は本発
明の実施例２を示す断面図である。
１０１ 、２０１・・・ＬＳＩチップ
１０２ 、２０２・・・半田バング
１０３ 、２０４・・・実装回路基板
１０４ 、２０３・・・多層配線層
１０５ 、２０７・・・樹脂層
１０６・・・シリコーン樹脂層
１０７・・・銅タングステン板
１０８ 、２０５・・・銀ペースト層
１０９ 、２０９・・・ヒートシンク接着用樹脂層１１
１ 、２１０・・・ヒートシンク
２０８・・・ヒートシンク取り付は穴
特許出願人 日本電気株式会社
′・−１年
／θ７−−−乙ＳＩチアア
１０２− モヨバンフ１
／刀−Ｋ牧ａ路基板
層−４嗜め鋸
１０δ−・−罫バースト層
腐−錫板
ｔｔｌｌ−！−） ＞ン７＃４１ｆＨＭＵ〃ｌ −〜−
１−７−ランク
第
図FIG. 1 is a sectional view showing a first embodiment of the present invention, and FIG. 2 is a sectional view showing a second embodiment of the present invention. 101, 201... LSI chip 102, 202... Solder bang 103, 204... Mounted circuit board 104, 203... Multilayer wiring layer 105, 207... Resin layer 106... Silicone resin layer 107 ...Copper tungsten plate 108, 205...Silver paste layer 109, 209...Resin layer 11 for heat sink adhesion
1, 210...Heat sink 208...Heat sink mounting hole Patent applicant NEC Corporation'-1 year/θ7--Otsu SI Cheer 102-Moyo Banfu 1/Katana-K Maki a road board layer- 4 Saw 10δ-・-Ruled burst layer rot-Tin plate ttll-! -) >n7#41fHMU〃l -～-
1-7-Rank chart
Claims (3)
実装してなるマルチチップモジュールであって、 前記ＬＳＩチップの少なくとも素子の形成された面は樹
脂により封止され、かつ前記素子の形成された面と反対
面は金属板を介してあるいは直接にヒートシンクに取り
付けてあることを特徴とするマルチチップモジュール。(1) A multi-chip module formed by flip-chip mounting a plurality of LSI chips on a circuit board, wherein at least a surface of the LSI chip on which an element is formed is sealed with a resin, and a surface on which the element is formed. A multi-chip module characterized in that the opposite side is attached to a heat sink via a metal plate or directly.
樹脂がポッティング形成されていることを特徴とする請
求項第（１）項記載のマルチチップモジュール。(2) The multi-chip module according to claim 1, wherein the resin is potted in a gap between the LSI chip and the circuit board.
樹脂でモールドされていることを特徴とする請求項第（
１）項記載のマルチチップモジュール。(3) The LSI chip and the circuit board are entirely molded with resin.
The multi-chip module described in section 1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17096590A JPH0458551A (en) | 1990-06-28 | 1990-06-28 | Multichip module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17096590A JPH0458551A (en) | 1990-06-28 | 1990-06-28 | Multichip module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0458551A true JPH0458551A (en) | 1992-02-25 |
Family
ID=15914654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17096590A Pending JPH0458551A (en) | 1990-06-28 | 1990-06-28 | Multichip module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0458551A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5604978A (en) * | 1994-12-05 | 1997-02-25 | International Business Machines Corporation | Method for cooling of chips using a plurality of materials |
| US5757073A (en) * | 1996-12-13 | 1998-05-26 | International Business Machines Corporation | Heatsink and package structure for wirebond chip rework and replacement |
| US6313521B1 (en) | 1998-11-04 | 2001-11-06 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| US6720650B2 (en) * | 2000-07-13 | 2004-04-13 | Nec Electronics Corporation | Semiconductor device having heat spreader attached thereto and method of manufacturing the same |
| EP1198005A4 (en) * | 1999-03-26 | 2004-11-24 | Hitachi Ltd | Semiconductor module and method of mounting |
| US6940162B2 (en) | 1999-03-26 | 2005-09-06 | Renesas Technology Corp. | Semiconductor module and mounting method for same |
| JP2017191904A (en) * | 2016-04-15 | 2017-10-19 | オムロン株式会社 | Heat radiation structure of semiconductor device |
-
1990
- 1990-06-28 JP JP17096590A patent/JPH0458551A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5604978A (en) * | 1994-12-05 | 1997-02-25 | International Business Machines Corporation | Method for cooling of chips using a plurality of materials |
| US5724729A (en) * | 1994-12-05 | 1998-03-10 | International Business Machines Corporation | Method and apparatus for cooling of chips using a plurality of customized thermally conductive materials |
| US5757073A (en) * | 1996-12-13 | 1998-05-26 | International Business Machines Corporation | Heatsink and package structure for wirebond chip rework and replacement |
| US6134776A (en) * | 1996-12-13 | 2000-10-24 | International Business Machines Corporation | Heatsink and package structure for wirebond chip rework and replacement |
| US6313521B1 (en) | 1998-11-04 | 2001-11-06 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| EP1198005A4 (en) * | 1999-03-26 | 2004-11-24 | Hitachi Ltd | Semiconductor module and method of mounting |
| US6940162B2 (en) | 1999-03-26 | 2005-09-06 | Renesas Technology Corp. | Semiconductor module and mounting method for same |
| US6720650B2 (en) * | 2000-07-13 | 2004-04-13 | Nec Electronics Corporation | Semiconductor device having heat spreader attached thereto and method of manufacturing the same |
| JP2017191904A (en) * | 2016-04-15 | 2017-10-19 | オムロン株式会社 | Heat radiation structure of semiconductor device |
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