JP3169753B2 - Resin-sealed package and electronic circuit device - Google Patents
Resin-sealed package and electronic circuit deviceInfo
- Publication number
- JP3169753B2 JP3169753B2 JP25394893A JP25394893A JP3169753B2 JP 3169753 B2 JP3169753 B2 JP 3169753B2 JP 25394893 A JP25394893 A JP 25394893A JP 25394893 A JP25394893 A JP 25394893A JP 3169753 B2 JP3169753 B2 JP 3169753B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- thermal expansion
- sealed package
- coefficient
- filling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明はエリアアレイタイプの
半導体チップの入出力端子を中間キャリア基板に接続は
んだによりフリップチップ接続し、半導体チップと中間
キャリア基板との間に充填樹脂を充填し、半導体チップ
の少なくとも側部をモールド樹脂で封止した樹脂封止パ
ッケージ、樹脂封止パッケージを絶縁配線基板に実装し
た電子回路装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an input / output terminal of an area array type semiconductor chip is flip-chip connected to an intermediate carrier substrate by solder, and a filling resin is filled between the semiconductor chip and the intermediate carrier substrate. The present invention relates to a resin-sealed package in which at least a side portion of a chip is sealed with a mold resin, and an electronic circuit device in which the resin-sealed package is mounted on an insulated wiring board.
【０００２】[0002]
【従来の技術】最近のパーソナルコンピュータ、ワーク
ステーション等の電子計算機においては、ＬＳＩパッケ
ージ等の樹脂封止パッケージを絶縁配線基板に実装し、
絶縁配線基板を複数個組み合わせてモジュール基板上に
配置して、中央演算処理装置（ＣＰＵ）としてユニット
化している。2. Description of the Related Art In recent computers such as personal computers and workstations, a resin-sealed package such as an LSI package is mounted on an insulated wiring board.
A plurality of insulated wiring boards are combined and arranged on a module board to form a unit as a central processing unit (CPU).
【０００３】このような電子計算機を高速化するために
は、演算や記憶に用いられる半導体チップをより高集積
化しなければならないが、これに供ない半導体チップの
入出力端子数が増加し、入出力端子の接続は微細化の一
途をたどっている。In order to increase the speed of such an electronic computer, it is necessary to increase the degree of integration of semiconductor chips used for calculation and storage. The connection of the output terminal is steadily miniaturized.
【０００４】現在のＬＳＩパッケージにおいては、ＬＳ
Ｉチップの入出力端子が直線状に設けられ、入出力端子
のピッチが０．３ｍｍのＱＦＰ、ＴＣＰ等のＬＳＩパッ
ケージが実用化段階に来ている。これらの技術について
は、マイクロエレクトロニクス パッケージング ハン
ドブック（Rao R. Tummala, Eugene J. Rymazewski著、
日経ＢＰ社（1991.3）、P.326〜337およびP.425〜429）
に記載されている。In the current LSI package, LS
An I / O terminal of an I chip is provided in a straight line, and an LSI package such as QFP or TCP having a pitch of the input / output terminal of 0.3 mm has come to practical use. These technologies are described in the Microelectronics Packaging Handbook (by Rao R. Tummala, Eugene J. Rymazewski,
Nikkei BP (1991.3), P.326-337 and P.425-429)
It is described in.
【０００５】しかし、このようなＬＳＩパッケージにお
いては、ＬＳＩチップの入出力端子の数がさらに多くな
ると、ＬＳＩチップを大型化しなければならない。However, in such an LSI package, when the number of input / output terminals of the LSI chip further increases, the size of the LSI chip must be increased.
【０００６】そこで、所定面全面に入出力端子が設けら
れたエリアアレイタイプの半導体チップの入出力端子を
接続はんだでフリップチップ接続したＯＭＰＡＣ、ＢＧ
Ａ等の樹脂封止パッケージが注目されている。そして、
ベアチップをプリント基板にフリップチップ接続して樹
脂封止する技術については、樹脂封止フリップチップ実
装の信頼性と応力解析（塚田裕、他１名、日本機械学会
第７０期全国大会講演論文集（Vol.Ｂ）、p.525〜527）
に記載されており、中間キャリア基板を用いた樹脂封止
パッケージについては、セラミック基板上のフリップチ
ップ封止（Flip-Chip Encapsulation on Ceramic Subst
rates、J. Clementi、他５名、ECTC 43rd.、Vol.1（199
3）、p.175〜181）に記載されている。Therefore, OMPAC, BG in which input / output terminals of an area array type semiconductor chip having input / output terminals provided on the entire surface of a predetermined surface are flip-chip connected by connection solder.
A resin-sealed package such as A has attracted attention. And
For the technology of flip-chip connection of bare chips to a printed circuit board and resin encapsulation, see the reliability and stress analysis of resin-encapsulated flip-chip mounting (Yutaka Tsukada, et al., Proceedings of the 70th Annual Meeting of the Japan Society of Mechanical Engineers ( Vol.B), p.525-527)
For the resin-encapsulated package using an intermediate carrier substrate, refer to Flip-Chip Encapsulation on Ceramic Substrate on a ceramic substrate.
rates, J. Clementi, 5 others, ECTC 43rd., Vol.1 (199
3), pages 175 to 181).
【０００７】図９はこのような従来の樹脂封止パッケー
ジを有する電子回路装置の一部を示す概略断面図であ
る。図に示すように、エリアアレイタイプのＬＳＩチッ
プ等の半導体チップ１の入出力端子がセラミックからな
る中間キャリア基板１１に接続はんだ２によりフリップ
チップ接続され、半導体チップ１がモールド樹脂１２で
封止され、半導体チップ１と中間キャリア基板１１との
間に充填樹脂１３が充填され、モールド樹脂１２と充填
樹脂１３とは一体で同一の樹脂からなり、モールド樹脂
１２、充填樹脂１３の熱膨張率は接続はんだ２の熱膨張
率よりも大きい。また、樹脂封止パッケージは接続はん
だ５により樹脂からなる絶縁配線基板６に実装されてい
る。FIG. 9 is a schematic sectional view showing a part of an electronic circuit device having such a conventional resin-sealed package. As shown in the figure, input / output terminals of a semiconductor chip 1 such as an area array type LSI chip are flip-chip connected to an intermediate carrier substrate 11 made of ceramic by a connecting solder 2, and the semiconductor chip 1 is sealed with a mold resin 12. The filling resin 13 is filled between the semiconductor chip 1 and the intermediate carrier substrate 11, and the molding resin 12 and the filling resin 13 are integrally formed of the same resin. It is larger than the thermal expansion coefficient of the solder 2. The resin-sealed package is mounted on an insulated wiring board 6 made of resin by connection solder 5.
【０００８】[0008]
【発明が解決しようとする課題】しかし、このような樹
脂封止パッケージ、電子回路装置においては、実装プロ
セス時に樹脂封止パッケージが熱圧着され、実稼働時に
半導体チップから発熱したときに、充填樹脂１３、接続
はんだ２に熱が加えられるから、充填樹脂１３、接続は
んだ２が熱膨脹しようとするが、充填樹脂１３の左右方
向（図９紙面左右方向）の変形は拘束されているので、
充填樹脂１３、接続はんだ２に熱応力が発生する。この
ため、充填樹脂１３、接続はんだ２は上下方向（図９紙
面上下方向）に変形するが、充填樹脂１３の熱膨張率は
接続はんだ２の熱膨張率より大きいから、たとえば充填
樹脂１３、接続はんだ２のヤング率、ポアソン比が等し
いと、充填樹脂１３の接続はんだ２と接している部分の
上下方向の変位量は充填樹脂１３の上記部分と接してい
る接続はんだ２の上下方向の変位量よりも大きいので、
充填樹脂１３から接続はんだ２に上下方向に力が作用す
る。したがって、接続はんだ２と半導体チップ１との接
続不良が生ずるから、信頼性が低い。However, in such a resin-sealed package and electronic circuit device, when the resin-sealed package is thermocompression-bonded during the mounting process and heat is generated from the semiconductor chip during actual operation, the charged resin is not filled. 13. Since heat is applied to the connection solder 2, the filling resin 13 and the connection solder 2 tend to thermally expand. However, since the deformation of the filling resin 13 in the left-right direction (left-right direction in FIG. 9) is restricted,
Thermal stress is generated in the filling resin 13 and the connection solder 2. For this reason, the filling resin 13 and the connection solder 2 are deformed in the vertical direction (vertical direction in FIG. 9), but since the coefficient of thermal expansion of the filling resin 13 is larger than the coefficient of thermal expansion of the connection solder 2, for example, When the Young's modulus and Poisson's ratio of the solder 2 are equal, the vertical displacement of the portion of the filling resin 13 in contact with the connection solder 2 is the vertical displacement of the connection solder 2 in contact with the portion of the filling resin 13. Is larger than
A vertical force acts on the connection solder 2 from the filling resin 13. Therefore, a connection failure between the connection solder 2 and the semiconductor chip 1 occurs, resulting in low reliability.
【０００９】この発明は上述の課題を解決するためにな
されたもので、信頼性が高い樹脂封止パッケージ、電子
回路装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a highly reliable resin-sealed package and electronic circuit device.
【００１０】[0010]
【課題を解決するための手段】この目的を達成するた
め、この発明においては、エリアアレイタイプの半導体
チップの入出力端子を中間キャリア基板に接続はんだに
よりフリップチップ接続し、上記半導体チップと上記中
間キャリア基板との間に充填樹脂を充填し、上記半導体
チップの少なくとも側部をモールド樹脂で封止した樹脂
封止パッケージにおいて、上記充填樹脂の熱膨張率を上
記接続はんだの熱膨張率より小さくし、樹脂からなる上
記中間キャリア基板を用い、上記モールド樹脂の熱膨張
率を上記中間キャリア基板の熱膨張率と上記接続はんだ
の熱膨張率との間の値とする。 In order to achieve this object, according to the present invention, an input / output terminal of an area array type semiconductor chip is flip-chip connected to an intermediate carrier substrate by connection solder, and the semiconductor chip and the intermediate chip are connected to each other. filling a filling resin between the carrier substrate, the resin-sealed package that seals at least the sides with the mold resin of the semiconductor chip, the thermal expansion coefficient of the filled resin is made smaller than the thermal expansion coefficient of the soldered , Consisting of resin
Using the intermediate carrier substrate, thermal expansion of the mold resin
The coefficient of thermal expansion of the intermediate carrier substrate and the connection solder
And the coefficient of thermal expansion.
【００１１】[0011]
【００１２】この場合、上記充填樹脂と上記モールド樹
脂とを同一の樹脂とする。In this case, the filling resin and the molding resin are the same resin.
【００１３】また、上記充填樹脂と上記モールド樹脂と
を異なる樹脂とする。Further, the filling resin and the molding resin are different resins.
【００１４】[0014]
【００１５】さらに、電子回路装置において、上記のい
ずれかの樹脂封止パッケージを絶縁配線基板に実装す
る。Further, in the electronic circuit device, any one of the resin-sealed packages described above is mounted on an insulated wiring board.
【００１６】[0016]
【作用】この樹脂封止パッケージ、電子回路装置におい
ては、実装プロセス時、実稼働時に充填樹脂、接続はん
だに熱が加えられ、充填樹脂、接続はんだに熱応力が発
生したときに、充填樹脂の熱膨張率は接続はんだの熱膨
張率より小さいから、充填樹脂から接続はんだに力が作
用することがなく、また樹脂からなる中間キャリア基板
を用いたときには、樹脂基板はセラミック基板と比較し
て安価であり、またモールド樹脂の熱膨張率を中間キャ
リア基板の熱膨張率と接続はんだの熱膨張率との間の値
としたときには、半導体チップとモールド樹脂との総合
的な熱膨張率が中間キャリア基板の熱膨張率に近くなる
から、実稼動時に半導体チップからの熱によってモール
ド樹脂、中間キャリア基板が加熱されたとしても、中間
キャリア基板の変形量と他の部分の変形量とがほぼ同じ
になる。 In this resin-sealed package and electronic circuit device, when heat is applied to the filling resin and the connection solder during the mounting process and actual operation, and thermal stress is generated in the filling resin and the connection solder, the filling resin and the connection solder are removed. since the thermal expansion coefficient is smaller than the thermal expansion coefficient of the connection solder, it is rather name that force acts from the filling resin to the connection solder, also made of a resin intermediate carrier substrate
Is used, the resin substrate is compared with the ceramic substrate.
And is inexpensive.
Value between the coefficient of thermal expansion of the rear substrate and the coefficient of thermal expansion of the connecting solder
And the total of the semiconductor chip and mold resin
Thermal expansion coefficient approaches that of the intermediate carrier substrate
From the semiconductor chip during operation
Even if the resin and intermediate carrier substrate are heated,
Deformation amount of carrier substrate is almost the same as other parts
become.
【００１７】[0017]
【００１８】また、充填樹脂とモールド樹脂とを同一の
樹脂としたときには、容易に製造することができる。When the same resin is used for the filling resin and the molding resin, it can be easily manufactured.
【００１９】また、充填樹脂とモールド樹脂とを異なる
樹脂としたときには、充填樹脂として流動性の良好な樹
脂を用い、モールド樹脂として充填樹脂の熱膨張率より
小さな熱膨張率を有する樹脂を用いることができる。When the filling resin and the molding resin are different from each other, a resin having good fluidity is used as the filling resin, and a resin having a coefficient of thermal expansion smaller than that of the filling resin is used as the molding resin. Can be.
【００２０】[0020]
【００２１】[0021]
【実施例】図１、図２はそれぞれこの発明に係る樹脂封
止パッケージを有する電子回路装置の一部を示す概略断
面図である。図に示すように、半導体チップ１の入出力
端子が樹脂からなる中間キャリア基板４に接続はんだ２
によりフリップチップ接続され、半導体チップ１がモー
ルド樹脂３で封止され、半導体チップ１と中間キャリア
基板４との間に充填樹脂９が充填されおり、モールド樹
脂３と充填樹脂９とは一体で同一の樹脂からなり、モー
ルド樹脂３、充填樹脂９の熱膨張率は接続はんだ２の熱
膨張率よりも小さく、また中間キャリア基板４の熱膨張
率よりも大きい。1 and 2 are schematic sectional views each showing a part of an electronic circuit device having a resin-sealed package according to the present invention. As shown in the figure, the input / output terminals of the semiconductor chip 1 are connected to an intermediate carrier substrate 4 made of resin.
And the semiconductor chip 1 is sealed with the molding resin 3, and the filling resin 9 is filled between the semiconductor chip 1 and the intermediate carrier substrate 4, and the molding resin 3 and the filling resin 9 are integrated and the same. The thermal expansion coefficients of the molding resin 3 and the filling resin 9 are smaller than the thermal expansion coefficient of the connection solder 2 and larger than the thermal expansion coefficient of the intermediate carrier substrate 4.
【００２２】これらの樹脂封止パッケージ、電子回路装
置においては、実装プロセス時、実稼働時に充填樹脂
９、接続はんだ２に熱が加えられ、充填樹脂９、接続は
んだ２に熱応力が発生したときに、充填樹脂９の熱膨張
率は接続はんだ２の熱膨張率より小さいから、充填樹脂
９から接続はんだ２に作用する力が小さいので、接続は
んだ２と半導体チップ１との接続不良が生じないため、
信頼性が高い。また、樹脂からなる中間キャリア基板４
を用いており、樹脂基板はセラミック基板より安価であ
るから、製造コストが安価である。この場合、図１０に
示すように、モールド樹脂１４の熱膨張率、形状等を考
慮せず、半導体チップ１とモールド樹脂１４との総合的
な熱膨張率すなわちモールド樹脂部の熱膨張率と中間キ
ャリア基板４の熱膨張率とが大きく相違するときには、
実稼動時に半導体チップ１からの熱によってモールド樹
脂１４、中間キャリア基板４が加熱された場合に、モー
ルド樹脂部の変形量と中間キャリア基板４の変形量とが
大きく相違するから、樹脂封止パッケージに大きな反り
が生ずるので、樹脂封止パッケージと絶縁回路基板６と
の接続不良が生ずる。これに対して、図１、図２に示し
た樹脂封止パッケージ、電子回路装置においては、モー
ルド樹脂３の熱膨張率は中間キャリア基板４の熱膨張率
より大きく、また半導体チップ１の熱膨張率は中間キャ
リア基板４の熱膨張率より小さいから、モールド樹脂３
の形状、大きさ等を考慮すれば、半導体チップ１とモー
ルド樹脂３との総合的な熱膨張率すなわちモールド樹脂
部の熱膨張率を中間キャリア基板４の熱膨張率とほぼ同
様の値にすることができる。このため、実稼動時に半導
体チップ１からの熱によってモールド樹脂３、中間キャ
リア基板４が加熱されたとしても、モールド樹脂部の変
形量と中間キャリア基板４の変形量とがほぼ同じになる
から、樹脂封止パッケージに生ずる反りが小さくなるの
で、樹脂封止パッケージと絶縁配線基板６との接続不良
が生ずることがないため、信頼性が高い。また、充填樹
脂９とモールド樹脂３とを同一の樹脂としているから、
容易に製造することができるので、製造コストが安価で
ある。In these resin-sealed packages and electronic circuit devices, when heat is applied to the filling resin 9 and the connection solder 2 during the mounting process and actual operation, and thermal stress is generated in the filling resin 9 and the connection solder 2, In addition, since the coefficient of thermal expansion of the filling resin 9 is smaller than the coefficient of thermal expansion of the connection solder 2, the force acting on the connection solder 2 from the filling resin 9 is small, so that the connection failure between the connection solder 2 and the semiconductor chip 1 does not occur. For,
High reliability. Also, an intermediate carrier substrate 4 made of resin
Since the resin substrate is cheaper than the ceramic substrate, the manufacturing cost is low. In this case, as shown in FIG. 10, the total thermal expansion coefficient of the semiconductor chip 1 and the molding resin 14, that is, the intermediate thermal expansion coefficient of the molding resin portion, is not considered without considering the thermal expansion coefficient and the shape of the molding resin 14. When the coefficient of thermal expansion of the carrier substrate 4 is significantly different,
When the molding resin 14 and the intermediate carrier substrate 4 are heated by heat from the semiconductor chip 1 during actual operation, the amount of deformation of the molding resin portion and the amount of deformation of the intermediate carrier substrate 4 are greatly different. Large warpage occurs, resulting in poor connection between the resin-sealed package and the insulating circuit board 6. On the other hand, in the resin-sealed package and the electronic circuit device shown in FIGS. 1 and 2, the coefficient of thermal expansion of the mold resin 3 is larger than the coefficient of thermal expansion of the intermediate carrier substrate 4 and the coefficient of thermal expansion of the semiconductor chip 1. Since the rate is smaller than the coefficient of thermal expansion of the intermediate carrier substrate 4, the molding resin 3
Considering the shape, size, etc. of the semiconductor chip 1 and the molding resin 3, the overall thermal expansion coefficient of the semiconductor chip 1 and the molding resin 3, that is, the thermal expansion coefficient of the molding resin portion, is set to substantially the same value as the thermal expansion coefficient of the intermediate carrier substrate 4. be able to. For this reason, even if the mold resin 3 and the intermediate carrier substrate 4 are heated by heat from the semiconductor chip 1 during actual operation, the deformation amount of the mold resin portion and the deformation amount of the intermediate carrier substrate 4 become substantially the same. Since the warpage generated in the resin-sealed package is reduced, a connection failure between the resin-sealed package and the insulated wiring board 6 does not occur, so that the reliability is high. Further, since the filling resin 9 and the molding resin 3 are the same resin,
Since it can be easily manufactured, the manufacturing cost is low.
【００２３】図３、図４はそれぞれこの発明に係る他の
樹脂封止パッケージを有する電子回路装置の一部を示す
概略断面図である。図に示すように、半導体チップ１の
背面に金属板７ａ、ＴＡＢテープの金属板７ｂが高熱伝
導性接着剤８で接着されている。FIGS. 3 and 4 are schematic sectional views each showing a part of an electronic circuit device having another resin-sealed package according to the present invention. As shown in the figure, a metal plate 7a and a metal plate 7b of a TAB tape are bonded to the back surface of the semiconductor chip 1 with a high thermal conductive adhesive 8.
【００２４】これらの樹脂封止パッケージ、電子回路装
置においては、モールド樹脂３、金属板７ａ、７ｂの形
状、大きさ等を考慮すれば、半導体チップ１、モールド
樹脂３、金属板７ａ、７ｂの総合的な熱膨張率すなわち
モールド樹脂部の熱膨張率を中間キャリア基板４の熱膨
張率とほぼ同様の値にすることができる。このため、実
稼動時に半導体チップ１からの熱によってモールド樹脂
３、中間キャリア基板４が加熱されたとしても、モール
ド樹脂部の変形量と中間キャリア基板４の変形量とがほ
ぼ同じになるから、樹脂封止パッケージに生ずる反りが
小さくなるので、樹脂封止パッケージと絶縁配線基板と
の接続不良が生ずることがないため、信頼性が高い。し
かも、半導体チップ１に発生した熱を金属板７ａ、７ｂ
を介して放熱することができるから、樹脂封止パッケー
ジの温度が高くならないので、充填樹脂９から接続はん
だ２に作用する力がより小さくなるとともに、樹脂封止
パッケージに発生する反りがより小さくなるから、信頼
性がより高くなる。また、図４に示した樹脂封止パッケ
ージ、電子回路装置においては、半導体チップ１に金属
薄板７ｂを接着したものをモールド樹脂３で封止すれ
ば、一括封止が可能であるから、量産化に適している。In these resin-sealed packages and electronic circuit devices, considering the shape and size of the mold resin 3 and the metal plates 7a and 7b, the semiconductor chip 1, the mold resin 3, and the metal plates 7a and 7b The overall coefficient of thermal expansion, that is, the coefficient of thermal expansion of the mold resin portion, can be set to substantially the same value as the coefficient of thermal expansion of the intermediate carrier substrate 4. For this reason, even if the mold resin 3 and the intermediate carrier substrate 4 are heated by the heat from the semiconductor chip 1 during the actual operation, the deformation amount of the mold resin portion and the deformation amount of the intermediate carrier substrate 4 become substantially the same. Since the warpage that occurs in the resin-sealed package is reduced, a connection failure between the resin-sealed package and the insulated wiring board does not occur, resulting in high reliability. Moreover, the heat generated in the semiconductor chip 1 is transferred to the metal plates 7a, 7b.
Since the heat can be dissipated through the package, the temperature of the resin-sealed package does not increase, so that the force acting on the connection solder 2 from the filling resin 9 becomes smaller and the warpage generated in the resin-sealed package becomes smaller. Therefore, the reliability becomes higher. In the resin-sealed package and the electronic circuit device shown in FIG. 4, if the semiconductor chip 1 and the thin metal plate 7b are bonded and sealed with the mold resin 3, the package can be sealed at a time. Suitable for.
【００２５】図５〜図８はそれぞれこの発明に係る他の
樹脂封止パッケージを有する電子回路装置の一部を示す
概略断面図である。図に示すように、充填樹脂１０とモ
ールド樹脂３とは異なる樹脂からなる。FIGS. 5 to 8 are schematic sectional views each showing a part of an electronic circuit device having another resin-sealed package according to the present invention. As shown in the figure, the filling resin 10 and the molding resin 3 are made of different resins.
【００２６】これらの樹脂封止パッケージ、電子回路装
置においては、充填樹脂１０として流動性の良好な樹脂
を用い、モールド樹脂３として充填樹脂１０の熱膨張率
より小さな熱膨張率を有する樹脂を用いることができる
から、充填樹脂１０を確実に充填することができるとと
もに、樹脂封止パッケージに生ずる反りを小さくするこ
とができるので、信頼性がより高くなる。In these resin-sealed packages and electronic circuit devices, a resin having good fluidity is used as the filling resin 10, and a resin having a coefficient of thermal expansion smaller than that of the filling resin 10 is used as the mold resin 3. Therefore, the filling resin 10 can be reliably filled, and the warpage generated in the resin-sealed package can be reduced, so that the reliability is further improved.
【００２７】なお、上述実施例においては、樹脂からな
る絶縁配線基板６を用いたが、セラミックからなる絶縁
配線基板を用いてもよい。また、上述実施例において
は、樹脂からなる中間キャリア基板４を用いたが、セラ
ミックからなる中間キャリア基板を用いてもよい。ま
た、上述実施例においては、半導体チップ１、モールド
樹脂３、金属板７ａ、７ｂの総合的な熱膨張率を中間キ
ャリア基板４の熱膨張率とほぼ同様の値にしたが、半導
体チップ１、モールド樹脂３の総合的な熱膨張率を中間
キャリア基板４の熱膨張率とほぼ同様の値にするととも
に、金属板として中間キャリア基板４の熱膨張率とほぼ
等しい熱膨張率を有するものを用いてもよい。また、図
３、図４、図７、図８に示した実施例においては、高熱
伝導性接着剤８を用いたが、代わりにはんだを用いても
よい。また、図４、図８に示した実施例においては、金
属板７ｂの突出部を封止後に加工して、冷却フィンと接
続すれば、冷却特性をさらに向上することができる。In the above embodiment, the insulating wiring board 6 made of resin is used, but an insulating wiring board made of ceramic may be used. Further, in the above embodiment, the intermediate carrier substrate 4 made of resin is used, but an intermediate carrier substrate made of ceramic may be used. Further, in the above-described embodiment, the total thermal expansion coefficient of the semiconductor chip 1, the mold resin 3, and the metal plates 7a and 7b is set to substantially the same value as the thermal expansion coefficient of the intermediate carrier substrate 4. The overall thermal expansion coefficient of the mold resin 3 is set to a value substantially similar to the thermal expansion coefficient of the intermediate carrier substrate 4, and a metal plate having a thermal expansion coefficient substantially equal to the thermal expansion coefficient of the intermediate carrier substrate 4 is used. You may. In the embodiments shown in FIGS. 3, 4, 7, and 8, the high thermal conductive adhesive 8 is used, but solder may be used instead. In the embodiment shown in FIGS. 4 and 8, if the protruding portion of the metal plate 7b is processed after sealing and connected to the cooling fin, the cooling characteristics can be further improved.
【００２８】[0028]
【発明の効果】以上説明したように、この発明に係る樹
脂封止パッケージ、電子回路装置においては、実装プロ
セス時、実稼働時に充填樹脂、接続はんだに熱が加えら
れ、充填樹脂、接続はんだに熱応力が発生したときに、
充填樹脂から接続はんだに作用する力が小さくなるか
ら、接続はんだと半導体チップとの接続不良が生じない
ので、信頼性が高く、また樹脂からなる中間キャリア基
板を用いたときには、樹脂基板はセラミック基板と比較
して安価であるから、製造コストが安価であり、またモ
ールド樹脂の熱膨張率を中間キャリア基板の熱膨張率と
接続はんだの熱膨張率との間の値としたときには、実稼
動時に半導体チップからの熱によってモールド樹脂、中
間キャリア基板が加熱されたとしても、中間キャリア基
板の変形量と他の部分の変形量とがほぼ同じになるか
ら、樹脂封止パッケージに生ずる反りが小さくなるの
で、樹脂封止パッケージと絶縁配線基板との接続不良が
生ずることがないため、信頼性が高い。 As described above, in the resin-sealed package and the electronic circuit device according to the present invention, heat is applied to the filling resin and the connection solder during the mounting process and during the actual operation, and the filling resin and the connection solder are heated. When thermal stress occurs,
Since the force acting from the filling resin to the connecting solder is reduced, connection since solder and no connection failure occurs between the semiconductor chip, rather high reliability, also an intermediate carrier base made of a resin
When using a board, the resin substrate is compared to the ceramic substrate
Manufacturing costs are low, and
The coefficient of thermal expansion of the mold resin is calculated as the coefficient of thermal expansion of the intermediate carrier substrate.
When the value is between the coefficient of thermal expansion of the connection solder,
During operation, heat from the semiconductor chip causes the molding resin
Even if the carrier substrate is heated,
Is the deformation of the plate almost the same as the deformation of other parts?
The warpage of the resin-encapsulated package
Insufficient connection between the resin-sealed package and the insulated wiring board
Since it does not occur, reliability is high.
【００２９】[0029]
【００３０】また、充填樹脂とモールド樹脂とを同一の
樹脂としたときには、容易に製造することができるか
ら、製造コストが安価である。Further, when the same resin is used for the filling resin and the molding resin, the resin can be easily manufactured, so that the manufacturing cost is low.
【００３１】また、充填樹脂とモールド樹脂とを異なる
樹脂としたときには、充填樹脂として流動性の良好な樹
脂を用い、モールド樹脂として充填樹脂の熱膨張率より
小さな熱膨張率を有する樹脂を用いることができるか
ら、充填樹脂を確実に充填することができるとともに、
樹脂封止パッケージに生ずる反りをより小さくすること
ができるので、信頼性が高くなる。When the filling resin and the molding resin are different resins, a resin having good fluidity is used as the filling resin, and a resin having a coefficient of thermal expansion smaller than that of the filling resin is used as the molding resin. Can be filled, the filling resin can be reliably filled,
Since the warpage generated in the resin-sealed package can be further reduced, the reliability is improved.
【００３２】[0032]
【００３３】このように、この発明の効果は顕著であ
る。As described above, the effect of the present invention is remarkable.
【図１】この発明に係る樹脂封止パッケージを有する電
子回路装置の一部を示す概略断面図である。FIG. 1 is a schematic sectional view showing a part of an electronic circuit device having a resin-sealed package according to the present invention.
【図２】この発明に係る他の樹脂封止パッケージを有す
る電子回路装置の一部を示す概略断面図である。FIG. 2 is a schematic sectional view showing a part of an electronic circuit device having another resin-sealed package according to the present invention.
【図３】この発明に係る他の樹脂封止パッケージを有す
る電子回路装置の一部を示す概略断面図である。FIG. 3 is a schematic sectional view showing a part of an electronic circuit device having another resin-sealed package according to the present invention.
【図４】この発明に係る他の樹脂封止パッケージを有す
る電子回路装置の一部を示す概略断面図である。FIG. 4 is a schematic sectional view showing a part of an electronic circuit device having another resin-sealed package according to the present invention.
【図５】この発明に係る他の樹脂封止パッケージを有す
る電子回路装置の一部を示す概略断面図である。FIG. 5 is a schematic sectional view showing a part of an electronic circuit device having another resin-sealed package according to the present invention.
【図６】この発明に係る他の樹脂封止パッケージを有す
る電子回路装置の一部を示す概略断面図である。FIG. 6 is a schematic sectional view showing a part of an electronic circuit device having another resin-sealed package according to the present invention.
【図７】この発明に係る他の樹脂封止パッケージを有す
る電子回路装置の一部を示す概略断面図である。FIG. 7 is a schematic sectional view showing a part of an electronic circuit device having another resin-sealed package according to the present invention.
【図８】この発明に係る他の樹脂封止パッケージを有す
る電子回路装置の一部を示す概略断面図である。FIG. 8 is a schematic sectional view showing a part of an electronic circuit device having another resin-sealed package according to the present invention.
【図９】従来の樹脂封止パッケージを有する電子回路装
置の一部を示す概略断面図である。FIG. 9 is a schematic sectional view showing a part of an electronic circuit device having a conventional resin-sealed package.
【図１０】この発明に係る樹脂封止パッケージ、電子回
路装置の効果を説明するための図である。FIG. 10 is a diagram for explaining the effects of the resin-sealed package and the electronic circuit device according to the present invention.
１…半導体チップ ２…接続はんだ ３…モールド樹脂 ４…中間キャリア基板 ６…絶縁配線基板 ７ａ、７ｂ…金属板 ９…充填樹脂 １０…充填樹脂 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Connection solder 3 ... Mold resin 4 ... Intermediate carrier board 6 ... Insulated wiring board 7a, 7b ... Metal plate 9 ... Filled resin 10 ... Filled resin
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭61−271847（ＪＰ，Ａ) 特開 昭62−136865（ＪＰ，Ａ) 特開 平２−69945（ＪＰ，Ａ) 特開 昭63−316447（ＪＰ，Ａ) 特開 昭63−25686（ＪＰ，Ａ) 特開 昭60−94744（ＪＰ，Ａ) 特開 平３−94460（ＪＰ，Ａ) 特開 平４−22144（ＪＰ，Ａ) 特開 平４−211150（ＪＰ，Ａ) 特開 平５−326625（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 23/29 H01L 23/31 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-61-271847 (JP, A) JP-A-62-136865 (JP, A) JP-A-2-69945 (JP, A) JP-A 63-271845 316447 (JP, A) JP-A-63-25686 (JP, A) JP-A-60-94744 (JP, A) JP-A-3-94460 (JP, A) JP-A-4-22144 (JP, A) JP-A-4-211150 (JP, A) JP-A-5-326625 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/60 H01L 23/29 H01L 23/31
Claims (4)
力端子を中間キャリア基板に接続はんだによりフリップ
チップ接続し、上記半導体チップと上記中間キャリア基
板との間に充填樹脂を充填し、上記半導体チップの少な
くとも側部をモールド樹脂で封止した樹脂封止パッケー
ジにおいて、上記充填樹脂の熱膨張率を上記接続はんだ
の熱膨張率より小さくし、樹脂からなる上記中間キャリ
ア基板を用い、上記モールド樹脂の熱膨張率を上記中間
キャリア基板の熱膨張率と上記接続はんだの熱膨張率と
の間の値としたことを特徴とする樹脂封止パッケージ。An input / output terminal of an area array type semiconductor chip is flip-chip connected to an intermediate carrier substrate by connecting solder, and a filling resin is filled between the semiconductor chip and the intermediate carrier substrate. In a resin-sealed package in which at least a side portion is sealed with a mold resin, a thermal expansion coefficient of the filling resin is smaller than a thermal expansion coefficient of the connection solder, and the intermediate carrier made of resin is formed.
Using a substrate, set the coefficient of thermal expansion of the mold resin
The coefficient of thermal expansion of the carrier board and the coefficient of thermal expansion of the connection solder
A resin-sealed package characterized by having a value between the above .
の樹脂としたことを特徴とする請求項１に記載の樹脂封
止パッケージ。2. The resin-sealed package according to claim 1 , wherein the filling resin and the molding resin are the same resin.
る樹脂としたことを特徴とする請求項１に記載の樹脂封
止パッケージ。3. The resin-sealed package according to claim 1 , wherein said filling resin and said molding resin are different resins.
封止パッケージを絶縁配線基板に実装したことを特徴と
する電子回路装置。4. The electronic circuit device, characterized in that the resin sealing package according to any one of claims 1 to 3 is mounted on the insulating circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25394893A JP3169753B2 (en) | 1993-10-12 | 1993-10-12 | Resin-sealed package and electronic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25394893A JP3169753B2 (en) | 1993-10-12 | 1993-10-12 | Resin-sealed package and electronic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07111278A JPH07111278A (en) | 1995-04-25 |
| JP3169753B2 true JP3169753B2 (en) | 2001-05-28 |
Family
ID=17258215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25394893A Expired - Fee Related JP3169753B2 (en) | 1993-10-12 | 1993-10-12 | Resin-sealed package and electronic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3169753B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2825083B2 (en) * | 1996-08-20 | 1998-11-18 | 日本電気株式会社 | Semiconductor element mounting structure |
| JP4836847B2 (en) * | 1997-10-15 | 2011-12-14 | 株式会社東芝 | Semiconductor device and manufacturing method of semiconductor device |
| JP2002111222A (en) * | 2000-10-02 | 2002-04-12 | Matsushita Electric Ind Co Ltd | Multilayer substrate |
| JP2003060117A (en) * | 2001-08-10 | 2003-02-28 | Texas Instr Japan Ltd | Method for manufacturing semiconductor |
| JP4595265B2 (en) * | 2001-08-13 | 2010-12-08 | 日本テキサス・インスツルメンツ株式会社 | Manufacturing method of semiconductor device |
| JP5502268B2 (en) * | 2006-09-14 | 2014-05-28 | 信越化学工業株式会社 | Resin composition set for system-in-package semiconductor devices |
-
1993
- 1993-10-12 JP JP25394893A patent/JP3169753B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07111278A (en) | 1995-04-25 |
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