JPH045843A - Bonding pad - Google Patents

Bonding pad

Info

Publication number
JPH045843A
JPH045843A JP2106915A JP10691590A JPH045843A JP H045843 A JPH045843 A JP H045843A JP 2106915 A JP2106915 A JP 2106915A JP 10691590 A JP10691590 A JP 10691590A JP H045843 A JPH045843 A JP H045843A
Authority
JP
Japan
Prior art keywords
metal layer
metal
bonding
layer
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2106915A
Other languages
Japanese (ja)
Inventor
Mitsuaki Fujihira
藤平 充明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2106915A priority Critical patent/JPH045843A/en
Publication of JPH045843A publication Critical patent/JPH045843A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05085Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089Disposition of the additional element
    • H01L2224/05093Disposition of the additional element of a plurality of vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4845Details of ball bonds
    • H01L2224/48451Shape
    • H01L2224/48453Shape of the interface with the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Abstract

PURPOSE:To improve a shearing strength, and to eliminate peeling of a metal layer from a semiconductor device by providing a coupling metal for coupling upper and lower metal layers, and covering the outer peripheries of the upper and lower layers with insulating films. CONSTITUTION:Bonding pads 26 are formed of first and second metal layers 22, 23, and a coupling metal 25 for coupling the layer 22 to the layer 23 on a semiconductor substrate 21. The layer 22 is covered with an interlayer insulating film 28 together with the substrate 21 therearound and a metal interconnection pattern 27 except the part bonded to the metal 25. Accordingly, the layer 22 is pressed to the substrate 21 by the film 28 covering the outer periphery. The layer 23 is covered with a passivation film 30 together with the film 28 at the outer periphery. Therefore, the layer 23 is pressed to the substrate 21 by the film 30 covering the outer periphery.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に形成されるボンディングパッド
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bonding pad formed on a semiconductor device.

〔従来の技術〕[Conventional technology]

半導体装置に形成されるボンディングパッドは、従来、
半導体装置を構成する半導体基板上に微小な一枚の金属
板として形成され、その外周部がパッシベーション膜等
の絶縁膜により題イ〕れた構造となっている。化合物半
導体装置に形成されるボンディングパッドでは、化合物
半導体基板の表面に形成されることが多く、この場合に
は化合物′1!。
Bonding pads formed on semiconductor devices are conventionally
It is formed as a single minute metal plate on a semiconductor substrate constituting a semiconductor device, and has a structure in which the outer periphery is covered with an insulating film such as a passivation film. Bonding pads formed in compound semiconductor devices are often formed on the surface of a compound semiconductor substrate, and in this case, compound '1! .

導体基板表面にパターン形成される第1層配線金属をそ
の゛ままボンディングパッドとして用いることが多い。
The first layer wiring metal patterned on the surface of the conductor substrate is often used as it is as a bonding pad.

第5図に、多層配線を有する半導体装置に形成された従
来のボンディングパッドを示す。図示した半導体装置に
おいては、半導体基板1の表面に第1層配線金属2がパ
ターン形成されており、第1層配線金属2は絶縁膜3に
より覆われている。
FIG. 5 shows a conventional bonding pad formed on a semiconductor device having multilayer wiring. In the illustrated semiconductor device, a first layer wiring metal 2 is patterned on the surface of a semiconductor substrate 1, and the first layer wiring metal 2 is covered with an insulating film 3.

絶縁膜3の上面には第2層配線金属がパターン形成され
、第2層配線金属により平面形状が略11一方形のボン
ディングパッド5が形成されている。そして、ボンディ
ングパッド5は絶縁膜3を貫通ずるバイアメタル6によ
り第1層配線金属2と電気的に接続され、その表面外周
部はその周囲の絶縁膜3と共にパッシベーション膜7に
より覆われた構造となっている。
A second layer wiring metal is patterned on the upper surface of the insulating film 3, and a bonding pad 5 having an approximately 11-sided planar shape is formed by the second layer wiring metal. The bonding pad 5 is electrically connected to the first layer wiring metal 2 by a via metal 6 passing through the insulating film 3, and the outer periphery of the surface thereof is covered with a passivation film 7 together with the surrounding insulating film 3. It has become.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した如くの従来のボンディングパッドに対して金線
等のボンディングワイヤを熱圧む法や超音波併用熱圧着
法等で接続する場合、ボンディングパッドの底面と半導
体基板の上面あるいはボンディングパッドの底面と絶縁
膜の上面の接着力(密着力)が十分でないため、ボンデ
ィングの作業中にワイヤに加わる張力によりボンディン
グパッドが半導体装置から剥離し易いという不具合があ
り、当該剥離が多発していた。
When bonding wires such as gold wires are connected to conventional bonding pads as described above by hot pressing or ultrasonic hot pressing, the bottom surface of the bonding pad is connected to the top surface of the semiconductor substrate or the bottom surface of the bonding pad. Since the adhesive strength (adhesion strength) on the upper surface of the insulating film is not sufficient, there is a problem in that the bonding pad is easily peeled off from the semiconductor device due to the tension applied to the wire during the bonding operation, and such peeling occurs frequently.

そこで、上述の事情に鑑み、本発明は半導体装置から剥
離し難いボンディングパッドを提(Jtiすることを目
的としている。
Therefore, in view of the above-mentioned circumstances, an object of the present invention is to provide a bonding pad that is difficult to peel off from a semiconductor device.

〔課題を解決するための手段〕[Means to solve the problem]

上述の目的を達成するため、本発明によるボンディング
パッドにおいては、互いに離間し、半導体装置を構成す
る半導体基板に対して略平行に配置される第1の金属層
および第2の金属層と、この第1および第2の金属層の
相互間においてこれらの双方に接合し、ワイヤボンディ
ング時にボンディングワイヤから伝わる張力に抗して第
1の金属層と第2の金属層との連結を維持しうる程度の
連結強度をもってこれらを相互に連結する複数の連結金
属部とを備えており、第1の金属層はその周囲を覆う絶
縁膜により連結金属部との接合部を除いて覆われ、第2
の金属層はその周囲を覆う絶縁膜によりその外周部か覆
われた構成となっている。
In order to achieve the above object, the bonding pad according to the present invention includes a first metal layer and a second metal layer, which are spaced apart from each other and arranged approximately parallel to a semiconductor substrate constituting a semiconductor device; The extent to which the first and second metal layers are bonded to each other and the connection between the first metal layer and the second metal layer can be maintained against the tension transmitted from the bonding wire during wire bonding. The first metal layer is covered with an insulating film surrounding the first metal layer except for the joints with the connection metal parts, and the second
The outer periphery of the metal layer is covered with an insulating film surrounding the metal layer.

〔作用〕[Effect]

このような構成となっているので、ボンディングパッド
の厚さが従来のものよりも実質的に厚くなり、その剪断
強度が向上する。また、第1および第2の金属層を覆う
絶縁膜がボンディングパッドを剥離しようとする外力に
抗して、それぞれ第1および第2の金属層を半導体装置
側へ押さえ付けるように作用する。
With this configuration, the thickness of the bonding pad is substantially thicker than in the prior art, improving its shear strength. Furthermore, the insulating films covering the first and second metal layers act to press the first and second metal layers toward the semiconductor device, respectively, against external forces that tend to peel off the bonding pads.

なお、本発明は、次のような実験により得られた後述す
る知見に基づき完成されたものである。
The present invention was completed based on the findings described below obtained through the following experiments.

すなわち、第6図に示したように、半導体基板11上に
ボンディングパッド15を形成し、ボンディングパッド
15の外周部をパッシベーション膜17により覆った状
態でボンディングワイヤ18の接続(ボンディング)を
行った場合(同図(a)参照)と、パッシベーション膜
17により覆わない状態でワイヤボンディングを行った
場合(同図(b)および(c)参照)とで、ボンディン
グパッド15の剥離が発生する頻度を比較した。
That is, as shown in FIG. 6, when the bonding pad 15 is formed on the semiconductor substrate 11 and the bonding wire 18 is connected (bonded) with the outer periphery of the bonding pad 15 covered with the passivation film 17. Compare the frequency at which the bonding pad 15 peels off (see (a) in the same figure) and when wire bonding is performed without covering it with the passivation film 17 (see (b) and (c) in the same figure). did.

更に、ボンディングパッド15がパッシベーション膜1
7により覆われていない状態で行った実験は、ボンディ
ングワイヤ18がパッド15からはみ出した場合(同図
(b)参照)と、ワイヤ18がパッド15のほぼ中央部
にボンディングされ、パッド15の端部にかからなかっ
た場合(同図(C)参照)との比較も行った。
Furthermore, the bonding pad 15 is connected to the passivation film 1.
The experiments conducted with the bonding wire 18 not covered by the pad 15 were conducted in two cases: one in which the bonding wire 18 protruded from the pad 15 (see FIG. A comparison was also made with the case in which it did not occur (see figure (C)).

実験の結果、同図(b)に示した状態におけるパッド1
5の剥離発生頻度が最も高く、同図(C)、同図(a)
の順でパッド15の剥離発生頻度は減少した。この結果
から、以下の知見を得ることができた。つまり、同図(
b)の実験結果と同図(c)の実験結果とを比較すると
、同図(c)の場合の剥離発生頻度は、同図(b)の場
合の1/10以下であったことから、同図(b)のよう
にワイヤ18がパッド15の中央部からはずれて端部に
かかると、ワイヤ18に作用する張力によりパッド15
と半導体基板11との間に作用する応力がパッド15の
端部に集中し、そこをきっかけとして剥離が容易に発生
する。従って、剥離発生頻度を減少させるには、ワイヤ
18がパッド15の端部にかからないようにすることが
望ましい。また、同図(b)および(c)の実験で剥離
が生じたボンディングパッドを調べたところ、パッド1
5が部分的にちぎれて剥離したものはなく、どれもバッ
ド全体が剥離していた。このことから、ボンディングパ
ッド自体の剪断強度よりも半導体基板11とボンディン
グバッド15相互間の接着強度の方が小さいことが分っ
た。更に、パッド15の外周部がパッシベーション膜1
7により覆われている場合には(同図(a)参照)、パ
ッド15の中心部からずれた位置にワイヤ18がボンデ
ィングされても、外・周部を覆うパッシベーション膜1
7によりワイヤ18がパッド15の端部に接触すること
か防止される。これにより、ワイヤ18は実質的に同図
(c)と同様の状態でパッドに接続されることとなり、
ボンディングの位置精度があまくでも、パッド15の剥
離発生頻度を減少させることができる。また、パッド1
5の外周部を讃うパッシベーション膜17はパッド15
を剥離しようとする外力に抗してパッド15を基板11
に対して押さえ付ける役割も果たしている。この結果、
同図(c)の場合よりも同図(a)の場合の剥離発生頻
度が減少したのである。
As a result of the experiment, pad 1 in the state shown in FIG.
5 had the highest peeling frequency, as shown in Figures (C) and (A).
The frequency of peeling of the pad 15 decreased in this order. From this result, we were able to obtain the following knowledge. In other words, the same figure (
Comparing the experimental results in b) and the experimental results in figure (c), the frequency of peeling in case of figure (c) was less than 1/10 of that in figure (b). When the wire 18 deviates from the center of the pad 15 and hangs on the end of the pad 15 as shown in FIG.
The stress acting between the pad 15 and the semiconductor substrate 11 is concentrated at the end of the pad 15, and peeling easily occurs there. Therefore, in order to reduce the frequency of peeling, it is desirable to prevent the wire 18 from touching the end of the pad 15. In addition, when we examined the bonding pads that had peeled off in the experiments shown in Figures (b) and (c), we found that pad 1
None of the pads were partially torn and peeled off, but the entire pad was peeled off in all of them. From this, it was found that the adhesive strength between the semiconductor substrate 11 and the bonding pad 15 was smaller than the shear strength of the bonding pad itself. Furthermore, the outer periphery of the pad 15 is covered with the passivation film 1.
7 (see figure (a)), even if the wire 18 is bonded to a position shifted from the center of the pad 15, the passivation film 1 covering the outer and peripheral portion
7 prevents the wire 18 from contacting the end of the pad 15. As a result, the wire 18 is connected to the pad in a state substantially similar to that shown in FIG.
Even if the bonding position accuracy is poor, the frequency of peeling of the pad 15 can be reduced. Also, pad 1
The passivation film 17 covering the outer periphery of the pad 15
The pad 15 is removed from the substrate 11 by resisting the external force that tries to peel it off.
It also plays a role in suppressing the situation. As a result,
The frequency of occurrence of peeling in the case of FIG. 3(a) was lower than that in the case of FIG. 2(c).

なお、同図(d)に同図(a)の実験でパッド15が剥
離した状態を示す。この図から理解されるように、この
場合の剥離はパッド15の剪断と基板11表面からの剥
離が同時に起って生じている。そこで、パッド15の肉
厚を増して剪断強度を高めたところ、パッドの剥離は更
に減少した。
Note that FIG. 3D shows a state in which the pad 15 was peeled off in the experiment shown in FIG. As can be understood from this figure, the peeling in this case occurs due to simultaneous shearing of the pad 15 and peeling from the surface of the substrate 11. Therefore, when the thickness of the pad 15 was increased to increase the shear strength, the peeling of the pad was further reduced.

〔実施例〕〔Example〕

以下、本発明の実施例について第1図〜第4図を参照し
つつ、説明する。
Embodiments of the present invention will be described below with reference to FIGS. 1 to 4.

第1図は、本発明によるボンディングパッドを備えた半
導体装置の一実施例を部分的に示した斜視図である。第
1図に示した半導体装置においては、半導体基板21の
表面に対して略平行に、かつ、互いに離間して形成され
た第1金属層22および第2金属層23と、これら第1
金属層22および第2金属層23の相互間に形成され、
これらを相互に連結する複数の連結金属部25とによっ
てボンディングパッド26が構成されている。
FIG. 1 is a perspective view partially showing an embodiment of a semiconductor device equipped with a bonding pad according to the present invention. In the semiconductor device shown in FIG. 1, a first metal layer 22 and a second metal layer 23 are formed substantially parallel to the surface of a semiconductor substrate 21 and separated from each other, and
formed between the metal layer 22 and the second metal layer 23,
A bonding pad 26 is constituted by a plurality of connecting metal parts 25 that interconnect these parts.

ボンディングパッド26の下層部を構成する第1金属層
22は、半導体基板21の表面にフォトリソグラフィ等
によりパターン形成され、例えばQ、5μmの厚さで、
その平面形状が一辺50〜100μm程度の略正方形に
なるように形成されている。また、第1金属層22は幅
寸法2μm程度の金属配線パターン27と同時に、かつ
、これに連続してパターン形成されており、金属配線パ
ターン27を介して半導体基板21上に形成されている
電子回路に接続される。第1金属層22は、連結金属部
25との接合部を除き、その周囲の半導体基板21表面
および金属配線パターン27と共に層間絶縁膜28によ
り覆われている。したがって、第1金属層22はこれを
覆う層間絶縁膜28により半導体基板21に対して押さ
え付けられることとなる。
The first metal layer 22 constituting the lower layer part of the bonding pad 26 is patterned on the surface of the semiconductor substrate 21 by photolithography or the like, and has a thickness of, for example, Q, 5 μm.
The planar shape is approximately square with a side of about 50 to 100 μm. Further, the first metal layer 22 is patterned simultaneously with and in succession to a metal wiring pattern 27 having a width of about 2 μm, and the electron beams formed on the semiconductor substrate 21 via the metal wiring pattern 27 are patterned. connected to the circuit. The first metal layer 22 is covered with an interlayer insulating film 28 along with the surrounding surface of the semiconductor substrate 21 and the metal wiring pattern 27, except for the joint portion with the connecting metal portion 25. Therefore, the first metal layer 22 is pressed against the semiconductor substrate 21 by the interlayer insulating film 28 covering it.

第2図に複数の連結金属部25の平面形状及びその配置
を示す。複数の連結金属部25は、第1図にも示したよ
うに、層間絶縁膜28により覆われていない部分の第1
金属層22上に互いに離間して形成される。この連結金
属部25の形成はバイアメタルを形成する要領で行うこ
とができる。
FIG. 2 shows the planar shape and arrangement of the plurality of connecting metal parts 25. As shown in FIG.
They are formed on the metal layer 22 to be spaced apart from each other. The connecting metal portion 25 can be formed in the same manner as via metal.

なお、本実施例においては、連結金属部25は第1金属
層22の外周部を除いた領域に形成されている。このた
め、第1金属層22は複数の連結金属部25が形成され
る領域から側方に張り出した張出し部を有していること
になる。
In this embodiment, the connecting metal portion 25 is formed in a region other than the outer peripheral portion of the first metal layer 22. Therefore, the first metal layer 22 has an overhang portion that overhangs laterally from the region where the plurality of connecting metal portions 25 are formed.

そして、ボンディングパッド26の上層部を構成する第
2金属層23は、複数の連結金属部25に接合して連結
金属部25及びその周辺の層間絶縁膜28上にパターン
形成される。第1図に示した実施例においては、第2金
属層23は第1金属層22とほぼ同一の形状および大き
さで形成されており、第2金属層23も第1金属層22
と同様に、複数の連結金属部25が形成されている領域
から側方に張り出した張出し部を有している。そして、
第2金属層23はその外周部がその周囲の層間絶縁膜2
5と共にパッシベーション膜30により覆われた構造と
なっている。したがって、第2金属層23はその外周部
を覆うパッシベーション膜30により半導体基板21側
へ押さえず・jけられることとなる。パッシベーション
膜30には第2金属層23の上面を露出させるための開
口部30aが形成されており、第2金属層23の露出し
た部分に対してボンディングワイヤが接続されるように
なっている。
The second metal layer 23 constituting the upper layer of the bonding pad 26 is bonded to the plurality of connection metal parts 25 and is patterned on the connection metal parts 25 and the interlayer insulating film 28 around the connection metal parts 25 . In the embodiment shown in FIG. 1, the second metal layer 23 is formed to have substantially the same shape and size as the first metal layer 22, and the second metal layer 23 is also similar to the first metal layer 22.
Similarly, it has an overhanging portion that overhangs laterally from the region where the plurality of connecting metal portions 25 are formed. and,
The second metal layer 23 has its outer periphery covered by the surrounding interlayer insulating film 2.
5 is covered with a passivation film 30. Therefore, the second metal layer 23 is not pressed toward the semiconductor substrate 21 by the passivation film 30 covering the outer periphery of the second metal layer 23 . An opening 30a is formed in the passivation film 30 to expose the upper surface of the second metal layer 23, and a bonding wire is connected to the exposed portion of the second metal layer 23.

なお、複数の連結金属部25は、第2金属層23上への
ワイヤボンディング時にボンディングワイヤから伝わる
張力に抗して第1金属層22と第2金属層23との連結
を維持し得る程度の連結強度を満足するように形成され
る。連結金属部25に要求される連結強度は、第2金属
層23の厚さやパッシベーション膜30の厚さ等により
異なるが、連結金属部25と第1金属層22の総接合面
積及び連結金属部25と第2金属層23の総接合面積を
それぞれ第2金属層23の露出面積(開口部30aの開
口面積)の少なくとも40%以上とすることにより、満
足される。
Note that the plurality of connecting metal parts 25 are made of a material that can maintain the connection between the first metal layer 22 and the second metal layer 23 against the tension transmitted from the bonding wire during wire bonding onto the second metal layer 23. Formed to satisfy connection strength. The connection strength required for the connection metal part 25 varies depending on the thickness of the second metal layer 23, the thickness of the passivation film 30, etc. This is achieved by making the total bonding area of the second metal layer 23 and the second metal layer 23 at least 40% or more of the exposed area of the second metal layer 23 (opening area of the opening 30a).

また、連結金属部25はパッシベーション膜30に形成
された開口部30aの外周長さの少なくとも約40%を
その接合領域内に含むように形成される。すなわち、該
外周長の少なくとも40%が連結金属部25上に存在す
るように形成される。これは、ワイヤボンディング時に
開口部30aの外周部に剪断力が作用するが、この剪断
力に第2金属層23が絶え得るようにするためである。
Further, the connecting metal portion 25 is formed so that at least about 40% of the outer circumferential length of the opening 30a formed in the passivation film 30 is included in its bonding region. That is, at least 40% of the outer circumference is formed on the connecting metal part 25. This is to allow the second metal layer 23 to resist the shearing force that acts on the outer periphery of the opening 30a during wire bonding.

上述した本発明によるボンディングパッドの剥離発生頻
度を調査するため次のような実験を行った。実験はパッ
シベーション膜30を連結金属部25と第2金属層23
の接合領域外周から第2金属層23の中心側に寸法Bだ
け迫り出させて形成した場合(第3図(a)参照)と、
逆に外側に寸法Bだけ後退させて形成した場合(同図(
b)参照)とに分け、それぞれ5000回及び1000
回のワイヤボンディングを超音波併用熱圧着法により行
った。
In order to investigate the frequency of peeling of the bonding pad according to the present invention described above, the following experiment was conducted. In the experiment, the passivation film 30 was connected to the metal part 25 and the second metal layer 23.
When formed by protruding from the outer periphery of the bonding region toward the center of the second metal layer 23 by a dimension B (see FIG. 3(a)),
On the other hand, if it is formed by retracting the dimension B outward (see figure (
b)) and 5,000 times and 1,000 times, respectively.
The second wire bonding was performed using a thermocompression method combined with ultrasonic waves.

なお、実験にあたり、半導体基板21としてGaAs基
板を用い、第1金属層22としてTi(100nIII
) /P t (150nm) /Au (400nm
)の多層金属を真空蒸着により形成した。また、層間絶
縁膜28としてプラズマCVD法により600 nmの
厚さでSiN膜を形成し、パッシベーション膜30とし
て500nlTlの厚さでSiN膜を形成した。更に、
第2金属層23としてTt(100nm)/Pt (1
50nm)/Au (700nm)の多層金属を、連結
金属部25として厚さ750 n11のAu層をそれぞ
れ真空蒸着により形成した。
In the experiment, a GaAs substrate was used as the semiconductor substrate 21, and Ti (100nIII) was used as the first metal layer 22.
) /P t (150nm) /Au (400nm
) was formed by vacuum evaporation. Further, as the interlayer insulating film 28, a SiN film was formed with a thickness of 600 nm by plasma CVD, and as the passivation film 30, a SiN film was formed with a thickness of 500 nlTl. Furthermore,
As the second metal layer 23, Tt (100 nm)/Pt (1
50 nm)/Au (700 nm), and an Au layer having a thickness of 750 nm was formed as the connecting metal part 25 by vacuum evaporation.

この実験の結果、第3図(b)の構造では1000個の
ボンディングパッドのうち7個に剥離が生じた。これに
対し、同図(a)の構造では5000個のボンディング
パッドに剥離は全く生じなかった。第3図(b)の構造
で剥離が生じたボンディングパッドについて調べたとこ
ろ、パッシベーション膜30により覆われていない部分
で第2金属層25と層間絶縁膜28との界面剥離をきっ
かけに、パッド26の剥離が生じていることが推察され
た。したがって、この様な剥離を防止するため、連結金
属部25と第2金属層23の接合領域外周からパッシベ
ーション膜30を第2金属層23の中心側に迫り出させ
て形成することが好ましい。
As a result of this experiment, peeling occurred in 7 out of 1000 bonding pads in the structure shown in FIG. 3(b). On the other hand, in the structure shown in FIG. 5(a), no peeling occurred at all among the 5,000 bonding pads. When we investigated the bonding pad in which peeling occurred in the structure shown in FIG. It was inferred that peeling had occurred. Therefore, in order to prevent such peeling, it is preferable to form the passivation film 30 so as to protrude toward the center of the second metal layer 23 from the outer periphery of the bonding region between the connecting metal part 25 and the second metal layer 23.

また、比較のためパッシベーション膜30を形成しなか
った場合(第4図(a)参照)と、更に複数の連結金属
部25を形成せず、その代わりに単一の連結金属部33
を第1金属層22及び第2金属層23の中央部に形成し
た場合(同図(b)参照)とについて、第3図の場合と
同様の実験を行った。この結果、第4図(b)の構造で
は1000個のボンディングパッドのうち58個に剥離
が生じたのに対し、同図(a)の構造では1000個中
17個まで剥離頻度が減少した。このことから、複数の
連結金属部25相互間の第1金属層22を覆う層間絶縁
膜28により、ボンディングパッドの押さえ付は作用が
有効に発揮されていることが判明した。
For comparison, a case in which no passivation film 30 is formed (see FIG. 4(a)) and a case in which a plurality of connecting metal parts 25 are not formed and a single connecting metal part 33 is formed instead.
The same experiment as in the case of FIG. 3 was conducted for the case where the metal layer was formed at the center of the first metal layer 22 and the second metal layer 23 (see FIG. 3B). As a result, in the structure shown in FIG. 4(b), 58 out of 1000 bonding pads were peeled off, whereas in the structure shown in FIG. 4(a), the peeling frequency was reduced to 17 out of 1000. From this, it was found that the interlayer insulating film 28 covering the first metal layer 22 between the plurality of connecting metal parts 25 effectively pressed down the bonding pad.

したがって、ボンディングパッドの剥離を防lニするた
めには、パッシベーション膜30や層間絶縁膜28等の
絶縁膜によりボンディングパッドを半導体基板に対して
押さえ付けることが有効であり、しかも、複数の連結金
属部25相互間の第1金属層22を層間絶縁膜28によ
り覆うことが有効である。そして、第1図ないし第3図
に示した実施例のように、半導体基板表面に垂直な方向
における複数箇所で絶縁膜によりボンディングパッドを
押さえ付けることが好ましい。
Therefore, in order to prevent the bonding pad from peeling off, it is effective to press the bonding pad against the semiconductor substrate with an insulating film such as the passivation film 30 or the interlayer insulating film 28. It is effective to cover the first metal layer 22 between the portions 25 with an interlayer insulating film 28. As in the embodiments shown in FIGS. 1 to 3, it is preferable to press the bonding pad with an insulating film at a plurality of locations in a direction perpendicular to the surface of the semiconductor substrate.

なお、ボンディングパッド底面の接若強度について着目
すると、第1図ないし第3図に示した実施例では、ボン
ディングパッド底面は半導体基板表面に接合されている
。これに対し、第5図に示した従来のボンディングパッ
ド底面は絶縁膜に接合されている。ボンディングパッド
に用いられる金属は、通常、絶縁膜に接合された場合に
比べると半導体基板に接合された場合の方がより高い接
合強度を得ることができる。本発明においては、半導体
基板上に多層構造の配線が形成される場合であっても、
ボンディングパッド底面を半導体基板に接合させること
が可能であり、絶縁膜に底面が接合される従来のボンデ
ィングパッドよりモ高い接合強度をその底面に得ること
が可能である。
Note that with regard to the attachment strength of the bottom surface of the bonding pad, in the embodiments shown in FIGS. 1 to 3, the bottom surface of the bonding pad is bonded to the surface of the semiconductor substrate. In contrast, the bottom surface of the conventional bonding pad shown in FIG. 5 is bonded to an insulating film. Metals used for bonding pads can usually achieve higher bonding strength when bonded to a semiconductor substrate than when bonded to an insulating film. In the present invention, even when multilayer wiring is formed on a semiconductor substrate,
It is possible to bond the bottom surface of the bonding pad to the semiconductor substrate, and it is possible to obtain bonding strength on the bottom surface that is higher than that of a conventional bonding pad in which the bottom surface is bonded to an insulating film.

なお、上述した絶縁膜による押さえ付は作用によりボン
ディングパッドの剥離を十分に防止できる場合には、ボ
ンディングパッド底面の接合強度について考慮する必要
がないので、この場合には第1金属層22を多層配線の
層間絶縁股上に形成してもよい。
Note that if the above-mentioned pressing by the insulating film can sufficiently prevent the bonding pad from peeling off, there is no need to consider the bonding strength of the bottom surface of the bonding pad. It may also be formed on the interlayer insulation crotch of the wiring.

また、上述した実施例においては、第1金属層22に金
属配線パターン27が接続されているが、層間絶縁膜2
8上に形成される金属配線パターンが第2金属層23に
接続され、これによりボンディングパッド26が半導体
基板上の71i子回路に接続されていてもよい。
Furthermore, in the embodiment described above, the metal wiring pattern 27 is connected to the first metal layer 22, but the interlayer insulating film 2
A metal wiring pattern formed on the semiconductor substrate 8 may be connected to the second metal layer 23, thereby connecting the bonding pad 26 to the child circuit 71i on the semiconductor substrate.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によればボンディングパッ
ドの厚さを従来のものよりも実質的に厚くすることがで
き、その剪断強度が向上する。また、第1および第2の
金属層を覆う絶縁膜がボンディングパッドを剥離しよう
とする外力に抗して、それぞれ第1および第2の金属層
を半導体装置側へ押さえ付けるように作用する。したが
って、半導体装置から剥離し難いボンディングパッドを
得ることができる。
As explained above, according to the present invention, the thickness of the bonding pad can be made substantially thicker than that of the conventional bonding pad, and its shear strength is improved. Furthermore, the insulating films covering the first and second metal layers act to press the first and second metal layers toward the semiconductor device, respectively, against external forces that tend to peel off the bonding pads. Therefore, a bonding pad that is difficult to peel off from a semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明によるボンディングパッドの一実施例を
示した斜視図、第2図は連結金属部の配置を示した図、
第3図及び第4図はボンディングパッドの剥離実験に用
いたボンディングパッドの断面図、第5図は従来のボン
ディングパッドを示した斜視図、第6図はボンディング
パッドの剥離メカニズムを調べるために行った実験の様
子を示した図である。 21・・・半導体基板、22・・・第1金属層、23・
・・第2金属層、25・・・連結金属部、26・・・ボ
ンディングパッド、27・・・金属配線パターン、28
・・・層間絶縁膜、30・・・パッシベーション膜、3
0a・・・開口部。 実験に用℃\たボンブイシフ大・ソド 第3図
FIG. 1 is a perspective view showing an embodiment of the bonding pad according to the present invention, FIG. 2 is a view showing the arrangement of the connecting metal parts,
Figures 3 and 4 are cross-sectional views of the bonding pad used in the bonding pad peeling experiment, Figure 5 is a perspective view of a conventional bonding pad, and Figure 6 is a cross-sectional view of the bonding pad used in the bonding pad peeling experiment. FIG. 21... Semiconductor substrate, 22... First metal layer, 23...
... Second metal layer, 25... Connection metal part, 26... Bonding pad, 27... Metal wiring pattern, 28
...Interlayer insulating film, 30... Passivation film, 3
0a...opening. Figure 3 of Bonbuishifu University and Sodo used for experiments.

Claims (1)

【特許請求の範囲】  半導体装置上に形成され、半導体装置上の配線パター
ンに接続されると共に、ボンディングワイヤが接続され
るボンディングパッドであって、互いに離間し、前記半
導体装置を構成する半導体基板表面に対して略平行に配
置される第1の金属層および第2の金属層と、 前記第1および第2の金属層の相互間においてこれらの
双方に接合し、ワイヤボンディング時にボンディングワ
イヤから伝わる張力に抗して前記第1の金属層と前記第
2の金属層との連結を維持しうる程度の連結強度をもっ
てこれらを相五に連結する複数の連結金属部とを備え、 前記第1の金属層はその周囲を覆う絶縁膜により前記連
結金属部との接合部を除いて覆われており、 前記第2の金属層はその周囲を覆う絶縁膜によりその外
周部が覆われていることを特徴とするボンディングパッ
ド。
[Scope of Claims] Bonding pads formed on a semiconductor device, connected to wiring patterns on the semiconductor device, and to which bonding wires are connected, the pads being spaced apart from each other and on the surface of the semiconductor substrate constituting the semiconductor device. a first metal layer and a second metal layer that are arranged substantially parallel to each other; and a first metal layer and a second metal layer that are bonded to each other between the first and second metal layers, and that are bonded to each other to prevent tension transmitted from the bonding wire during wire bonding. a plurality of connecting metal parts that connect the first metal layer and the second metal layer in a phase-like manner with a connection strength that is sufficient to maintain the connection between the first metal layer and the second metal layer; The second metal layer is covered with an insulating film surrounding the layer except for the joint with the connecting metal part, and the second metal layer has an outer peripheral part covered with an insulating film surrounding the second metal layer. bonding pad.
JP2106915A 1990-04-23 1990-04-23 Bonding pad Pending JPH045843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2106915A JPH045843A (en) 1990-04-23 1990-04-23 Bonding pad

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2106915A JPH045843A (en) 1990-04-23 1990-04-23 Bonding pad

Publications (1)

Publication Number Publication Date
JPH045843A true JPH045843A (en) 1992-01-09

Family

ID=14445725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2106915A Pending JPH045843A (en) 1990-04-23 1990-04-23 Bonding pad

Country Status (1)

Country Link
JP (1) JPH045843A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335851A (en) * 2006-05-15 2007-12-27 Matsushita Electric Ind Co Ltd Circuit board, method of fabricating same, and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335851A (en) * 2006-05-15 2007-12-27 Matsushita Electric Ind Co Ltd Circuit board, method of fabricating same, and semiconductor device

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