JPH04348047A - Semiconductor integrated circuit electrode - Google Patents
Semiconductor integrated circuit electrodeInfo
- Publication number
- JPH04348047A JPH04348047A JP3149948A JP14994891A JPH04348047A JP H04348047 A JPH04348047 A JP H04348047A JP 3149948 A JP3149948 A JP 3149948A JP 14994891 A JP14994891 A JP 14994891A JP H04348047 A JPH04348047 A JP H04348047A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- integrated circuit
- semiconductor integrated
- bonding
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 229910052782 aluminium Inorganic materials 0.000 abstract description 56
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- 229920005591 polysilicon Polymers 0.000 abstract description 15
- 230000007547 defect Effects 0.000 abstract description 4
- 239000004411 aluminium Substances 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 28
- 238000000034 method Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、半導体集積回路電極
に関し、特に、超音波熱圧着等の手段によってボンディ
ングボールが圧接して接合される半導体集積回路電極に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit electrode, and more particularly to a semiconductor integrated circuit electrode to which a bonding ball is pressed and bonded by means such as ultrasonic thermocompression bonding.
【０００２】0002
【従来の技術】図４は、従来の半導体集積回路電極にワ
イヤ先端部のボンディングボールを接合した状態を示す
断面図である。2. Description of the Related Art FIG. 4 is a sectional view showing a state in which a bonding ball at the tip of a wire is bonded to a conventional semiconductor integrated circuit electrode.
【０００３】図において、１は半導体基板、２はフィー
ルド酸化膜（絶縁膜）、３は第１のアルミ電極、４は層
間膜（第２の絶縁膜）、５は第２のアルミ電極、５ａは
第２のアルミ電極５における表面、６はパッシベーショ
ン膜、７はボンディングボール、８はボンディングボー
ルである。In the figure, 1 is a semiconductor substrate, 2 is a field oxide film (insulating film), 3 is a first aluminum electrode, 4 is an interlayer film (second insulating film), 5 is a second aluminum electrode, 5a is the surface of the second aluminum electrode 5, 6 is a passivation film, 7 is a bonding ball, and 8 is a bonding ball.
【０００４】次に、上記半導体集積回路電極の形成工程
について説明する。先ず、半導体基板１上にフィールド
酸化膜（絶縁膜）２を形成する。次に、フィールド酸化
２上にアルミ層を形成し、写真製版，エッチング技術を
用いて第１のアルミ電極３を形成する。次に、基板１の
全面にＳｉＯ２ による絶縁膜を形成した後、写真製版
，エッチング技術を用いて第１のアルミ電極３の表面を
覆う絶縁膜を除去して層間膜４を形成する。次に、第１
のアルミ電極３と層間膜４との表面を覆うようにアルミ
層を形成した後、写真製版，エッチング技術により第２
のアルミ電極５を形成する。そして、最後に、ＳｉＮ膜
を基板１の全面に形成した後、通常の写真製版，エッチ
ング技術により第２のアルミ電極５上に形成されたＳｉ
Ｎ膜を除去して、パッシベーション膜６を形成し、半導
体集積回路電極が形成される。Next, a process for forming the semiconductor integrated circuit electrode will be explained. First, a field oxide film (insulating film) 2 is formed on a semiconductor substrate 1. Next, an aluminum layer is formed on the field oxide 2, and a first aluminum electrode 3 is formed using photolithography and etching techniques. Next, after forming an insulating film of SiO2 on the entire surface of the substrate 1, the insulating film covering the surface of the first aluminum electrode 3 is removed using photolithography and etching techniques to form an interlayer film 4. Next, the first
After forming an aluminum layer to cover the surfaces of the aluminum electrode 3 and the interlayer film 4, a second layer is formed using photolithography and etching techniques.
An aluminum electrode 5 is formed. Finally, after forming a SiN film on the entire surface of the substrate 1, a SiN film is formed on the second aluminum electrode 5 by ordinary photolithography and etching techniques.
The N film is removed, a passivation film 6 is formed, and a semiconductor integrated circuit electrode is formed.
【０００５】次に、以上のようにして形成された電極の
最上面、即ち、第２のアルミ電極５の表面に、ボンディ
ングワイヤ８の先端部に形成された真球状のボンディン
グボール７を適当な温度，荷重の条件下に超音波併用に
より圧接すると、ボンディングワイヤ７と第２のアルミ
電極５との接合部が形成される。Next, a spherical bonding ball 7 formed at the tip of the bonding wire 8 is placed on the top surface of the electrode formed as described above, that is, on the surface of the second aluminum electrode 5. When the bonding is performed under temperature and load conditions using ultrasonic waves, a joint between the bonding wire 7 and the second aluminum electrode 5 is formed.
【０００６】このように、従来の半導体集積回路におけ
る電極とホンディングワイヤ８との接続は、半導体集積
回路電極の最上層の第２のアルミ電極５の平坦な表面５
ａに、ボンディングワイヤ８の先端に形成されたボンデ
ィングボール７を適当な温度，荷重の条件下で超音波併
用して圧接し、前記第２のアルミ電極の平坦な表面５ａ
とボンディングボール７との接合部を形成することによ
り行われていた。As described above, the connection between the electrode and the bonding wire 8 in the conventional semiconductor integrated circuit is achieved through the flat surface 5 of the second aluminum electrode 5 on the uppermost layer of the semiconductor integrated circuit electrode.
The bonding ball 7 formed at the tip of the bonding wire 8 is pressed into contact with the tip of the bonding wire 8 using ultrasonic waves under appropriate temperature and load conditions to form a flat surface 5a of the second aluminum electrode.
This was done by forming a joint between the bonding ball 7 and the bonding ball 7.
【０００７】[0007]
【発明が解決しようとする課題】ところで、半導体集積
回路装置の小型化にともない、電極自体も縮小して形成
することがある。しかしながら、電極を縮小して形成す
るとワイヤが接続される電極表面、即ち、上記の半導体
集積回路電極における第２のアルミ電極５の電極表面５
ａも自ずと小さくなり、その結果、ボンディングボール
７と第２のアルミ電極５の表面５ａとの接触する面積が
減少して双方の接着力が低下し、樹脂封止の際や保管時
の急激な温度変化によってボンディングボールはがれ等
の不具合を発生するようになり、半導体集積回路の信頼
性を低下させる等の問題点を生じさせていた。By the way, as semiconductor integrated circuit devices become smaller, the electrodes themselves are sometimes formed in a smaller size. However, if the electrode is reduced in size, the electrode surface to which the wire is connected, that is, the electrode surface 5 of the second aluminum electrode 5 in the semiconductor integrated circuit electrode,
a also naturally becomes smaller, and as a result, the contact area between the bonding ball 7 and the surface 5a of the second aluminum electrode 5 decreases, reducing the adhesive strength between the two, and causing sudden damage during resin sealing and storage. Temperature changes have caused problems such as peeling of the bonding balls, resulting in problems such as lowering the reliability of semiconductor integrated circuits.
【０００８】この発明は、上記のような問題点を解消す
るためになされたもので、ボンディングボールの電極部
への接着力が増し、電極部を縮小して形成した場合にも
、ボンディングボールはがれ等の不具合の発生を抑制す
ることができる半導体集積回路電極を得ることを目的と
している。The present invention was made to solve the above-mentioned problems, and the adhesive force of the bonding ball to the electrode part is increased, so that even when the electrode part is reduced in size, the bonding ball does not peel off. The object of the present invention is to obtain a semiconductor integrated circuit electrode that can suppress the occurrence of such defects.
【０００９】[0009]
【課題を解決するための手段】この発明にかかる半導体
集積回路電極は、半導体基板上に形成された絶縁膜と該
絶縁膜上に形成された少なくとも一層の金属層を有する
電極において、前記絶縁膜と前記少なくとも一層の金属
層との間に突起状電極を設け、前記金属層の最上層の表
面になめらかな凹凸を形成したものである。Means for Solving the Problems A semiconductor integrated circuit electrode according to the present invention includes an insulating film formed on a semiconductor substrate and at least one metal layer formed on the insulating film. A protruding electrode is provided between the metal layer and the at least one metal layer, and smooth irregularities are formed on the surface of the uppermost layer of the metal layer.
【００１０】更に、この発明にかかる半導体集積回路は
、半導体基板上に形成された絶縁膜と該絶縁膜上に形成
された複数の金属層とを有する電極部において、前記絶
縁膜上に形成された複数の金属層の最上層を除く他の一
層を不連続な層構造に形成し、前記金属層の最上層の表
面になめらかな凹凸を形成したものである。Furthermore, in the semiconductor integrated circuit according to the present invention, in the electrode portion having an insulating film formed on a semiconductor substrate and a plurality of metal layers formed on the insulating film, a plurality of metal layers formed on the insulating film are formed on the insulating film. The plurality of metal layers except for the top layer are formed in a discontinuous layer structure, and smooth irregularities are formed on the surface of the top layer of the metal layers.
【００１１】[0011]
【作用】この発明においては、半導体集積回路電極を構
成する金属層の最上層の表面になめらかな凹凸を形成し
たので、ボンディングボールを前記金属層の表面に圧接
して接合する際、ボンディングボールと金属層との接触
面積か増大し、これにより、接合部における接着力を高
めることができる。[Operation] In this invention, smooth irregularities are formed on the surface of the uppermost metal layer constituting the semiconductor integrated circuit electrode, so that when the bonding ball is pressure-contacted to the surface of the metal layer and bonded, the bonding ball and The contact area with the metal layer is increased, thereby increasing the adhesive force at the joint.
【００１２】0012
【実施例】以下、この発明の一実施例を図について説明
する。図１は、この発明の一実施例による半導体集積回
路電極にボンディングボール７を圧接して接合した接合
部を示す断面図であり、図において、１は半導体基板、
２はフィールド酸化膜としての絶縁膜、３は第１のアル
ミ電極、４は層間膜としての第２の絶縁層、５は第２の
アルミ電極、５ａは第２のアルミ電極５の表面、６はパ
ッシベーション膜としての絶縁膜、７はボンディングボ
ール、８はボンディングワイヤ、９はフィールド酸化膜
２上に形成された突起状のポリシリコン電極である。
尚、図中、図４と同一符号は同一或いは相当する部分を
示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a bonded part in which a bonding ball 7 is pressed into contact with a semiconductor integrated circuit electrode according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate;
2 is an insulating film as a field oxide film, 3 is a first aluminum electrode, 4 is a second insulating layer as an interlayer film, 5 is a second aluminum electrode, 5a is the surface of the second aluminum electrode 5, 6 7 is an insulating film as a passivation film, 7 is a bonding ball, 8 is a bonding wire, and 9 is a protruding polysilicon electrode formed on the field oxide film 2. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding parts.
【００１３】次に、上記電極部の形成工程を説明する。
図３は、図１に示す電極部の形成工程を示す工程断面図
であり、先ず、半導体基板１上にＳｉＯ２ からなるフ
ィールド酸化膜２を形成する。次に、該フィールド酸化
膜２上にＣＶＤ法等によりポリシリコンを堆積し、その
上にレジストを塗布し、露光，現像を行ってレジストパ
ターンを形成する。そして、該レジストパターンをマス
クとしたエッチングにより不要なポリシリコンを除去し
、更に、不要なレジストを除去して図３（ａ） に示す
ポリシリコン電極９を形成する。Next, the process of forming the electrode portion will be explained. FIG. 3 is a cross-sectional view showing the process of forming the electrode section shown in FIG. 1. First, a field oxide film 2 made of SiO2 is formed on the semiconductor substrate 1. Next, polysilicon is deposited on the field oxide film 2 by CVD or the like, a resist is applied thereon, and exposed and developed to form a resist pattern. Then, unnecessary polysilicon is removed by etching using the resist pattern as a mask, and further unnecessary resist is removed to form a polysilicon electrode 9 shown in FIG. 3(a).
【００１４】次に、図３（ｂ） に示すように、基板１
の全面にアルミをスパッタ蒸着してアルミ層を形成し、
通常の写真製版，エッチング技術によりポリシリコン電
極９を覆うように第１のアルミ電極３を形成する。続い
て、図３（ｃ） に示すように、ＳｉＯ２ からなる絶
縁膜を基板１の全面に蒸着し、通常の写真製版，エッチ
ング技術により前記第１のアルミ電極３上に形成された
絶縁膜を除去して層間膜４を形成する。Next, as shown in FIG. 3(b), the substrate 1
Form an aluminum layer by sputter-depositing aluminum on the entire surface of the
The first aluminum electrode 3 is formed to cover the polysilicon electrode 9 using ordinary photolithography and etching techniques. Subsequently, as shown in FIG. 3(c), an insulating film made of SiO2 is deposited on the entire surface of the substrate 1, and the insulating film formed on the first aluminum electrode 3 is removed by ordinary photolithography and etching techniques. The interlayer film 4 is then removed.
【００１５】次に、図３（ｄ） に示すように、前記第
１のアルミ電極３と前記層間膜４を覆うようにスパッタ
蒸着してアルミ層を形成し、通常の写真製版，エッチン
グ技術により第２のアルミ電極５を形成する。そして、
最後に図３（ｅ） に示すように、基板１の全面にＳｉ
Ｎを蒸着し、通常の写真製版，エッチング技術により前
記第２のアルミ電極５上に形成されたＳｉＮ膜を除去し
てパッシベーション膜６を形成し、電極が完成する。こ
こで、以上のようにして形成された電極は最上層の第２
のアルミ電極５の表面５ａになめらかな凹凸が形成され
ている。Next, as shown in FIG. 3(d), an aluminum layer is formed by sputter deposition so as to cover the first aluminum electrode 3 and the interlayer film 4, and is then etched using ordinary photolithography and etching techniques. A second aluminum electrode 5 is formed. and,
Finally, as shown in Figure 3(e), Si is deposited on the entire surface of the substrate 1.
N is vapor-deposited, and the SiN film formed on the second aluminum electrode 5 is removed by ordinary photolithography and etching techniques to form a passivation film 6, thereby completing the electrode. Here, the electrode formed as above is the second layer of the uppermost layer.
Smooth irregularities are formed on the surface 5a of the aluminum electrode 5.
【００１６】次に、上記得られた第２のアルミ電極５の
表面５ａに、Ａｕからなるボンディングワイヤ８の先端
を溶融して形成した真球状のボンディングボール７を適
当な温度，荷重の条件下で超音波併用して圧接して双方
が接合する。この時、ボンディングボール７と第２のア
ルミ電極５の表面５ａの接合部は従来に比べて広い接触
面に接合されており、これによって、接合部における第
２のアルミ電極５の表面５ａとボンディングボール７と
の接着力を向上することができる。Next, a true spherical bonding ball 7 formed by melting the tip of a bonding wire 8 made of Au is placed on the surface 5a of the second aluminum electrode 5 obtained above under appropriate temperature and load conditions. Both parts are joined together by pressure welding using ultrasonic waves. At this time, the bonding portion between the bonding ball 7 and the surface 5a of the second aluminum electrode 5 is bonded to a wider contact surface than in the past. The adhesive force with the ball 7 can be improved.
【００１７】このような本実施例による半導体集積回路
電極は、フィールド酸化膜２上に形成された突起状のポ
リシリコン電極９と、該ポリシリコン電極９を覆うよう
に形成された第１のアルミ電極３と第２のアルミ電極５
とを備えているので、第２のアルミ電極５の表面５ａに
はなめらかな凹凸が形成され、ボンディングボール７を
第２のアルミ電極５の表面５ａに接合する際の接触面が
拡大し、ボンディングボールはがれが等の不具合が減少
する。The semiconductor integrated circuit electrode according to this embodiment has a protruding polysilicon electrode 9 formed on the field oxide film 2, and a first aluminum electrode formed to cover the polysilicon electrode 9. Electrode 3 and second aluminum electrode 5
Since smooth irregularities are formed on the surface 5a of the second aluminum electrode 5, the contact surface when bonding the bonding ball 7 to the surface 5a of the second aluminum electrode 5 is expanded, and the bonding Problems such as ball peeling are reduced.
【００１８】尚、上記実施例におけるポリシリコン電極
９の形成は、ウエハプロセス内における半導体基板１上
の図示しない他の領域にポリシリコンによるゲート酸化
膜等を形成する際、レジストパターンのパターン制御を
行って上記ゲート酸化膜と同時に形成したものであり、
従来からのウエハプロセスに新たな工程を追加すること
なく突起状の電極を形成することができる。The formation of the polysilicon electrode 9 in the above embodiment is performed by controlling the pattern of the resist pattern when forming a polysilicon gate oxide film or the like on other regions (not shown) on the semiconductor substrate 1 during the wafer process. It was formed at the same time as the gate oxide film,
Protruding electrodes can be formed without adding any new steps to conventional wafer processes.
【００１９】また、上記実施例ではポリシリコンによっ
て突起状の電極を形成したが、他の酸化物から突起状の
電極を形成しても、上記実施例と同様の効果を奏する。Further, in the above embodiment, the protruding electrodes were formed from polysilicon, but the same effects as in the above embodiments can be obtained even if the protruding electrodes are formed from other oxides.
【００２０】次に、この発明の第２の実施例を図につい
て説明する。図２は、本発明の第２の実施例による半導
体集積回路電極にボンディングボール７を圧接して接続
したその接合部を示す断面図であり、図において、１は
半導体基板、２はフィールド酸化膜としての絶縁膜、３
は第１のアルミ電極、４は層間膜としての第２の絶縁層
、５は第２のアルミ電極、５ａは第２のアルミ電極５の
表面、６はパッシベーション膜、７はボンディングボー
ル、８はボンディングワイヤである。Next, a second embodiment of the present invention will be explained with reference to the drawings. FIG. 2 is a cross-sectional view showing a bonded portion where a bonding ball 7 is pressed and connected to a semiconductor integrated circuit electrode according to a second embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a field oxide film. Insulating film as 3
is the first aluminum electrode, 4 is the second insulating layer as an interlayer film, 5 is the second aluminum electrode, 5a is the surface of the second aluminum electrode 5, 6 is the passivation film, 7 is the bonding ball, 8 is the It is a bonding wire.
【００２１】本実施例による電極は、前述した実施例に
おける電極の形成工程において突起状のポリシリコン電
極を形成せず、第１のアルミ電極を形成する際に第１の
アルミ電極を不連続な層構造に形成しており、この第１
のアルミ電極３を覆うように形成した第２のアルミ電極
５のの表面５ａには滑らかな凹凸が形成されている。In the electrode according to this example, the protruding polysilicon electrode was not formed in the electrode forming process in the above-described example, and the first aluminum electrode was formed discontinuously when forming the first aluminum electrode. It is formed in a layered structure, and this first
Smooth irregularities are formed on the surface 5a of the second aluminum electrode 5 formed to cover the aluminum electrode 3.
【００２２】また、電極とボンディングワイヤとの接続
は、前述した実施例と同様に第２のアルミ電極５の表面
５ａに、Ａｕからなるボンディングワイヤ８の先端を溶
融して得られた真球状のボンディングボール７を適当な
温度，荷重の条件下で超音波併用して圧接し、電極とボ
ンディグワイヤ８の接合が行われる。そして、ボンディ
ングボール７と第２のアルミ電極５の表面５ａの接合部
は広い接触面にて接合されて接合部の接着力が向上する
。Further, the connection between the electrode and the bonding wire is made by melting the tip of the bonding wire 8 made of Au onto the surface 5a of the second aluminum electrode 5, in the same way as in the above-mentioned embodiment. The electrode and the bonding wire 8 are bonded by pressing the bonding ball 7 together with ultrasonic waves under appropriate temperature and load conditions. The bonding ball 7 and the surface 5a of the second aluminum electrode 5 are bonded together over a wide contact surface, and the adhesive strength of the bonding portion is improved.
【００２３】このような本実施例による半導体集積回路
電極では、フィールド酸化膜２上に不連続な層構造に形
成された第１のアルミ電極３と、第１のアルミ電極３を
覆うように形成された第２のアルミ電極５を備えている
ので、第２のアルミ電極５の表面５ａにはなめらかな凹
凸が形成され、ボンディングボール８は広い接触面にて
第２のアルミ電極５の表面５ａに接合されるので、ボン
ディングボールはがれ等の不具合が減少し、装置自体の
信頼性が向上する。In the semiconductor integrated circuit electrode according to this embodiment, the first aluminum electrode 3 is formed in a discontinuous layer structure on the field oxide film 2, and the first aluminum electrode 3 is formed to cover the first aluminum electrode 3. Since the second aluminum electrode 5 is provided with a smooth surface 5a, smooth irregularities are formed on the surface 5a of the second aluminum electrode 5, and the bonding ball 8 has a wide contact surface with the surface 5a of the second aluminum electrode 5. Since the bonding balls are bonded to each other, problems such as peeling of the bonding balls are reduced, and the reliability of the device itself is improved.
【００２４】[0024]
【発明の効果】以上のように、この発明にかかる半導体
集積回路によれば、電極部の最上層になめらかな凹凸が
形成されているので、金属層の表面と接合されるボンデ
ィングボールの表面との接合面が拡大し、その結果、接
合部におけるの接着力が向上してボンディングボールは
がれ等の不具合が低減された信頼性の高い半導体集積回
路を得ることができる効果がある。As described above, according to the semiconductor integrated circuit according to the present invention, smooth irregularities are formed on the uppermost layer of the electrode portion, so that the surface of the bonding ball that is bonded to the surface of the metal layer is The bonding surface is enlarged, and as a result, the adhesive force at the bonding portion is improved, and a highly reliable semiconductor integrated circuit with reduced defects such as bonding ball peeling can be obtained.
【図１】この発明の一実施例による半導体集積回路の電
極部にボンディングワイヤを接続した状態を示す断面図
である。FIG. 1 is a sectional view showing a state in which bonding wires are connected to electrode portions of a semiconductor integrated circuit according to an embodiment of the present invention.
【図２】この発明の一実施例による半導体集積回路の電
極部にボンディングワイヤを接続した状態を示す断面図
である。FIG. 2 is a sectional view showing a state in which bonding wires are connected to electrode portions of a semiconductor integrated circuit according to an embodiment of the present invention.
【図３】図１に示す半導体集積回路の電極部の形成工程
を示す断面図である。3 is a cross-sectional view showing a process of forming an electrode portion of the semiconductor integrated circuit shown in FIG. 1; FIG.
【図４】従来の半導体集積回路の電極部にボンディング
ワイヤを接続した状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state in which bonding wires are connected to electrode portions of a conventional semiconductor integrated circuit.
１ 半導体基板
２ 絶縁膜（フィールド酸化膜）３ 第１
のアルミ電極
４ 絶縁膜（層間膜）
５ 第２のアルミ電極
５ａ 第２のアルミ電極の表面
６ パッシベーション膜
７ ボンディングボール
８ ボンディングワイヤ
９ ポリシリコン電極1 Semiconductor substrate 2 Insulating film (field oxide film) 3 First
Aluminum electrode 4 Insulating film (interlayer film) 5 Second aluminum electrode 5a Surface of second aluminum electrode 6 Passivation film 7 Bonding ball 8 Bonding wire 9 Polysilicon electrode
Claims (2)
該絶縁膜上に形成された少なくとも一層の金属層とを備
えた半導体集積回路電極において、上記絶縁膜と上記少
なくとも一層の金属層との間に突起状電極が設けられ、
前記金属層における最上層の表面にはなめらかな凹凸が
形成されていることを特徴とする半導体集積回路電極。Claim 1: An insulating film formed on a semiconductor substrate;
In a semiconductor integrated circuit electrode comprising at least one metal layer formed on the insulating film, a protruding electrode is provided between the insulating film and the at least one metal layer,
A semiconductor integrated circuit electrode, characterized in that smooth irregularities are formed on the surface of the uppermost layer of the metal layer.
該絶縁膜上に形成された複数の金属層とを備えた半導体
集積回路電極において、上記絶縁膜上に形成された複数
の金属層の最上層を除く層が不連続な層構造に形成され
、前記複数の金属層における最上層の表面にはなめらか
な凹凸が形成されていることを特徴半導体集積回路電極
。2. An insulating film formed on a semiconductor substrate;
In a semiconductor integrated circuit electrode including a plurality of metal layers formed on the insulating film, layers other than the top layer of the plurality of metal layers formed on the insulating film are formed in a discontinuous layer structure, A semiconductor integrated circuit electrode characterized in that smooth irregularities are formed on the surface of the uppermost layer of the plurality of metal layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3149948A JPH04348047A (en) | 1991-05-24 | 1991-05-24 | Semiconductor integrated circuit electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3149948A JPH04348047A (en) | 1991-05-24 | 1991-05-24 | Semiconductor integrated circuit electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04348047A true JPH04348047A (en) | 1992-12-03 |
Family
ID=15486086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3149948A Pending JPH04348047A (en) | 1991-05-24 | 1991-05-24 | Semiconductor integrated circuit electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04348047A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0543544U (en) * | 1991-11-12 | 1993-06-11 | 日本無線株式会社 | Electronic element connection terminal structure |
| US7196000B2 (en) * | 2002-10-22 | 2007-03-27 | Samsung Electronics Co., Ltd. | Method for manufacturing a wafer level chip scale package |
| CN108493200A (en) * | 2018-05-28 | 2018-09-04 | 武汉华星光电半导体显示技术有限公司 | A kind of production method of array substrate, array substrate and display device |
| WO2021240748A1 (en) * | 2020-05-28 | 2021-12-02 | 三菱電機株式会社 | Semiconductor device, method for producing same, and electric power converter |
-
1991
- 1991-05-24 JP JP3149948A patent/JPH04348047A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0543544U (en) * | 1991-11-12 | 1993-06-11 | 日本無線株式会社 | Electronic element connection terminal structure |
| US7196000B2 (en) * | 2002-10-22 | 2007-03-27 | Samsung Electronics Co., Ltd. | Method for manufacturing a wafer level chip scale package |
| CN108493200A (en) * | 2018-05-28 | 2018-09-04 | 武汉华星光电半导体显示技术有限公司 | A kind of production method of array substrate, array substrate and display device |
| WO2021240748A1 (en) * | 2020-05-28 | 2021-12-02 | 三菱電機株式会社 | Semiconductor device, method for producing same, and electric power converter |
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