JPH0454676A - Method and device for layout of lsi function cell - Google Patents

Abstract

PURPOSE:To execute the pattern design of high density by classifying the net into a net for generating a noise, and a net which is apt to be influenced by a noise, executing a wiring to the net for generating a noise, based on a first rule, and executing a wiring to the net which is apt to be influenced by a noise, based on a second rule. CONSTITUTION:First of all, a net 34 for generating a noise is subjected to wiring. In this case, a priority wiring area is classified into a wiring area positioned in the uppermost position of a cell or a wiring area positioned in the lowest position. Secondly, a net 36 which is apt to be influenced by a noise is subjected to wiring. This net is subjected to wiring so that is does not intersect with the net 34 whose wiring is finished, and also, the wiring length becomes as short as possible. Thirdly, other general net is subjected to wiring so that the wiring length becomes as short as possible. In the end, a shield wiring 38 is executed in order to further decrease the influence of a noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a layout device for laying out functional cells used in pattern design of an LSI chip.

(Prior Art) When laying out a functional cell, the presence of parasitic elements that are not included in the designed circuit diagram, such as capacitors, resistors, transistors, etc., has a large effect on the electrical characteristics of the functional cell. Particularly in circuits that require high-speed operation and high precision, crosstalk between wiring nets caused by the presence of these parasitic elements becomes a major problem. Therefore, several methods have been proposed for wiring nets that generate noise or nets that are susceptible to noise using special methods.

For example, “Analog Standard Cell LS” by Harada et al.
In I's Wiring Method J (1990 Institute of Electronics, Information and Communication Engineers Spring National Conference 5A-3-5), wiring channels are classified into analog and digital, each analog and digital wiring is performed, and the rough wiring stage is described. We are evaluating the number of intersections between nets that are susceptible to noise and nets that generate noise, and are working to reduce the number of intersections. However, with this method, it is not necessarily possible to satisfactorily reduce the influence of crosstalk of the noise net and reduce the number of wiring crossings to zero.

(Issues to be solved by the invention) As described above, with conventional methods, it is not possible to eliminate the influence of crosstalk between wirings, which is a problem in the electrical characteristics of circuits that require high-speed operation and high-precision operation. difficult.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to create an LSI functional cell that has high quality electrical characteristics and can easily perform a layout of high-density functional cells in a short time. The purpose of the present invention is to provide a layout device for the layout.

[Structure of the invention]

(Means for Solving the Problems) In order to solve the above problems, the LSI functional cell layout method of the present invention is based on the size of the functional cell to be designed (
(width and height of the cell); determining the position of element placement within the functional cell where the length of the wiring is short and the number of crossings of the wiring is small; and setting the power supply line of the functional cell. A step of determining the degree of influence of noise on the net of each wiring and classifying it into nets that generate noise, nets that are susceptible to noise, and other nets; and a step of classifying nets that generate noise based on the first rule. a step of wiring a net that is susceptible to the noise, taking into consideration the degree of influence of the noise, and based on a second rule for preventing the wiring of the net that generates the noise from intersecting with the wiring; and a step of wiring other nets.

Further, the LSI functional cell layout device of the present invention includes a means for setting the size of a functional cell to be designed, and a means for determining the element placement position in a functional cell where the length of the wiring is short and the number of crossings of the wiring is small. means for determining the power supply line of the functional cell; and means for determining the degree of influence of noise on the net of each wiring and classifying the net into nets that generate noise, nets that are susceptible to noise, and other nets. The present invention is characterized by having a means for wiring a net that generates noise, a means for wiring a net susceptible to noise, and a means for wiring other nets. .

(Operation) In the LSI functional cell layout method of the present invention, elements necessary for a given cell size are arranged, and then a power supply line is set. At this time, a general element arrangement position is determined where the wiring length is short and there are few intersections, and this is used as an initial arrangement to determine the element arrangement position so that wasted layout space is not generated as much as possible. , Next, determine the degree of influence of noise on each wiring net, and divide the net into r type 1: generates noise, r type 2: susceptible to noise, jl type 3:
Others, not particularly related to noise, are classified into three types. By performing this classification, different wiring methods can be applied to each type, and it becomes possible to route the type 1 and type 2 wiring so that they do not cross each other.

Wiring is then done for each type, and if necessary, a power line is inserted between the r type 1: noise generating net and other nets as a shield net. This allows the influence of noise to be further reduced.

When the layout results according to the present invention are compared with the results according to the conventional layout method, it is possible to prevent the deterioration of the electrical characteristics of the circuit due to crosstalk because the nets that generate noise and the nets that are susceptible to noise do not intersect. If necessary, a noisy net can be shielded from the container.

That is, by wiring with a stable potential to the power supply net, it is possible to shield the net that generates noise.

In this way, it is possible to realize a functional cell layout with higher quality electrical characteristics and higher density than in the past.

According to the layout device of the present invention, the method of the present invention can be executed, and therefore, the same effect as described above can be obtained.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows a flowchart of an LSI functional cell layout method according to an embodiment of the present invention. First, in step S1, the size of the functional cell to be placed is set. The size of this functional cell is the height and width of the cell. The height and width of this cell are defined as shown in FIG. 4(a). After this step, the arrangement positions of elements within the cell are determined in step s2. Once the arrangement positions of the elements are determined, the power supply lines for each cell are set in step s3. This power supply line is laid in the peripheral area of the cell as shown in FIG. 4(b). Next, in step s4, the degree of influence of noise on each wiring net is determined. Based on the degree of influence of noise, each net is divided into r type 1: generates noise, type 2: susceptible to noise, r type 3:
Others, not particularly related to noise, are classified into three types.

Based on this classification result, step s5. s6° In S7, each type of net is wired as follows.

For example, in an area where type l and type 2 nets tend to intersect, nets that generate type 1 noise are routed from the right side of the elements within the cell, and nets that are susceptible to type 2 noise are routed within the cell. Wire the elements from the left side. The wiring order of these type 1, type 2, and type 3 nets may be determined as appropriate, and may be determined on a case-by-case basis.

If necessary, shield wiring is provided for the net that generates type 1 noise in step s8. By providing this shield wiring, the influence of noise can be further reduced.

FIG. 2 is a block diagram showing the overall configuration of an LSI functional cell layout device according to an embodiment of the present invention. In the same figure, a database 9 is a storage means that stores information necessary for LSI layout design, and a data processing device 10 performs various processes in layout design, and performs various processes in the layout design. is generated. The console 11 and the interactive editor 12 are operated by a layout designer to input various instructions to the data processing device 10.

The graphic display 13 is the data processing device 10
This is a display unit that displays the layout results obtained by.

FIG. 3 shows a specific configuration of the database 9 and data processing device 10 in FIG. 2. Element library pattern information storage section 15, inter-element connection information storage section 16, design rule-original information storage section 17, circuit drawing information storage section 18, circuit simulation result information storage section 1
9. Net noise influence evaluation result information storage section 20, layout result information storage section 21, cell size setting processing device 2
2. In-cell element arrangement information processing device 23, cell power line setting processing device 24, noise influence degree determination processing device 25,
Net wiring processing device 26 that generates noise, net wiring processing device 27 that is susceptible to noise, other general net wiring processing device 28, shield wiring processing device 2
Consisting of 9.

Next, the operation of the LSI functional cell layout apparatus configured as described above will be explained according to the flowchart shown in FIG. 1 while referring to the layout diagrams of each process shown in FIGS. 4(a) to (e). .

First of all, the element library pattern information storage section 15,
Based on the data in the inter-element connection information storage section 16 and the design rule information storage section 17, the cell size is estimated according to the number of elements to be placed in the functional cell and the number of wirings to be connected, and the width and height of the cell are determined as the cell size. The settings processing device 22 performs settings as shown in FIG. 4(a) (step Sl).

Next, the placement position of the cable member 31 is determined by the intra-cell element placement information processing device 23. At this time, for example, referring to the designed circuit diagram in the circuit drawing information storage unit 18, the wiring length is made as short as possible. The arrangement position of the elements 31 with a small number of intersections is set based on the data in the inter-element connection information storage section 16 and the design rule information storage section 17, and the space 33 between the elements necessary for wiring is secured (step s2).

Then, the cell power line setting processing device 24 sets the cell power line 30 to the upper and lower sides of the cell, as shown in FIG. 4(a) (step s3).

Next, the noise influence degree determination processing device 25 determines the degree of influence of noise on each wiring net (step s4).
). For example, the circuit simulation result information storage unit 19
Referring to the AC analysis results and transient analysis results of the circuit simulation in , compare the magnitude of one phase of the current/voltage amplitude in each wiring net, and identify the "nets that generate noise."
, - "Nets susceptible to the influence of noise" and "Other general networks" and stored in the net noise influence degree evaluation result information storage unit 20.

Then, the classification data is read from the net noise influence evaluation result information storage section 20, and wiring is performed according to each classification. In this case, the element library pattern information storage section 15
, while referring to data stored in the inter-element connection information storage section 16 and the design rule information storage section 17.

First, the "noise generating net 34" is wired in the noise generating net wiring processing device 26 (step s5). At this time, as shown in Figure 4(b), refer to the position of the element terminal connected to each net.
The priority wiring area 32 when wiring the net is divided into the wiring area located at the top of the cell or the wiring area located at the bottom. Furthermore, when drawing out the wiring of the net 34 that generates r noise from the terminal of each element, it is limited to either the right side or the left side of the element.

That is, the wiring for other types of nets is pulled out from the opposite side. In this way, as shown in FIG. 4(C), all "
A net 34 that generates noise is wired.

Second, the wiring processing device 27 of the net which is susceptible to the influence of noise performs a process called “Net 3 which is susceptible to the influence of noise”.
6" (step s6).

This net is wired so that it does not intersect with the already wired "noise generating net 34" and the wire length is as short as possible. For this purpose, as shown in FIG. 4(d), the wires are drawn out from the opposite side from where the "noise generating net 34" is drawn out from the terminals of each element.

Thirdly, other general network wiring processing equipment 2
8, the remaining "other general nets" are routed so that the wiring length is as short as possible.

Finally, if necessary, the shield wiring processing device 29 installs a shield to further reduce the influence of noise between the "net 34 that generates noise" and the "net 36 that is susceptible to noise." Wiring 38 is performed. Normally, shielding is performed using a power line with a stable potential, so as shown in Figure 4(e), the shield wiring 38 is placed so as to sandwich the "noise generating net 34" from both sides. Form.

FIG. 5 shows an enlarged view of the shield wiring 38.

The order and procedure of wiring that generates noise, i.e. the direction of extraction,
When wiring is done using a conventional method that does not take into account the wiring area, the result is as shown in FIG. That is, compared to the layout result according to the present invention shown in FIG. 4(e), in the wiring result according to the present invention, there is no intersection between "the net 34 that generates noise" and the "net 36 that is susceptible to the influence of r noise"; In the conventional method, intersections exist. As described above, according to the present invention, a layout with high quality electrical characteristics is possible.

〔Effect of the invention〕

As described above, according to the present invention, automatic layout of LSI functional cells, particularly layout that reduces crosstalk between wiring nets caused by the presence of parasitic elements, becomes possible. Compared to the conventional automatic layout method, the design period m1 can be shortened, and a high-density pattern design with excellent electrical characteristics can be performed.

[Brief explanation of the drawing]

FIG. 1 is a flowchart of the layout method of the present invention, FIG. 2 is a block diagram showing a schematic configuration of an LSI functional cell layout device according to an embodiment of the present invention, and FIG. 3 is a flowchart of the layout method of the above embodiment. 4(a), (b), (c), (d), and (e) are explanatory diagrams of each processing step of the present invention; FIG. 5 is a shield FIG. 6, an enlarged plan view showing an example of wiring, is a diagram showing an example of a layout result obtained by a conventional wiring method. 9...Database, 10...Data processing device, 1
1... Console, 12... Interactive editor, 13
... Graphic display, 14... Mask pattern data, 15... Element library pattern information storage section, 16... Inter-element connection information storage section, 17...
Design rule information storage unit, 18...Circuit drawing information storage unit, 19...Circuit simulation result information storage unit, 20...Net noise impact evaluation result information storage unit,
21... Layout result information storage unit, 22... Cell size setting processing device, 23... In-cell element arrangement information processing device, 24... Cell power line setting processing device, 2
5...Noise influence degree determination processing device, 26...Net wiring processing device that generates noise, 27...Net wiring processing device that is susceptible to noise, 28...Other general Net wiring processing device, 29... Shield wiring processing device. 2) Figure 2 Applicant's agent Patent attorney Takehiko Suzue (a) 34N Beggar Originated Net (c) Figure (d) Figure (e) Figure

Claims (2)

[Claims] (1) Setting the size of the functional cell to be designed; determining the position of element arrangement within the functional cell where the length of the wiring is short and the number of crossings of the wiring is small; and the power supply of the functional cell. a step of setting a line; a step of determining the degree of influence of noise on the net of each wiring and classifying the net into a net that generates noise, a net that is susceptible to the influence of noise, and other nets; a step of wiring based on the first rule; a step of wiring a net that is susceptible to the noise based on a second rule that prevents the net from intersecting with the wiring of the net that generates the noise; and a step of wiring the other nets. 1. A layout method for an LSI functional cell, comprising the step of wiring. (2) means for setting the size of a functional cell to be designed; means for determining the position of element arrangement within the functional cell where the length of the wiring is short and the number of crossings of the wiring is small; and a power source for the functional cell. A means for setting a line, a means for determining the degree of influence of noise on the net of each wiring and classifying it into a net generating noise, a net susceptible to noise, and other nets, and wiring a net generating noise. 1. A layout device for an LSI functional cell, comprising: means for wiring nets susceptible to noise; and means for wiring other nets.