JPH0451679A - Multiscreen display device - Google Patents

Abstract

PURPOSE:To easily realize multiscreen display through inexpensive configuration by providing a first and a second multiplexers, demultiplexers and plural first-in- first-out memories. CONSTITUTION:Plural compressed digital video signals obtained by compressing plural video signals are written in plural divided areas of a frame memory 27 respectively by the switching control of the first and the second multiplexers 21, 26 and a demultiplexer 23 and the control of the horizontal address 31 for write-in and the vertical address 32 for write-in of the digital video signal by writing address generating means, and the digital video signals in the frame memory 27 are read out successively for every line of a display screen by address generating means 33, 34 for reading out. Thus, the number of analog.digital converters and the number of the frame memories are reduced, and the inexpensive multiscreen display can be realized by only providing the inexpensive first-in-first-out memories 24, 25,... 39 by the portion of the number of horizontal divisions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-screen display device that compresses a plurality of images and simultaneously displays them side by side horizontally and vertically on the same screen.

[Traditional techniques]

In recent years, so-called multi-window display, which displays various types of information simultaneously on the same screen, has become mainstream for display devices used as terminal devices for office automation. This kind of display has become popular not only in still image devices such as text and graph ink, but also in media display devices that handle moving images. Examples of the latter include television receivers with picture-in-picture functions and surveillance camera systems.

Among these, a surveillance camera system has been put into practical use that displays images from, for example, four television cameras on a single monitor screen divided into two vertically and horizontally on four screens.

Hereinafter, a conventional multi-screen display device will be described with reference to the drawings.

FIG. 5 shows a functional conceptual diagram of a conventional multi-screen display device.

In Figure 5, 1 to 4 are analog-to-digital converters (
5 to 8 are frame memories, 9 is a four-output multiplexer, 10 is a digital-analog converter (abbreviated as DAC in the drawings),
11 is a timing generator, and 12 is an image display element.

S and -34 are video signals input to the analog-to-digital converters 1 to 4, respectively.

The operation of the four-screen display device configured as described above will be described below.

First, the input video signals 81 to S4 are converted into digital video signals through the analog-to-digital converters 1 to 4, respectively, and stored in compressed state in independent frame memories 5 to 8, respectively.

In this way, the digital video signal for one frame constructed on each frame memory 5 to 8 is outputted at the reading timing shown below. In other words, as shown in Figure 6, we have created a coordinate system in which the screen is divided into four parts, with the upper right area as the first quadrant, and counterclockwise from this area as the second, third, and fourth quadrants. In this case, the frame memories 5 to 8 to be read are switched according to the position of the scanning line. That is, when the scanning line is in the second quadrant, the digital video signal is read from the frame memory 5, and in the same way, when the scanning line is in the first quadrant, it is read from the frame memory 6, in the third quadrant, it is read from the frame memory 7, and in the fourth quadrant, the digital video signal is read out from the frame memory 5. Each digital video signal is read out from the memory 8, and the multiplexer 9 is also switched. The digital video signal from the multiplexer 9 is again converted into an analog video signal by the digital-to-analog converter IO, and is displayed on the image display element 12. The timing generator 11 generates various timing pulses to perform the above series of controls.

[Problem to be solved by the invention]

In the above configuration, since analog-to-digital converters 1 to 4 and frame memories 5 to 8 are provided corresponding to each video signal, there is an advantage that four-screen display can be performed even for asynchronous video signals. , is ideal for that purpose, but the circuit is complicated and expensive for the purpose of displaying multiple fully synchronous input video signals. Thus, it has been desired to develop an apparatus that can perform multi-screen display with a simple configuration and at low cost, targeting a plurality of video signals that are all synchronized.

An object of the present invention is to provide an inexpensive multi-screen display device.

[Means to solve the problem]

The multi-screen display device of the present invention compresses a plurality of video signals, all of which are in a synchronized state, and displays the compressed video signals side by side in the horizontal and vertical directions on one screen.

For this purpose, this multi-screen display device includes: a sync separator that synchronously separates any one of the plurality of video signals to generate a horizontal sync pulse and a vertical sync pulse; a reference pulse generator that generates synchronized reference pulses; a first multiplexer that receives the plurality of video signals and selectively outputs one of the plurality of video signals; an analog-to-digital converter that converts the video signal output from the multiplexer into a digital video signal for each of the reference pulses; a plurality of first-in, first-out memories that store the digital video signals; and a number of outputs equal to the number of horizontal screen divisions. a demultiplexer having an end and selectively supplying the digital video signal output from the analog-to-digital converter to any of the plurality of first-in, first-out memories according to a selection of the first multiplexer; and a display screen. a frame memory for storing digital video signals in the plurality of first-in, first-out memories; a second multiplexer for selecting one of the digital video signals in the plurality of first-in, first-out memories and sending it to the frame memory; and a horizontal write address for the frame memory. and write address generation means for generating a write vertical address for each of the reference pulses; read address generation means for generating a read horizontal address and a read vertical address for the frame memory for each of the reference pulses; It includes a digital-to-analog converter that converts a digital video signal read from the memory for each reference pulse into an analog video signal, and an image display element that displays the analog video signal output from the digital-to-analog converter. .

[For production]

According to the configuration of the present invention, a plurality of video signals are controlled by switching control of the first and second multiplexers and demultiplexers, and control of the write horizontal address and write vertical address of the digital video signal by the write address generation means. A plurality of compressed digital video signals are respectively written into a plurality of divided areas of the frame memory, and the digital video signals of the frame memory are sequentially read out line by line on the display screen by the read address generation means.

This configuration greatly reduces the number of analog-to-digital converters and frame memories compared to conventional systems, and by simply preparing inexpensive line first-in, first-out memories for the number of horizontal divisions, it is possible to achieve multi-screen display at an overall low cost.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained in Figures 1 to 4.
This will be explained with reference to the figures.

FIG. 1 shows a block diagram of a multi-screen display device according to an embodiment of the present invention, which displays m×n images (m and n are natural numbers) on one screen.

As shown in FIG. 1, this multi-screen display device compresses a plurality of video signals that are all synchronized and displays them horizontally and vertically on one screen.
A multiplexer 21 having Xn input terminals, an analog-to-digital converter 22, a demultiplexer 23 having m output terminals, and m first-in first-out memories (abbreviated as FIFO in the drawing) 24, 25 . ..., 3
9, a multiplexer 26 having m inputs, 2
A frame memory 27 which has a storage capacity for a screen and can independently write to and read from the storage area of one screen and the storage area of the other screen, and a digital/analog converter 28 and CR
An image display element 29 such as T, a sync separator 30, a horizontal writing counter 31, and a vertical writing counter 32
, a readout horizontal counter 33, a readout vertical counter 34, a decoder 35, a divider 36 that divides the input value by n, an adder 37, and a reference pulse generator 38.

The synchronous separator 30 receives m x n video signals S1□ to S
+a+ S++~Sza, +ll, 3111
-3 RII video signals, for example, S nm, are synchronously separated to generate horizontal synchronizing pulses and vertical synchronizing pulses.

The reference pulse generator 38 generates a reference pulse for sampling or the like that is phase-locked with the horizontal synchronizing pulse.

The first multiplexer 21 has a plurality of video signals Sll to
SIN, sx+~Sza+..., S□~S,
1. Input multiple video signals S, ~S+a, Sg
+~S21. . . . selectively outputs one video signal from S1 to Sa.

The analog-to-digital converter 22 is a multiplexer 21
The video signal output from the converter is converted into a digital video signal for each reference pulse.

The plurality of first-in, first-out memories 24, 25, and 39 each have a storage capacity capable of storing digital video signals for a period of 1/m of the horizontal period, and store the digital video signals, respectively.

The demultiplexer 23 has the same number of output terminals as the number m of screen divisions in the horizontal direction, and transfers the digital video signal output from the analog-to-digital converter 22 to a plurality of first-in, first-out memories 24, 25, . ...
, 39.

The frame memory 27 stores digital video signals corresponding to the display screen.

Multiplexer 26 connects multiple first-in, first-out memories 24
, 25. . . . selects one of the 39 digital video signals and sends it to the frame memory 27.

The writing horizontal counter 32 generates a writing horizontal address by counting reference pulses using the horizontal synchronizing pulse as a reset pulse. Further, the writing vertical counter 32 generates a writing vertical address by counting horizontal synchronizing pulses using the vertical synchronizing signal as a reset pulse. The divider 36 performs an operation of dividing the write vertical address by n. Adder 37
Adds a value that is an integral multiple of the number of horizontal scanning lines for one screen divided by n to the output of the divider 36 as the write vertical address of the frame memory 27. Each element of 0 or more is written to the frame memory 27. A write address generating means is configured to generate a write horizontal address and a write vertical address for each reference pulse.

The read horizontal counter 33 generates a read horizontal address by counting reference pulses using the horizontal synchronizing pulse as a reset pulse. Further, the read vertical counter 34 generates a read vertical address by counting horizontal synchronizing pulses using the vertical synchronizing signal as a reset pulse. Each of the above elements constitutes a read address generating means that generates a read horizontal address and a read vertical address for the frame memory 27 for each reference pulse.

The decoder 35 switches the multiplexer 26 every time the number of write horizontal addresses increases by a certain number.

The digital-to-analog converter 28 includes a frame memory 27
The digital video signal read out for each reference pulse is converted into an analog video signal.

The image display element 29 displays the analog video signal output from the digital-to-analog converter 2B.

This multi-screen display device includes a multiplexer 21.
A plurality of compressed digital video signals obtained by compressing a plurality of video signals respectively are stored in the frame memory 27 by switching control of the 26 and demultiplexer 23 and control of the writing horizontal address and the writing vertical address of the digital video signal by the write address generation means. The information is written in each of a plurality of divided areas, and read address generation means sequentially reads out the frame memory 27 line by line on the display screen.

The operation of the multi-screen display device configured as described above will be explained. At this time, the following conditions are assumed.

■ Let's take an example of displaying four screens on one screen.

The amount of information is reduced to one fourth. Techniques for suppressing the reduction in information content (double-density display, interpolation techniques, etc.) are out of the question here.

■ The target is video signals that are completely synchronized by all four people.

To make it more general and cover asynchronous input, it is sufficient to prepare a frame memory for one screen in front of each manual input except for one manual input, perform external synchronization control, and add it to the machine input.

■Random access at video rates for both frame memory and first-in first-out memory is currently impossible. This proposal will become invalid once random access per box element at video rate becomes possible at a practical level.

With the above as prerequisites, the operation will be explained with reference to FIG. FIG. 2 shows the circuit configuration of FIG. 1 rewritten into a four-screen display configuration.

First, four completely synchronized video signals S11. s+z
One of S2□ 32□ is selected by the multiplexer 21, and each is converted from analog to digital at the sample point indicated by the 3rd [1J (a+). In odd lines (scanning lines), the video signal SI+ and the video signal S1 □ are alternately selected and sampled as a, , b, , a2. are alternately selected and sampled as c++dl, Cz, dz, etc., and converted from analog to digital.After this, the analog-to-digital converted digital video signal is finally converted to As shown in the data arrangement in the frame memory of l, “I = a!
+ "' and b,, b!, -... and cl+c!...
. . , d l+ d , . . . are arranged on the frame memory 27 in a state where they are separated into four separate areas.

Due to this layout conversion, in the case of this 4-screen display, 1
Two first-in, first-out memories 24 having a storage capacity capable of storing digital video signals for one half of the horizontal period.
25 is used.

The operation of the first-in first-out memory 24 and 25 is shown in Fig. 4(a).
This will be explained with reference to ffi+. The compressed data strings of video signal S11 and video signal S+z are expressed as (dat
,...) and (b+, bz,...), since the multiplexer 21 alternately selects the video signals S++ and S+□, the data string output from the analog-to-digital converter 22 is As shown in Figure 4 fat, (a,,
b,, az, bz, = 1, but in analog
Since the demultiplexer 23 interposed between the digital converter 22 and the first-in first-out memory 24,25 switches in conjunction with the multiplexer 21, the demultiplexer 23
The data strings (atb, , a, , b, . . . ) are classified, and the data strings a, (i-1
, 2, . . .) are input, and the first-in, first-out memory 25 stores the data string.

(i=1, 2...) will be input. The above is the sampling of the video signal of the odd numbered line, but the sampling of the video signal of the even numbered line is also the same as above. That is, as shown in FIG. 4), the video signal So1. St2 time series data string (c 1.d
1. C2, d z, -) is the data string C0 (i=1.
2. ) and data string d, (i=123...)
are categorized.

The data string ai+bi of the video signal is stored in the first-in, first-out memory 2425 as described above.

c4. d4 are read out according to the following timings. That is, when reading data from the first-in, first-out memories 24 and 25, the video signal S11 or the video signal SZ+ is selected at the timing of the left half of the horizontal scanning period, and the video signal S1. Or video signal S. Select.

Such selection is made by multiplexer 26,
The switching is controlled by the decoder 35.

Then, horizontal memory arrangement in the frame memory 27 is performed by interlocking the data read clock from the first-in, first-out memories 24 and 25 with the write clock to the frame memory 27.

On the other hand, vertical writing to the frame memory 27 is performed as follows. That is, data strings a6 . J
are video signals S□, Szt that are written to the first half of the frame memory 27 and sampled on even-numbered lines.
The data string c, dB is written to the latter half of the frame memory 27 by dividing the output address value from the write vertical counter 32 by 2, leaving it unchanged for odd lines, and changing the vertical width for even lines. Add the number of horizontal scanning lines equivalent to 1/2.

In addition, if the vertical direction is divided into three, the 3rd x-2 line (
x=1.2. ), write vertical counter 32
The value obtained by dividing the output address value from 3 by 3 is set as the vertical address, and in the 3rd
The vertical address is the value obtained by dividing the output address value from 3 by 3 and adding the number of horizontal scanning lines corresponding to one-third of the vertical width. Divided by 3 plus 2/3 of the vertical width
The vertical address is the value obtained by adding the number of horizontal scanning lines corresponding to . In the case of n-division, the output address value from the write vertical counter 32 is divided by n, and the vertical address is determined by adding a value of 1/n to (n-1) of the vertical width.

With the above, the data arrangement state shown in the 31st EHb+ can be realized. The digital video signal thus configured in the frame memory 27 is sequentially read out in the order of arrangement by the readout horizontal counter 33 and the readout vertical counter 34, and after digital-to-analog conversion by the digital-to-analog converter 28, the image display element By supplying the signal to 29, a four-screen display is made.

Here, the frame memory 27 has a memory for two fields, and when one field is being written, the other is used for reading, and functions as a double buffer that alternately inverts the two fields. , and the read address independently, it is possible to display images in real time.

The above has been explained from the aspect of processing the video signal, but below we will supplement the timing generation section for controlling each section.

Any one of the four video signals S++, S+z, Sz+, St□ (video signal St□ in FIG. 2) is applied to the sync separator 30 to generate a horizontal sync pulse and a vertical sync pulse. At the same time, the reference pulse generator 38 generates a reference clock 7 which is phase synchronized with the horizontal synchronizing pulse. This becomes a sampling pulse, and the analog
It is used not only as a clock to the digital converter 22 and the frame memory 27, but also to generate a reference signal for each block. In the case of color video, 4 times 3.58 MHz is often used.

The horizontal synchronization pulse and vertical synchronization pulse generated by the synchronization separator 30 are sent to a horizontal write counter 31 and a vertical write counter 32 .
Horizontal counter for reading 33. The reading vertical counter 34 is driven. The write horizontal counter 31 serves as a horizontal address directly to the frame memory 27 and at the same time as an input to a decoder 35 which generates a signal for switching the multiplexer 26 in the center of the screen of the image display element 29. In order to function as a vertical address to the frame memory 27 as described above, the write vertical counter 32 can map odd addresses to the first half when the vertical width is halved, and map even addresses to the second half. In this example, the divider 36 functions as a shifter that divides the output value of the horizontal writing counter 31 into half, and adds 0 when the number is odd and halves the vertical width when the number is even. an adder 37 that adds the number of horizontal scanning lines of
This has been achieved by

As described above, according to this embodiment, by using two first-in first-out memories 24, 25 and one frame memory 27, a 400-page display device can be constructed.

In this embodiment, for the sake of simplicity, a method for realizing four-screen display has been described, but in -C, the horizontal direction is divided into m and the vertical direction is divided into n.
Of course, it is possible to configure multiple screens of mxn, and for a multiscreen display device that displays multiple screens of mxn, the explanation will be limited to the difference in configuration from a four screen display device, and the explanation of the overall configuration will be omitted.

In the mxn multi-screen display device, the multiplexer 21 that switches video signals has a configuration that selects one input from mxn inputs, the demultiplexer 23 has a configuration that can distribute to m outputs, and has a first-in first-out memory 24, 25, .・
. . 39 are required, and the multiplexer 26 is configured to be able to select one input from m inputs. The decoder 35 is configured to switch the multiplexer 26 every time the vertical address exceeds a value that is an integral multiple of the vertical width divided by n. The divider 36 and the charger 27 are as described above.

The display operation of the m x n multi-screen display described above can be easily inferred from the operation of the four-screen display, so a description thereof will be omitted.

〔Effect of the invention〕

The multi-screen display device of the present invention converts a plurality of video signals into digital video signals using one analog-to-digital converter by providing first and second multiplexers, a demultiplexer, and a plurality of first-in, first-out memories. At the same time as converting, the digital video signals for multi-screen display are stored on the frame memory by compressing multiple video signals and storing them separately in the frame memory. memory and one analog
By simply providing a digital converter, multi-screen display can be easily performed with an inexpensive configuration.

Note that for multi-screen display, first-in, first-out memories corresponding to the number of horizontal divisions are required, but first-in, first-out memories are sufficiently cheaper than frame memories, so there is no problem in reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a multi-screen display device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a four-screen display device as a specific example of the multi-screen display device of FIG.
Figure 3 is a diagram showing the relationship between sampling timing and data arrangement on the frame memory in a 4-screen display.
The figure shows data array conversion using a first-in first-out memory, FIG. 5 is a block diagram showing the configuration of a conventional four-screen display device, and FIG. 6 shows the relationship between scanning lines and readout memory in a conventional four-screen display device. It is a diagram. 21... Multiplexer, 22... Analog-to-digital converter, 23... Demultiplexer, 2425.
29... First-in first-out memory, 26... Multiplexer, 27... Frame memory, 28... Digital-to-analog converter, 29... Image display element, 30...
・Sync separator, 31...Horizontal counter for writing, 3
2... Vertical counter for writing, 33... Horizontal counter for reading, 34... Vertical counter for reading,
35... Decoder, 36... Divider, 37... Charger, 38... Reference pulse generator diagram (a) - Anvil line 111 Even number line: Dimble, Nero: Non-sample, φ, (b) Figure Figure TT-Oki bet

Claims (1)

[Scope of Claims] A multi-screen display device that compresses a plurality of video signals that are all in a synchronized state and displays them horizontally and vertically on one screen, wherein any one of the plurality of video signals a sync separator that synchronously separates the video signals to generate a horizontal sync pulse and a vertical sync pulse; a reference pulse generator that generates a reference pulse that is phase-synchronized with the horizontal sync pulse; and a reference pulse generator that receives the plurality of video signals. a first multiplexer that selectively outputs one video signal from the plurality of video signals; and an analog converter that converts the video signal output from the first multiplexer into a digital video signal for each of the reference pulses. - A digital converter, a plurality of first-in, first-out memories that store the digital video signals, and a plurality of first-in, first-out memories having the same number of output terminals as the number of screen divisions in the horizontal direction, and converting the digital video signal output from the analog-to-digital converter into the first a demultiplexer that selectively supplies digital video signals to any of the plurality of first-in, first-out memories according to the selection of the multiplexer; a frame memory that stores digital video signals in correspondence with display screens; a second multiplexer that selects any one of the above and sends it to the frame memory; write address generating means that generates a write horizontal address and a write vertical address for the frame memory for each of the reference pulses; a read address generation means for generating a read horizontal address and a read vertical address for the frame memory for each reference pulse; and a digital video signal for converting a digital video signal read from the frame memory for each reference pulse into an analog video signal. an analog converter; and an image display element that displays an analog video signal output from the digital-to-analog converter; switching control of the first and second multiplexers and the demultiplexer; and write address generation means. writing a plurality of compressed digital video signals obtained by compressing the plurality of video signals respectively into a plurality of divided areas of the frame memory by controlling the horizontal address for writing and the vertical address for writing of the digital video signal by the address for reading; A multi-screen display device, wherein the digital video signal from the frame memory is sequentially read out line by line on a display screen by a generating means.