JPH0450784A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To conduct an efficient test even with a small number of pins without requiring any enable input terminal by adding an N-bit shift register for writing a determined data sequence N times and a decoder which inputs N Q outputs. CONSTITUTION:For example, when a 3-bit shift register 21 and a D-FF 24 are reset to a test mode, the signal Reset of an internal circuit 2 is held at 0 at a point tR of time. When Adr2 is selected as a new address and 1, 0, and 1 are written successively to the LSB1 of a data bus with a write signal WR5, outputs Q1, Q2, and Q3 of a register 21 become 1, 0, and 1 from a point (t) of time and a test enable output 23 becomes 1. When Adrl is selected as an address at a point tt and 1 is written in the D-FF 24 with the signal WR5, the output TM of an AND gate 20 becomes 1 and the test mode is entered. Consequently, the test enable terminal of an LSI 1 wherein a test mode setting circuit is incorporated becomes unnecessary and the test can be conducted efficiently even with a small number of pins.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit (hereinafter abbreviated as LSI) having a test mode setting circuit.
Regarding.

[Conventional technology]

When testing digital LSIs or LSIs with mixed analog and digital functions using an LSI tester, or when tests cannot be easily performed using AC or DC tests, or when tests cannot be performed in a short period of time, test mode setting circuits are built into the LSI in advance. We aim to improve efficiency and shorten time.

Below, when testing using the test mode setting circuit,
This state is called a test mode, and the other normal use state is called a normal mode.

Normally, when using an LSI, the normal mode is used unless there is a special occasion, and the test mode is not open to general users. Therefore, a special terminal is set to pull the internal power supply potential or ground potential.
It's up, pulled down. When testing with a tester is necessary, a certain potential is applied to that terminal and the test is performed, and for normal use, the terminal is left open.

FIG. 4 is a block diagram of a conventional example commonly used. In this example, an LSI with a CPU interface is assumed.

In Fig. 4, 1b is the LSI itself, and 2a is the LSI.
Internal circuit of SI, 3 is data bus, address bus,
4 to 6 are C8 and WR respectively.

It is one knife. 7, 9, 11.14 are general input terminals, 8,
10, 12, and 13 are general output terminals, 15 is the data bus least significant bit (hereinafter referred to as LSB), and 16 is the test/bus terminal.
Enable input terminal, 17 is a pull-down resistor, 18 is D
type flip-flop (hereinafter referred to as D-FF), 19 is AND
It is a gate.

The operation of the blocks in FIG. 4 will be explained using the timing chart of each signal shown in FIG.

When the test enable input terminal 16 is used open, in normal mode, the pull-down resistor causes the terminal 16 to be at a low level (“°○’°
That's what it means. On the other hand, the high level is called 1゛) and AND19
The output signal TM of D-FF18 becomes 0°".
Even if 1"° is written to WR from the CPU interface at
The normal mode is maintained from n onwards.9 Conversely, if the signal TE of the test enable terminal 16 is set to °1"' at time tn, the AND gate is activated by "1" written to the D-FF 18 in the test mode. The output signal TM of 19 is also “1”
°, and the fact that it is the test mode is output to the internal circuit 2a. Thereby, LSI can be tested efficiently.

[Problem to be solved by the invention]

The above-described conventional test mode setting circuit for semiconductor integrated circuits requires a terminal such as the test enable input terminal 16, and has the disadvantage that it is difficult to apply in the case of a small number of pins.

[Means to solve the problem]

The semiconductor accumulation circuit of the present invention includes a D flip-flop that inputs the least significant bit of a data bus input to an internal circuit as data, and a test mode signal that is inputted to the Q signal and test enable signal of the D flip-flop. In a semiconductor integrated circuit that has a built-in test mode setting circuit that has an AND gate that supplies internal circuits, addressing is specified from the input of the CPU interface, and the predetermined data string is transmitted N times (N = 2.3 ...) Adds an N-bit shift register for writing and a decoder that inputs N Q outputs of the N-bit shift register, inputs the data string N times in succession, and inputs the data string to the decoder. It is constructed by inputting the output signal of the circuit as the test enable signal to one of the AND gates.

〔Example〕

Next, the present invention will be described with reference to compartments.

FIG. 1 is a block diagram of a first embodiment of the present invention. In Figure 1, 1 is the LSI itself, 2 is the LSI
2 is a Re5e internal circuit of the conventional internal circuit 2 of FIG.
A t signal output terminal is added.

The terminals of LSII are the terminals of LSllb in FIG. 4 except that the test enable input terminal 16 is removed. That is, 3 is the data bus, address bus, and 4 to 6 are each C3.
, WR, RDr.

7. 9, 11, 14, 25 are general input terminals, 8° 10.
12 and 13 are general output terminals.

15 is the LSB of the data bus, 20 is the AND gate, 2
1 is a 3-bit shift register when N is 3,
22 is a decoder, 23 is a test enable output, and 24 is a D-FF. Note that CKI and CR2 are clocks that are generated when either address 1 or address 2 is selected from the CPU interface and the write signal WR becomes ``0''.

Note that Re5et is a signal that becomes "0" when reset from outside the LSI.

Next, the operation of the blocks in FIG. 1 will be explained using the timing chart of each signal shown in FIG. 2.

First, the pin of the CPU interface of the LSII in the block shown in Figure 1 becomes "0" and Adr2 is set as the address.
is selected, and at time tw, the write signal VW first writes “1” and then “0” to LSH of the data bus.The output Ql of the 3-bit shift register 21
, Q2 become 0'' and ``1'', respectively. In this state, the output 23 of the decoder 22 does not become 1', but selects Adrl as the address, and writes 1'' to the LSB of the data bus using the write signal WR. , even if "1" is written in the D-FF 24, the output signal TM of the AND gate 20 does not become "1" and the test mode is not established.

When resetting the 3-bit shift register 21 and D-FF 24, the signal Re5et of the internal circuit 2 is set at time t.
Set R to 0'°.

Next, Adr2 is selected as a new address, and the write signal WR causes "1" to be written consecutively to the LSB of the data bus.
When 0" and 1" are written, the outputs Ql, Q2 and Q3 of the 3-bit shift register 21 become "0" and "1" from time t, respectively.
1", "O°' becomes "1" and test enable pressure 2
3 becomes "1".

Next, at time 11, when Adrl is selected as the address and "1" is written into the D-FF 24 by the write signal Wl, the output TM of the AND 20 becomes 1'' and the test mode is entered.

FIG. 3 is a block diagram of a second embodiment of the invention. The difference from the first embodiment is that LSlla is L of the data bus.
A predetermined code is input to the 8-bit data decoder 26 in place of the 1 bit of SB, and only if they match, ``1'' is output, and if not, ``0'' is output. Other operations are exactly the same as in the first embodiment.

〔Effect of the invention〕

As described above, the present invention has the effect of eliminating the need for a test enable input terminal in an LSi device incorporating a test mode setting circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a timing chart of each signal to explain the operation of the first block, and FIG. 3 is a block diagram of the second embodiment of the present invention. 4 is a block diagram of an example of a conventional semiconductor integrated circuit, and FIG. 5 is a timing chart of each signal for explaining the operation of the block in FIG. 4. 1...LSI, 2...Internal circuit, 3...Data
Bus, address bus, 4...CY, 5...WR1
6... Shoulder, 7.9.11, 14.25... General input terminal, 8, 10, 12.13... General power terminal, 15
...Data bus (LSB), 16...Test enable input terminal, 17...Pull-down resistor, 18°24...D type flip-flop, 19.20...
AND gate, 21... 3-bit shift register, 22... decoder, 23... test enable output, 26... 8-bit data converter, 27
...Output of the decoder 26.

Claims (1)

[Claims] A D flip-flop that inputs the least significant bit of the data bus input to the internal circuit as data, and an AND gate that inputs the Q signal and test enable signal of the D flip-flop and supplies a test mode signal to the internal circuit. In a semiconductor integrated circuit having a built-in test mode setting circuit, a method for writing a predetermined data string of the data N times (N=2, 3,...) by specifying an address from the input of a CPU interface. N-bit
A shift register and a decoder inputting N Q outputs of the N-bit shift register are added, the data string is inputted N times in succession, and the output signal of the decoder circuit is used as the test enable signal. A semiconductor integrated circuit characterized in that the input signal is input to one of the AND gates.