JPH116869A - Semiconductor integrated circuit and testing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable setting of a test mode by one exclusive terminal for testing and also to enable execution of a test without putting any restriction on ordinary input-output terminals other than the exclusive terminal for testing, in a semiconductor integrated circuit having a plurality of test modes. SOLUTION: One exclusive terminal 301 for testing is added to input-output terminals of an ordinary circuit. Besides, a test mode register 310 for setting a test operation mode is provided, and further a test mode holding register 311 is provided so that the data of the test mode register may not be rewritten in the course of testing. During the testing, writing in the test mode register is prohibited by the test mode holding register. The exclusive terminal for testing is connected to initial setting signals of the test mode register and the test mode holding register, and test mode data and test mode holding data are used also for ordinary input and output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a test method therefor, and more particularly to a semiconductor integrated circuit having a test mode different from a normal operation mode, in which test dedicated terminals are reduced and testability is improved. It relates to the technology to be performed.

[0002]

2. Description of the Related Art As a test method of a semiconductor integrated circuit, a method of inserting a circuit in order to improve observability and controllability of an internal signal and to facilitate a test (hereinafter referred to as test facilitation design), for example, a split test Methods, ad hoc methods, and scan design methods are well known. In these test facilitation designs, at least one or more dedicated test terminals are provided, and a logic value different from that during normal operation is provided to the dedicated test terminals so that each test circuit operation is made effective. Is common. Further, particularly when the chip area is affected by the number of terminals of the semiconductor integrated circuit, the number of dedicated test terminals is reduced to reduce the chip cost. As a conventional technology, a terminal for switching from a normal operation state to a test state is provided as a dedicated test terminal,
In general, input / output of test data to / from a circuit under test is performed by inserting a selection circuit and also serving as a normal terminal.

FIG. 1 shows an embodiment of a conventional divided test method. In FIG. 1, reference numeral 101 denotes a dedicated test terminal, which serves as a selection signal for the selection circuits 107, 108, 109, and 110. Reference numerals 102, 103, 104, and 105 denote normal input / output signals. When a test mode is selected by a dedicated test terminal, the reference
Then, test data is input to the circuit block under test 115 from the input terminal 108, and 104 and 105 are input to the selection circuits 109 and 110.
And outputs test data of the circuit block under test.
In the normal operation mode, the internal signals 111 and 112 are supplied to the block under test 115, and the internal signals 113 and 114 are output to the normal input / output terminals 104 and 105.

Further, when there are a plurality of test modes, for example, when there are a plurality of test modes in which a plurality of internal logical blocks are divided and each block is tested independently, or when a divided test method and a scan design method are used. When there are both test modes, a dedicated test terminal for selecting a test mode is provided, or a logic circuit is inserted so as to have a mode selection function only at the time of a test in order to share with a normal terminal. FIG.
1 shows an embodiment of a test mode selection circuit using an AND circuit. 201 is a test-only terminal, 202, 203, 20
4, 205 are normal input terminals, 206, 207, 208,
209 is a test mode selection signal. In FIG. 2, by setting the test dedicated terminal to “1”, 202 to 205
Can input a plurality of test mode selection signals from the normal input terminal. Furthermore, in FIG. 2, 206 to 209 can be decoded to provide a test mode selection signal.

[0005]

However, it is necessary to fix the input data in the test mode selection terminals in each test mode. Therefore, when the test mode selection terminal is also used as a normal input / output terminal, there are cases where restrictions are imposed on test data setting and test data observation, and a sufficient test cannot be performed or the test is complicated. The present invention has been made in order to solve the above-described problems. Even when a plurality of test modes are provided, a normal input / output or a test is performed except for one test dedicated terminal for switching from a normal operation state to a test state. An object of the present invention is to provide a semiconductor integrated circuit serving as data input / output and a test method thereof.

[0006]

In order to solve this problem, a semiconductor integrated circuit according to the present invention comprises: a) a register of at least one bit for changing to a test operation mode different from a normal operation (hereinafter referred to as a test mode). B) at least one or more dedicated test terminals for enabling setting of the initial value of the test mode register and writing data to the test mode register; and c) for holding the data of the test mode register. A register having at least one bit (hereinafter referred to as a test mode holding register) different from the test mode register, and d) the data input of the test mode register and the test mode holding register are the same as the signal input of the normal operation. It is characterized by being common.

Further, the test method includes: e) in the test flow of the semiconductor integrated circuit according to claim 1, f) a step of enabling data writing to the test mode register and the test mode holding register by a test dedicated terminal; g). Writing data from the normal terminal to the test mode register and the test mode holding register; h) excluding the test mode register and the test holding register;
Initializing a semiconductor integrated circuit to be tested; i) inputting or outputting test data from a normal terminal; and j) resetting a test mode register and a test mode holding register by a dedicated test terminal to invalidate data writing. It is characterized by comprising steps.

[0008]

Embodiments of the present invention will be described below. FIG. 3 shows an embodiment of the present invention.

In FIG. 3, reference numeral 301 denotes a dedicated test terminal.
During a normal operation, the test mode register 310 and the test mode holding register 311 are initialized, and writing to the test mode register 310 and the test mode holding register 311 is permitted in the test mode. Reference numeral 302 denotes a normal input / output terminal, which can supply an AND signal 312 with an inverted signal of the output of the test mode holding register 311 to the clock of the test mode holding register. Reference numeral 303 denotes a normal input / output terminal, which is a data input of the test mode holding register. Reference numerals 304, 305, and 306 are normal input / output terminals, which can supply data input to the test mode register. Reference numeral 311 denotes a test mode holding register, which is configured by one flip-flop. 310 is
The test mode register is composed of a plurality of flip-flops, and the clock of the test mode register 310 is the same 312 as the clock signal of the test mode holding register. 307, 308, and 309 are output signals of the test mode register 310, which operate as signals for selecting a test mode. Further, 307, 308,
309 can be decoded to provide a test mode signal. When the test mode state, that is, the reset release state is set by the test dedicated terminal 301 in FIG. 3, the data input 303 of the test mode register 311 is performed.
Is "0", 302 and 304, 305, 306
, The data in the test mode register 310 is rewritten. On the other hand, when 303 is “1”,
At the first clock input from 302, data is written to the test mode register 310, and thereafter, 302 and 3
Even if the signals of 04, 305, and 306 change, the data of the test mode register is held. FIG. 5 shows an embodiment in which data is set in parallel in the test mode register. FIG. 6 shows an embodiment in which data is serially set in the test mode register. In this case, when the last data of the serial data is set, "1" is set in the test mode holding register in FIG. FIG. 7 shows an embodiment in which the test mode register is constituted by a binary counter. In this case, "1" is set in the test mode holding register of FIG. 3 at the last clock of a predetermined counter value.

FIG. 4 shows a test flowchart of the present invention. First, writing to the test mode register and the test mode holding register is permitted by the test dedicated terminal (40).
2). Next, data is written to the test mode register according to the circuit configuration of the test mode register, and "1" is written to the test mode holding register in the final data writing to hold the data of the test mode register (403). At this point, the circuit is in a predetermined test mode state. Therefore, the test circuit is initialized in the test mode (404). Next, a test is performed using input / output terminals other than the test dedicated terminal (405).

When the test in one test mode is completed,
Return to the normal operation mode (406). If there is another test mode, the process returns to step 402 and the test is repeated.

[0012]

As described above, according to the present invention,
Even in a semiconductor integrated circuit having a plurality of test modes,
The test can be performed only by providing one test-dedicated terminal. In the test operation mode, only the test-dedicated terminal is fixed to the enable value and the other normal input / output can be operated freely. Since there is no restriction that the value must be fixed to the enable value, testability (controllability and observability) is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional division test method.

FIG. 2 is a circuit diagram of a test mode selection signal according to the related art.

FIG. 3 is a block diagram of a test mode selection signal according to the present invention.

FIG. 4 is a flowchart of the test method of the present invention.

FIG. 5 is a circuit diagram of a test mode register according to an embodiment of the present invention.

FIG. 6 is a circuit diagram of a test mode register according to an embodiment of the present invention.

FIG. 7 is a circuit diagram of a test mode register according to an embodiment of the present invention.

[Description of Signs] 101 Test dedicated terminal 102-105 Normal input / output terminal 106 Test mode selection signal 107-110 Selection circuit 111-114 Internal signal 115 Circuit under test 201 Test dedicated terminal 202-205 Normal input / output terminal 206-209 Test mode selection signal 301 Test dedicated terminal 302 to 306 Normal input / output terminal 307 to 309 Test mode selection signal 310 Test mode register 311 Test mode holding register 312 Test mode register and test mode holding register write clock 401 Test start 402 Test mode register reset Release step 403 Test mode register data write step 404 Normal circuit initialization step 405 Test execution step 406 Test mode register reset step 407 All tests Step 408 of test termination 501 Test dedicated terminal 502 Test mode register write clock 503 Test mode register 504 to 506 Normal input / output terminal 507 to 509 Test mode selection signal 601 Test dedicated terminal 602 Write test mode register Clock 603 Normal input / output terminal 604 Test mode register 605-607 Test mode selection signal 701 Test dedicated terminal 702 Test mode register write clock 703 Test mode register 704-706 Test mode selection signal

Claims (2)

[Claims] A) a register of at least one bit (hereinafter referred to as a test mode register) for changing to a test operation mode different from a normal operation; b) setting of an initial value of the test mode register and a test mode At least one or more dedicated test terminals for enabling data writing to the register; and c) a register of at least one bit separate from the test mode register to retain the data of the test mode register. D) a test mode register and a data input of the test mode holding register are common to a signal input of a normal operation. 2. The test flow of a semiconductor integrated circuit according to claim 1, wherein: b) enabling data writing to a test mode register and a test mode holding register by a dedicated test terminal; and c) starting from a normal terminal. Writing data to the test mode register and the test mode holding register; d) excluding the test mode register and the test holding register;
Initializing a semiconductor integrated circuit to be tested; e) inputting or outputting test data from a normal terminal; and f) resetting a test mode register and a test mode holding register by a dedicated test terminal to invalidate data writing. A test method comprising steps.