JPH03191884A - Integrated circuit - Google Patents

Abstract

PURPOSE:To perform a direct current test in a short time by constructing a DC test mode setting output buffer part such that the portion has a logic circuit for setting high and low level direct current test voltages to a plurality of output terminals in a prescribed order. CONSTITUTION:The setting signal SM of an input terminal 22 is inputted to the control end C of a DC test mode setting output buffer part 3 via an input buffer 27 and the internal output logic signal SL of an internal logic circuit 2 is selected to be outputted to output terminals 4-7 via the buffer portion 3. When a DC test is performed, particularly Voh, Ioh, Vol or Iol is tested, by using an LSI tester, a level 'H' is applied to the terminal 22 as the signal SM. Then, the signal 'H' is inputted to the control end C of the buffer portion 3 via the input buffer 27 and the signal SL of the circuit 2 is not selected. Therefore, the voltage levels of the terminals 4-7 are fixed to the levels 'H', 'L', 'H' and 'L', respectively. Thus, since high and low level output voltage or current characteristics can be measured at the same time on every other pin in an order from 1 to 7, a measuring time can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit, and particularly to an integrated circuit having a DC test mode setting circuit for LSI.

[Conventional technology]

DC test of digital LSI using LSI tester (
In the DC test), the high level output voltage (hereinafter referred to as VOH), high level output current (hereinafter referred to as 10H), low level output voltage (hereinafter referred to as VOt), and low level output current (hereinafter referred to as IOC) of the digital output bin. In the measurement of
A test mode setting signal is applied to the LSI under test, and when the DC voltage of the digital output reaches the expected high or low output level, the LSI is stopped with the power on, and the DC test is performed.

However, when there are many digital output bins, the expected output voltage level is often different for each bin, such as high or low. When the expected output voltage level is reached, stop the power supply with the power on.
Perform the C test, then apply the test mode setting signal for DC test again, and when the next other pin reaches the next predetermined expected voltage level, stop the power while it is on and perform the DC test. This was repeated until the measurement was completed.

In this case, there is a problem in that the test mode setting signal for DC testing must be input many times, which increases the total testing time.

Conventionally, various methods have been used to solve the above problems.
I have been announced. (Special Public Interest Publication No. 64-0005461
).

FIG. 3 is a circuit diagram of an example of a conventional integrated circuit.

This LS under test 11b performs a DC test by fixing each output bin to a voltage of a predetermined expected output level without inputting the test mode setting signal for DC test and the DC signal many times.

The LSI under test 1b has an internal logic circuit 2 that inputs input logic signals from input terminals 18 to 21 and outputs an internal output logic signal SL, and inputs an internal output logic signal SL, a DC test mode setting signal SM, and a DC signal SHL. selector 3
2 to 35 and a DC test mode setting/output buffer section 3a having output buffers 8 to 11.

When this LSI 1b under test is used normally, or when connected to output terminals 4 to 7, the LSI tester 36
When performing functional tests etc. on input terminal 22, connect DCC to input terminal 22.
Test mode setting signal S is raised to low level (hereinafter "L"')
) or pull down the input terminal 22.

The signal SM at the input terminal 22 is passed through the input buffer 27 to D
Selector 3 of C test mode setting/output buffer section 3
It is input to each select terminal of 2 to 35, and the internal logic circuit 2
The output logic signal SL of is selected, and the signals passing through selectors 32-35 are outputted to output terminals 4-7 through output buffers 8-11, respectively.

DC test using LSI tester 36, especially Volt.

IOH,V (When testing silicon and IOL, a high level (hereinafter referred to as "H") is input to the input terminal 22 as the input DC test mode setting signal SM.

When "H" is input, the signal passed through the input buffer 27 is input to the select terminals of the selectors 32 to 35 of the DC test mode setting/output buffer section 36, and the output logic signal SL of the internal logic circuit 2 is not selected. The DC signal SHL input to the input terminal 21 and passed through the input buffer 26 is selected.

For example, when "L" is input as the DC signal SHL to the input terminal 21, the output level "L" is input to all output terminals 4 to 7.
” is output, and using the LSI tester 36, VOL, I
OL DC test can be done.

Similarly, when "H" is input as the signal SHL to the input terminal 22, "H" is output to all the output terminals 4 to 7, so that the test of VO) I and T can be performed.

That is, since the same output level is output to all output terminals at the same time, the DC test is performed twice for "L" and "H" levels.

[Problem to be solved by the invention]

Although the above-mentioned conventional integrated circuit has considerably reduced the time required to conduct a DC test, it has the disadvantage that it is necessary to apply the input level ``L'' and HI+ twice as the DC signal sHt to the input terminal 21. There was.

An object of the present invention is to provide an integrated circuit that can perform DC testing in a short time.

[Means to solve the problem]

The integrated circuit of the present invention provides a DC test in which an internal output logic signal of an internal logic circuit and a DC test mode setting signal are input, and a predetermined high or low level DC voltage is set to a plurality of output terminals in the DC test mode. In the integrated circuit having a mode setting/output buffer section, the DC test mode setting/output buffer section includes a logic circuit that sets high and low level DC test voltages to the plurality of output terminals in a predetermined order. It is configured.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The LSII under test has the DC test mode setting/output buffer section 3. shown in FIG. Internal output logic signals SL and DC instead of
It is the same as the conventional LS under test 11b except that it includes a DC test mode setting/output buffer section 3 which inputs the C test mode setting signal S.

The DC test mode setting/output buffer unit 3 outputs the OR logic of one of the internal output logic signals SL and the DCC test mode setting signal S, or the AND logic output of one of the signals SL and the inverted signal of the signal SM, to output buffers 4 to 7. Set alternately.

In this embodiment, when this LSI is normally used or when performing a functional test with a tester, the DCC test mode setting signal S is applied to the input terminal 22 to input the input level "L 11" as in the conventional example. Alternatively, the input terminal 22 may be pulled down.

The setting signal SM of the input terminal 22 is passed through the input buffer 27 to the control terminal C of the DC test mode setting/output buffer section 3.
The internal output logic signal SL of the internal logic circuit 2 is selected, passes through the DC test mode setting/output buffer section 3, and is output to output terminals 4-7.

DC testing, especially VOH using an LSI tester.

IO+1. When testing VOL and IOL, level II is applied to the input terminal 22 as the test mode setting signal SM.
Give H11.

When “H” is input to the input terminal 22, the input buffer 27
The signal °°H'" through the DC test mode setting/output buffer section 3 is input to the control terminal C of the DC test mode setting/output buffer section 3, and the output logic signal SL of the internal logic circuit 2 is not selected. That is, the DC test mode setting/output buffer section 3 OR gate inside OR
The output voltage of the AND gate AND is fixed to "H", and the output voltage of the AND gate AND is fixed to "L".9 Therefore, the voltage levels of the output terminals 4.5 and 6.7 are "HII, uLII,", respectively. HII and °“L
” is fixed.

As described above, the voltage or current characteristics of high-level output and low-level output can be measured at every other pin in the order of 4 to 7 at the same time, and adjacent output buffers 8 to 11 in the same SLI have the same high level Since it is not necessary to invert the DC mode setting signal SM to "L" because it is assumed that the DC mode setting signal SM has low level characteristics, the total measurement time of the DC test can be reduced to half of the conventional measurement time.

In general, in the case of a digital LSI, output buffers 8 to 11 often use output buffers with the same driving capacity for both level output and low level output, so if the design is designed with sufficient margin in advance, the test method of this example However, this omission of inversion poses no particular problem. FIG. 2 is a circuit diagram of a second embodiment of the present invention.

The difference from the first embodiment is that the LSI under test1. The DC test mode setting and control of the output buffer unit 3 are performed through the CPU interface 28.

Data input from the CPU interface 28 passes through an output buffer 29 and a data bus 30, and is written to a D-type flip-flop (hereinafter referred to as a D-type FF) 31.
The Q output of 31 becomes the input to the control terminal C of the DC test mode setting/output buffer section 3.

In this embodiment, when LSI is normally used or when LSI is used,
When performing a functional test using an I tester, "Lo" is written from the CPU interface 28 to the D-type FF 31.

The Q output "L" of the D-type FF 31 is input to the control terminal C of the DC test mode setting/output buffer section 3, and the internal output logic signal SL of the internal logic circuit 2 is selected to set the DC test mode/output buffer section 3. It is output as expected.

DC test with LSI tester, especially VOH, IOH.

When testing VOL and IOL, use D type FF31
Write “H” to .

When the Q output of the D-type FF 31 outputs "H", the output terminals 4.5 and 6.7 output "IHIZ" as in the first embodiment.
Since i"L"2 is fixed at "H" and "Lo", the DCC soot time is similarly shortened.

In the above-described embodiment, the DC test mode setting/output buffer section 3 outputs H""L II alternately to the output terminals 4 to 7, but if it is set so that they are not all at the same voltage, for example "H", ° Any combination of ``H'', ``L'', ``'L'', etc. can be substituted.

〔Effect of the invention〕

As explained above, in the present invention, the output voltages of the output terminals are not all at the same level, but are set to "H".

”By fixing it to any level of “L”, the LS
This has the advantage of shortening the DC test time using an I tester.

Bark, OR...OR gate, SL...internal output logic signal, sm...DC test mode setting signal.

Claims (1)

[Claims] A DC test mode setting/output buffer unit inputs the internal output logic signal of the internal logic circuit and the DC test mode setting signal, and sets a predetermined high or low level DC voltage to multiple output terminals in the DC test mode. The integrated circuit comprising: the DC test mode setting/output buffer section having a logic circuit that sets high and low level DC test voltages to the plurality of output terminals in a predetermined order.