JPH0450737B2 - - Google Patents
Info
- Publication number
- JPH0450737B2 JPH0450737B2 JP7946088A JP7946088A JPH0450737B2 JP H0450737 B2 JPH0450737 B2 JP H0450737B2 JP 7946088 A JP7946088 A JP 7946088A JP 7946088 A JP7946088 A JP 7946088A JP H0450737 B2 JPH0450737 B2 JP H0450737B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- voltage
- substrate
- type semiconductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000010408 film Substances 0.000 description 5
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Weting (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本考案は半導体装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device.
近年、半導体装置の加工方法の中で、電気化学
現象を用いたエツチング方法が注目をあびてい
る。その技術は通常、初めに、Ｐ型の半導体基板
の片面に、拡散法、またはエピタキシー成長法な
どを用いて、Ｎ型半導体層を設け、PN接合を形
成した構造の基板を用意する。ついで、Ｎ型半導
体をエツチング溶液中において、陽極酸化反応に
よつてこれに酸化シリコンの膜が生成する程度に
正の電圧を加え、エツチングがＰ型半導体面から
Ｎ型半導体に到つた時に、そのPN接合の界面近
傍に酸化膜を形成せしめ、エツチングをその界面
で停止させるという方法により行われている。し
かし、そのためには外部から電圧を供給する必要
が生じる。第２図に従来用いられてきた基板を示
す。図において、従来は、半導体ウエフアー１１
における主回路部分１２を設けた片面周辺部を取
り巻くように、円形に高濃度拡散領域１３、つま
り低抵抗層を設けることにより、外部配線との接
触抵抗を小さく保つたまま、導通がとれる様に
し、そこに外から所望の電圧および電流を定電圧
電源より供給できるように工夫していた。
In recent years, among methods for processing semiconductor devices, etching methods using electrochemical phenomena have been attracting attention. Generally, in this technique, first, an N-type semiconductor layer is provided on one side of a P-type semiconductor substrate using a diffusion method or an epitaxial growth method, and a substrate having a structure in which a PN junction is formed is prepared. Next, a positive voltage is applied to the N-type semiconductor in an etching solution to the extent that a silicon oxide film is formed on it by an anodic oxidation reaction, and when the etching reaches the N-type semiconductor from the P-type semiconductor surface, the This is done by forming an oxide film near the interface of the PN junction and stopping etching at that interface. However, this requires an external voltage supply. FIG. 2 shows a conventionally used substrate. In the figure, conventionally, a semiconductor wafer 11
By providing a circular high-concentration diffusion region 13, that is, a low-resistance layer, surrounding the periphery of one side where the main circuit portion 12 is provided, conduction can be achieved while keeping the contact resistance with external wiring small. The device was devised so that the desired voltage and current could be supplied from outside using a constant voltage power supply.
ところで、エツチング溶液中でのシリコン酸化
膜の生成は、半導体にかかる電位によつて制御さ
れるので、以上述べた構造においては、円周部分
以外のシリコン部分の電気抵抗は、円周部に比べ
てかなり高いため、円周部から中心部に向うにし
たがつて、外部から供給される電圧とは異なつた
電圧となり、かつ、エツチングの進行とともにシ
リコンの膜厚は減少して行くために、さらに抵抗
値は大きな値に増加し、外部電源による設定電圧
値と各チツプ部分における電圧値の差異は顕著と
なり、中心部分はエツチングがPN接合界面に到
達する以前に、酸化膜が形成され始め、本来なら
エツチングされるべきシリコンの部分がエツチン
グされずに残つてしまい、結局正確なエツチング
が行えないという、深刻な問題点があつた。
By the way, the formation of a silicon oxide film in an etching solution is controlled by the potential applied to the semiconductor, so in the structure described above, the electrical resistance of the silicon portion other than the circumferential portion is lower than that of the circumferential portion. Since the voltage is quite high, the voltage becomes different from the voltage supplied from the outside as you move from the circumference to the center, and the silicon film thickness decreases as etching progresses. The resistance value increases to a large value, and the difference between the set voltage value by the external power supply and the voltage value at each chip part becomes remarkable.In the central part, an oxide film begins to form before the etching reaches the PN junction interface, and the original state In this case, the silicon part that should be etched would remain unetched, resulting in a serious problem in that accurate etching could not be performed.
本発明の目的は、上記従来の問題点を完全に克
服し、確実にシリコンのエツチングが遂行できる
方法を提供することにある。 An object of the present invention is to provide a method that completely overcomes the above-mentioned conventional problems and can reliably perform silicon etching.
上記目的を達成するため、本発明の半導体装置
の製造方法においては、電気化学エツチングを用
いた半導体装置の製造方法において、主電子回路
とは別に作りたい構造物の少なくとも近傍まで基
板の両面に低抵抗層を設け、該低抵抗層を電気化
学エツチングのための電極と接続するものであ
る。
In order to achieve the above object, in the method of manufacturing a semiconductor device of the present invention, in a method of manufacturing a semiconductor device using electrochemical etching, etching is applied to both sides of the substrate up to at least the vicinity of the structure to be formed separately from the main electronic circuit. A resistive layer is provided, and the low resistive layer is connected to an electrode for electrochemical etching.
本発明の電気化学エツチング法は、主回路形成
部分以外の部分に電気化学エツチングに必要とさ
れる電圧および電流を供給するための低抵抗回路
を基板の両面に形成し、これを外部電源と接続す
ることにより、電気化学エツチングにより取り除
こうとする部分の電位を精密に制御することがで
きるようにしている。これによつて、エツチング
が完全に行われ、必要とされる任意の形状にエツ
チングを施すことが可能である。
The electrochemical etching method of the present invention involves forming low resistance circuits on both sides of the substrate to supply the voltage and current required for electrochemical etching to parts other than the main circuit forming part, and connecting these to an external power supply. By doing so, it is possible to precisely control the potential of the portion to be removed by electrochemical etching. This ensures that the etching is complete and that any required shape can be etched.
以下の図面に基づいて、本発明に係わる方法の
最適な実施例を説明する。
A preferred embodiment of the method according to the invention will be explained based on the following drawings.
第１図ａ，ｂはそれぞれ基板１の表面と、裏面
とを示している。２は表面側の主回路部分、３は
裏面側の主回路部分である。主回路部分の各チツ
プの周辺に１ミリメートル程度のスクライブ領域
を設け、そこにイオンプランテイシヨン、もしく
は、拡散法により表面のＰ型半導体層面にはP+
配線４、および裏面のＮ型半導体層面にはN+配
線５を形成する。その後に表面にSiO2などの保
護層を設ける。この導電路の形成は、各半導体チ
ツプに同じ様に電圧が加わる事を促す働きと、外
部との電気回路接続の際に起こる接触抵抗を激減
させる働きを持つている。その後、外部に設けた
定電圧電源に接続し、Ｎ型半導体層から成るエツ
チングによつて作製しようとする構造物を、その
表面において陽極酸化が起こり、SiO2が生成す
る程度に、プラスの電位になるようにN+配線５
を通じて設定する、一方、エツチングによつて切
り取られる、Ｐ型半導体層部分を通常シリコン基
板に対して外から何も電圧を加えないときに、Si
の異方性エツチングが継続して起こる、自然平衡
電位よりもマイナス側になるように、P+配線４
を通じて設定し、エチレンジアミン系、KOH系、
およびヒドラジン系、等のシリコン異方性エツチ
ングが可能な溶液に浸し、90度付近に加温してエ
ツチングを行う。通常Ｐ型半導体層からエツチン
グは行われるが、配線の線材としてアルミのよう
な金属を用いると、それが異方性エツチングの進
行中にサイドエツチングされ、導体としての働き
を失う。又それらのとけた金属は、エツチング液
を汚染しエツチング液の寿命を著しく短くする。
ところが、拡散層を伝導層として用い、表面を
SiO2にて保護しておけば、上記欠点を克服する
ことが可能である。尚、この様に、導電体層を設
けると、従来の方法では円形にシリコンウエフア
ーの外周部を１センチメートル程度N+層の形成
に費やしていたために、チツプの有効作製面積
が、極端に下がる事が認められたが、それを著し
く改良することも可能である。 Figures 1a and 1b show the front and back sides of the substrate 1, respectively. 2 is a main circuit portion on the front side, and 3 is a main circuit portion on the back side. A scribe area of approximately 1 mm is provided around each chip in the main circuit section, and ion implantation or diffusion is applied to the surface of the P-type semiconductor layer .
An N + wiring 5 is formed on the wiring 4 and the N type semiconductor layer surface on the back side. After that, a protective layer such as SiO 2 is provided on the surface. The formation of this conductive path has the function of promoting the application of voltage to each semiconductor chip in the same way, and the function of drastically reducing the contact resistance that occurs when electrical circuits are connected to the outside. After that, it is connected to an external constant voltage power supply, and the structure to be fabricated by etching consisting of the N-type semiconductor layer is heated to a positive potential to the extent that anodic oxidation occurs on the surface and SiO 2 is generated. N + wiring 5 so that
On the other hand, when no voltage is applied externally to the silicon substrate, the P-type semiconductor layer portion cut out by etching is
The P + wiring 4 is set so that the anisotropic etching of the P
Set through, ethylenediamine type, KOH type,
It is immersed in a solution capable of silicon anisotropic etching, such as hydrazine or hydrazine, and etched by heating it to around 90 degrees. Etching is normally performed from the P-type semiconductor layer, but when a metal such as aluminum is used as a wire for wiring, it is side-etched during anisotropic etching and loses its function as a conductor. Also, these melted metals contaminate the etching solution and significantly shorten the life of the etching solution.
However, when the diffusion layer is used as a conductive layer, the surface becomes
By protecting it with SiO 2 , it is possible to overcome the above drawbacks. In addition, when a conductive layer is provided in this way, the effective fabrication area of the chip is extremely reduced, as in the conventional method, approximately 1 cm of the outer circumference of the circular silicon wafer is used to form the N + layer. Although it was observed that there is a decrease in the performance, it is possible to significantly improve it.
図においてスクライブ領域以外の周辺にも導電
体層が設けられているが外部電源に対して接続で
きる場所さえ設ければその部分はなくても構わな
い。 In the figure, a conductive layer is provided in the periphery other than the scribe area, but that part may be omitted as long as a place that can be connected to an external power source is provided.
以上説明したように、本発明によれば、シリコ
ンウエフアーのどの部分にも外から加えた電圧
が、均一にかかる様に制御できるので、エツチン
グによる薄膜形成は、非常に微細な形であつて
も、すべての部分に対して極めて良好であり、全
てのチツプを製品として用いることが可能とな
る。
As explained above, according to the present invention, the voltage applied from the outside can be controlled so as to be uniformly applied to any part of the silicon wafer, so that thin films can be formed by etching in very fine shapes. Also, all parts are extremely good, and all chips can be used as products.
第１図ａは本発明による電気化学エツチングに
使用される半導体基板の平面図、ｂは底面図、第
２図は従来電気化学エツチング使用されていた半
導体基板の平面図である。
１……基板、２……主回路部分、３……主回路
部分、４……P+配線、５……N+配線。
1A is a plan view of a semiconductor substrate used for electrochemical etching according to the present invention, FIG. 1B is a bottom view, and FIG. 2 is a plan view of a semiconductor substrate conventionally used for electrochemical etching. 1...Board, 2...Main circuit part, 3...Main circuit part, 4...P + wiring, 5...N + wiring.
Claims (1)
造方法において、主電子回路とは別に作りたい構
造物の少なくとも近傍まで基板の両面に低抵抗層
を設け、該低抵抗層を電気化学エツチングのため
の電極と接続することを特徴とする半導体装置の
製造方法。1. In a method of manufacturing a semiconductor device using electrochemical etching, a low resistance layer is provided on both sides of a substrate up to at least the vicinity of a structure to be manufactured separately from the main electronic circuit, and the low resistance layer is used as an electrode for electrochemical etching. 1. A method for manufacturing a semiconductor device, characterized in that it is connected to a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7946088A JPH01251619A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7946088A JPH01251619A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01251619A JPH01251619A (en) | 1989-10-06 |
| JPH0450737B2 true JPH0450737B2 (en) | 1992-08-17 |
Family
ID=13690491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7946088A Granted JPH01251619A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01251619A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120081764A (en) * | 2011-01-12 | 2012-07-20 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508038A (en) * | 1990-04-16 | 1996-04-16 | Alza Corporation | Polyisobutylene adhesives for transdermal devices |
-
1988
- 1988-03-30 JP JP7946088A patent/JPH01251619A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120081764A (en) * | 2011-01-12 | 2012-07-20 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01251619A (en) | 1989-10-06 |
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